[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-68-gd269b8c
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-68-gd269b8c
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From: Fabien M <fa...@us...> - 2012-12-06 16:48:21
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via d269b8cab162103a5753c8e5eec5ed0b7bbf6e7b (commit)
via 027125ca394105b5af9bfa67a4ad16a3a9a9623f (commit)
from b04cb6a64247b103defb7faa80830bbc5b296e46 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d269b8cab162103a5753c8e5eec5ed0b7bbf6e7b
Merge: 027125c b04cb6a
Author: Fabien Marteau <fab...@ar...>
Date: Thu Dec 6 17:48:06 2012 +0100
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit 027125ca394105b5af9bfa67a4ad16a3a9a9623f
Author: Fabien Marteau <fab...@ar...>
Date: Thu Dec 6 16:35:53 2012 +0100
[debug][imxregs] adding some registers for apf51
-----------------------------------------------------------------------
Summary of changes:
target/linux/debug/imxregs/imx5regs.h | 41 +++++++++++++++++++++++++++++++++
1 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/target/linux/debug/imxregs/imx5regs.h b/target/linux/debug/imxregs/imx5regs.h
index 543133d..21b9557 100644
--- a/target/linux/debug/imxregs/imx5regs.h
+++ b/target/linux/debug/imxregs/imx5regs.h
@@ -137,6 +137,30 @@ static struct reg_info regs[] =
{ "GPIO1_IMR", 0x73f84014, 0, 0xffffffff, 'x', "GPIO Bank1 Interrupt Mask Register" },
{ "GPIO1_ISR", 0x73f84018, 0, 0xffffffff, 'x', "GPIO Bank1 Interrupt Status Register" },
{ "GPIO1_EDGE", 0x73f8401c, 0, 0xffffffff, 'x', "GPIO Bank1 Edge Detect Register" },
+{ "GPIO2_DR", 0x73f88000, 0, 0xffffffff, 'x', "GPIO Bank2 Data Register" },
+{ "GPIO2_DIR", 0x73f88004, 0, 0xffffffff, 'x', "GPIO Bank2 Direction Register" },
+{ "GPIO2_PSR", 0x73f88008, 0, 0xffffffff, 'x', "GPIO Bank2 Pad Status Register" },
+{ "GPIO2_ICR1", 0x73f8800c, 0, 0xffffffff, 'x', "GPIO Bank2 Interrupt Configuration Register 1" },
+{ "GPIO2_ICR2", 0x73f88010, 0, 0xffffffff, 'x', "GPIO Bank2 Interrupt Configuration Register 2" },
+{ "GPIO2_IMR", 0x73f88014, 0, 0xffffffff, 'x', "GPIO Bank2 Interrupt Mask Register" },
+{ "GPIO2_ISR", 0x73f88018, 0, 0xffffffff, 'x', "GPIO Bank2 Interrupt Status Register" },
+{ "GPIO2_EDGE", 0x73f8801c, 0, 0xffffffff, 'x', "GPIO Bank2 Edge Detect Register" },
+{ "GPIO3_DR", 0x73f8C000, 0, 0xffffffff, 'x', "GPIO Bank3 Data Register" },
+{ "GPIO3_DIR", 0x73f8C004, 0, 0xffffffff, 'x', "GPIO Bank3 Direction Register" },
+{ "GPIO3_PSR", 0x73f8C008, 0, 0xffffffff, 'x', "GPIO Bank3 Pad Status Register" },
+{ "GPIO3_ICR1", 0x73f8C00c, 0, 0xffffffff, 'x', "GPIO Bank3 Interrupt Configuration Register 1" },
+{ "GPIO3_ICR2", 0x73f8C010, 0, 0xffffffff, 'x', "GPIO Bank3 Interrupt Configuration Register 2" },
+{ "GPIO3_IMR", 0x73f8C014, 0, 0xffffffff, 'x', "GPIO Bank3 Interrupt Mask Register" },
+{ "GPIO3_ISR", 0x73f8C018, 0, 0xffffffff, 'x', "GPIO Bank3 Interrupt Status Register" },
+{ "GPIO3_EDGE", 0x73f8C01c, 0, 0xffffffff, 'x', "GPIO Bank3 Edge Detect Register" },
+{ "GPIO4_DR", 0x73f90000, 0, 0xffffffff, 'x', "GPIO Bank4 Data Register" },
+{ "GPIO4_DIR", 0x73f90004, 0, 0xffffffff, 'x', "GPIO Bank4 Direction Register" },
+{ "GPIO4_PSR", 0x73f90008, 0, 0xffffffff, 'x', "GPIO Bank4 Pad Status Register" },
+{ "GPIO4_ICR1", 0x73f9000c, 0, 0xffffffff, 'x', "GPIO Bank4 Interrupt Configuration Register 1" },
+{ "GPIO4_ICR2", 0x73f90010, 0, 0xffffffff, 'x', "GPIO Bank4 Interrupt Configuration Register 2" },
+{ "GPIO4_IMR", 0x73f90014, 0, 0xffffffff, 'x', "GPIO Bank4 Interrupt Mask Register" },
+{ "GPIO4_ISR", 0x73f90018, 0, 0xffffffff, 'x', "GPIO Bank4 Interrupt Status Register" },
+{ "GPIO4_EDGE", 0x73f9001c, 0, 0xffffffff, 'x', "GPIO Bank4 Edge Detect Register" },
/* GPT */
{ "GPTCR_1", 0x73fa0000, 0, 0xffffffff, 'x', "GPT1 Control Register" },
{ "GPTPR_1", 0x73fa0004, 0, 0xffffffff, 'x', "GPT1 Prescaler Register" },
@@ -162,6 +186,20 @@ static struct reg_info regs[] =
{ "PWMSAR_2", 0x73fb800c, 0, 0xffffffff, 'x', "PWM2 Sample Register" },
{ "PWMPR_2", 0x73fb8010, 0, 0xffffffff, 'x', "PWM2 Period Register" },
{ "PWMCNR_2", 0x73fb8014, 0, 0xffffffff, 'x', "PWM2 Counter Register" },
+/* HSI2C */
+{ "HISADR", 0x70038000, 0, 0xffffffff, 'x', "HS_I2C Slave Address Register R/W 0X0000 39.3.3.1/39-8"},
+{ "HIMADR", 0x70038004, 0, 0xffffffff, 'x', "HS_I2C Master Address Register R/W 0x0000 39.3.3.2/39-9"},
+{ "HICR", 0x70038008, 0, 0xffffffff, 'x', "HS_I2C Control Register R/W 0x0000 39.3.3.3/39-9"},
+{ "HISR", 0x7003800C, 0, 0xffffffff, 'x', "HS_I2C Status Register R/W 0x0002 39.3.3.4/39-12"},
+{ "HIIMR", 0x70038010, 0, 0xffffffff, 'x', "HS_I2C Interrupt Mask Register R/W 0x00FF 39.3.3.5/39-13"},
+{ "HITDR", 0x70038014, 0, 0xffffffff, 'x', "HS_I2C Tx Data Register W 0x0000 39.3.3.6/39-15"},
+{ "HIRDR", 0x70038018, 0, 0xffffffff, 'x', "HS_I2C Rx Data Register R 0x0000 39.3.3.7/39-15"},
+{ "HIFSFDR", 0x7003801C, 0, 0xffffffff, 'x', "HS_I2C F/S-Mode Frequency Divider Register R/W 0x0000 39.3.3.8/39-16"},
+{ "HIHSFDR", 0x70038020, 0, 0xffffffff, 'x', "HS_I2C HS-Mode Frequency Divider Register R/W 0X0000 39.3.3.9/39-17"},
+{ "HITFR", 0x70038024, 0, 0xffffffff, 'x', "HS_I2C Tx FIFO Control/Status Register R/W 0x0000 39.3.3.10/39-18"},
+{ "HIRFR", 0x70038028, 0, 0xffffffff, 'x', "HS_I2C Rx FIFO Control/Status Register R/W 0x0000 39.3.3.11/39-20"},
+{ "HITDCR", 0x7003802C, 0, 0xffffffff, 'x', "HS_I2C Transmit Data Count register R/W 0x00FF 39.3.3.12/39-21"},
+{ "HIRDCR", 0x70038030, 0, 0xffffffff, 'x', "HS_I2C Receive Data Count register R/W 0x00FF 39.3.3.13/39-22"},
/* I2C1 */
{ "IADR_1", 0x83fc8000, 0, 0xffffffff, 'x', "I2C1 Address Register" },
{ "IFDR_1", 0x83fc8004, 0, 0xffffffff, 'x', "I2C1 Frequency Divider Register" },
@@ -329,4 +367,7 @@ static struct reg_info regs[] =
{ "SACCST_3", 0x83fe8050, 0, 0xffffffff, 'x', "SSI3 AC97 Channel Status Register" },
{ "SACCEN_3", 0x83fe8054, 0, 0xffffffff, 'x', "SSI3 AC97 Channel Enable Register" },
{ "SACCDIS_3", 0x83fe8058, 0, 0xffffffff, 'x', "SSI3 AC97 Channel Disable Register" },
+/* IOMUX */
+{ "IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK", 0x73FA81F8, 0, 0xffffffff, 'x', "Mux control for I2C1_CLK pad" },
+{ "IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT", 0x73FA81FC, 0, 0xffffffff, 'x', "Mux control for I2C1_DAT pad" },
};
hooks/post-receive
--
armadeus
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