[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-22-gff2812a
Brought to you by:
sszy
Menu
▾
▴
[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-22-gff2812a
|
From: jorasse <jo...@us...> - 2012-10-28 13:29:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via ff2812af57c2ddde1458512f2fe0a752fef04adb (commit)
via 0eaf5922c0ee45b890f2447ffb69b16bbab02606 (commit)
from 89202041278c6b3c7f25a1f3523a91213aaaf7c2 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ff2812af57c2ddde1458512f2fe0a752fef04adb
Author: Eric Jarrige <eri...@ar...>
Date: Sun Oct 28 14:32:00 2012 +0100
[UBOOT] APF27: 2012.10: update to support the new APF27 patch refactoring
commit 0eaf5922c0ee45b890f2447ffb69b16bbab02606
Author: Philippe Reynes <tr...@ya...>
Date: Sun Oct 28 14:29:27 2012 +0100
[UBOOT] APF27: 2012.10: refactor U-Boot patches to be pushed on the U-Boot mainline - Thanks Trem
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf27/apf27-u-boot-2012.10.h | 474 +------
.../100-SPL:-Add-u-boot-nand-build-option.patch | 30 +
...tant-to-support-the-armadeus-APF27-board.patch} | 2 +-
...-Add-support-for-the-armadeus-apf27-board.patch | 739 ----------
...-add-support-for-the-armadeus-APF27-board.patch | 1456 ++++++++++++++++++++
...303-apf27:-Add-spl-support-for-the-apf27.patch} | 336 ++---
...27:-Add-FPGA-support-for-the-apf27-board.patch} | 179 ++--
.../u-boot/2012.10/340-apf27-misc-commands.patch | 14 +-
8 files changed, 1745 insertions(+), 1485 deletions(-)
create mode 100644 patches/u-boot/2012.10/100-SPL:-Add-u-boot-nand-build-option.patch
rename patches/u-boot/2012.10/{301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch => 301-imx27:-Add-missing-constant-to-support-the-armadeus-APF27-board.patch} (99%)
delete mode 100644 patches/u-boot/2012.10/302-Add-support-for-the-armadeus-apf27-board.patch
create mode 100644 patches/u-boot/2012.10/302-apf27:-add-support-for-the-armadeus-APF27-board.patch
rename patches/u-boot/2012.10/{303-Add-nand-spl-support-on-apf27.patch => 303-apf27:-Add-spl-support-for-the-apf27.patch} (62%)
rename patches/u-boot/2012.10/{304-Add-FPGA-support-apf27.patch => 304-apf27:-Add-FPGA-support-for-the-apf27-board.patch} (60%)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.10.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.10.h
index c6f570c..da1cb11 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.10.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.10.h
@@ -24,7 +24,7 @@
#define __CONFIG_H
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "3.3"
+#define CONFIG_ENV_VERSION "3.3"
#define CONFIG_IDENT_STRING " apf27 patch 3.8"
#define CONFIG_BOARD_NAME apf27
@@ -33,13 +33,14 @@
*/
#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
-#define CONFIG_MACH_TYPE 1698 /* APF27 */
+#define CONFIG_MACH_TYPE 1698 /* APF27 */
/*
* Enable the call to miscellaneous platform dependent initialization.
*/
#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
/*
* Board display option
@@ -50,11 +51,24 @@
/*
* SPL
*/
-#define CONFIG_NAND_U_BOOT
/* Copy SPL+U-Boot here */
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_TEXT_BASE - 0x800)
/* Size is the partion size */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
+#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
+/* Build image with spl and u-boot */
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_SPL_PAD_TO 0xa1000000
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH "board/armadeus/apf27"
+#define CONFIG_SPL_LDSCRIPT "board/armadeus/apf27/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
/*
* BOOTP options
@@ -67,8 +81,8 @@
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
-#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
-#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root"
+#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
+#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root"
/*
* U-Boot Commands
@@ -78,17 +92,14 @@
#define CONFIG_CMD_ASKENV /* ask for env variable */
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
-/*#define CONFIG_CMD_DATE */ /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_DNS
-/*#define CONFIG_CMD_EEPROM */ /* EEPROM read/write support */
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT /* FAT support */
-/*#define CONFIG_CMD_I2C */ /* I2C serial bus support */
#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_CMD_MMC
-#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_CMD_NAND_TRIMFFS
@@ -104,10 +115,10 @@
#define CONFIG_NR_DRAM_POPULATED 1
#define CONFIG_NR_DRAM_BANKS 2
-#define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
+#define ACFG_SDRAM_MBYTE_SYZE 64
-#define PHYS_SDRAM_1 0xA0000000
-#define PHYS_SDRAM_2 0xB0000000
+#define PHYS_SDRAM_1 0xA0000000
+#define PHYS_SDRAM_2 0xB0000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
@@ -121,8 +132,7 @@
/*
* FLASH organization
*/
-/*#define CONFIG_SYS_MONITOR_BASE 0xAFF00000*/
-#define CONFIG_SYS_MONITOR_OFFSET 0x00000000
+#define ACFG_MONITOR_OFFSET 0x00000000
#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OVERWRITE
@@ -153,7 +163,7 @@
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE \
+#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 16 /* max command args */
@@ -168,17 +178,16 @@
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
#define CONFIG_INITRD_TAG /* send initrd params */
-/* #define CONFIG_REVISION_TAG */
#define CONFIG_OF_LIBFDT
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
-#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
- MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
+#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
+ MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
" ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
#define ACFG_CONSOLE_DEV ttySMX0
@@ -198,7 +207,7 @@
"consoledev=" MK_STR(ACFG_CONSOLE_DEV) "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"partition=nand0,6\0" \
- "u-boot_addr=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0" \
+ "u-boot_addr=" MK_STR(ACFG_MONITOR_OFFSET) "\0" \
"env_addr=" MK_STR(CONFIG_ENV_OFFSET) "\0" \
"firmware_addr=" MK_STR(CONFIG_FIRMWARE_OFFSET) "\0" \
"kernel_addr=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \
@@ -210,7 +219,7 @@
"addubifsargs=setenv bootargs ${bootargs} " \
"ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
"addmmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
+ "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
"addipargs=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"${hostname}:eth0:off \0" \
@@ -247,7 +256,7 @@
"else echo Flashing of uboot failed;" \
"fi; \0" \
"flash_firmware=nand erase.part firmware;" \
- "if nand write.trimffs ${fileaddr} ${firmware_addr} ${filesize};"\
+ "if nand write.trimffs ${fileaddr} ${firmware_addr} ${filesize};"\
"then echo Flashing of Firmware succeed;" \
"else echo Flashing of Firmware failed;" \
"fi\0" \
@@ -285,7 +294,7 @@
*/
#define CONFIG_MXC_UART
#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
#define CONFIG_MXC_UART_BASE UART1_BASE
/*
@@ -351,20 +360,6 @@
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
#define CONFIG_SYS_FPGA_CHECK_ERROR
-//#define CONFIG_SYS_FPGA_IS_PROTO /* to be defined with apf27 board prototype*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */
-#define CONFIG_SYS_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */
-#define CONFIG_SYS_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */
-#define CONFIG_SYS_FPGA_RDATA 0xD6000000 /* FPGA data addr */
-#define CONFIG_SYS_FPGA_WDATA 0xD6000000 /* FPGA data addr */
-#define CONFIG_SYS_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
-#define CONFIG_SYS_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */
-#define CONFIG_SYS_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
-#define CONFIG_SYS_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
-#define CONFIG_SYS_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
-#define CONFIG_SYS_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
/*
* Fuses - IIM
@@ -388,7 +383,7 @@
#define CONFIG_I2C_CMD_TREE
#define CONFIG_I2C_MULTI_BUS 2
-#define CONFIG_SYS_I2C_NOPROBES { }
+#define CONFIG_SYS_I2C_NOPROBES { }
#ifdef CONFIG_CMD_EEPROM
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
@@ -442,415 +437,22 @@
#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
#undef CONFIG_MX27_CLK26 /* No external 26MHz external clock */
-/* MPU CLOCK source before PLL */
-/* CONFIG_SYS_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) */
-#ifndef CONFIG_MX27_CLK26
-#if (CONFIG_MX27_CLK32 == 32000)
-#define CONFIG_SYS_MPCTL0_VAL 0x00211803 /* 398.998 MHz */
-#define CONFIG_SYS_MPCTL1_VAL 0
-#define CONFIG_MPLL_FREQ 399
-#else /* CONFIG_MX27_CLK32 == 32768*/
-#define CONFIG_SYS_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
-#define CONFIG_SYS_MPCTL1_VAL 0
-#define CONFIG_MPLL_FREQ 399
-#endif /* CONFIG_MX27_CLK32 */
-#else /* CONFIG_MX27_CLK26 in use*/
-#define CONFIG_SYS_MPCTL0_VAL 0x00331C23 /* 399.000 MHz */
-#define CONFIG_SYS_MPCTL1_VAL 0
-#define CONFIG_MPLL_FREQ 399
-#endif /* CONFIG_MX27_CLK26 */
-
-#define CONFIG_SYS_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
-
-/* Serial clock source before PLL (should be named CONFIG_SYS_SYSPLL_CLK_FREQ)*/
-#ifndef CONFIG_MX27_CLK26
-/*#define CONFIG_SYSPLL_CLK_FREQ (1024*CONFIG_MX27_CLK32)*/
-#if (CONFIG_MX27_CLK32 == 32000)
-#define CONFIG_SYS_SPCTL0_VAL 0x04A02419 /* 300.00020 MHz */
-#define CONFIG_SYS_SPCTL1_VAL 0
-#define CONFIG_SPLL_FREQ 300 /* MHz */
-#else /* CONFIG_MX27_CLK32 == 32768*/
-#define CONFIG_SYS_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
-#define CONFIG_SYS_SPCTL1_VAL 0
-#define CONFIG_SPLL_FREQ 300 /* MHz */
-#endif /* CONFIG_MX27_CLK32 */
-#else /* CONFIG_MX27_CLK26 in use*/
-/*#define CONFIG_SYSPLL_CLK_FREQ CONFIG_MX27_CLK26*/
-#define CONFIG_SYS_SPCTL0_VAL 0x040C2C07 /* 300 MHz */
-#define CONFIG_SYS_SPCTL1_VAL 0x0
-#define CONFIG_SPLL_FREQ 300 /* MHz */
-#endif /* CONFIG_MX27_CLK26 */
-
-/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
-#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
-
-/* external bus frequency (have to be a CONFIG_SYS_CLK_FREQ ratio) */
-#define CONFIG_HCLK_FREQ 133 /* (CONFIG_SYS_CLK_FREQ/2) */
-
-#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM*/
-#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC*/
-#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD*/
-#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI*/
-#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1*/
-#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2*/
-#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC*/
-#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264*/
-#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */
-#define CONFIG_CLK0_EN 1 /* CLK0 enabled */
-
-/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
-#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz*/
-
-/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
-#define CONFIG_USB_FREQ 60 /* 60 MHz */
-
-/*
- * SDRAM
- */
-#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
/* micron 64MB */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
-#define CONFIG_SYS_SDRAM_NUM_ROW 13 /* 11, 12 or 13 row address bits */
-#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power down delay */
-#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read cycle delay > 0 */
-#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
-#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register cycle delay 1..4 */
-#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; SDRAM: 0=1ck 1=2ck*/
-#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
-#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
-#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
-#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC refresh to command)*/
-#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time estimated fo CL=1 0=force 3 for lpddr*/
-#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 3=Eighth 4=Sixteenth */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 2=quater 3=Eighth */
-#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
#endif
-#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 128)
+#if (ACFG_SDRAM_MBYTE_SYZE == 128)
/* micron 128MB */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
-#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
-#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 row address bits */
-#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power down delay */
-#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read cycle delay > 0 */
-#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
-#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register cycle delay 1..4 */
-#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; SDRAM: 0=1ck 1=2ck*/
-#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
-#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
-#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
-#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC refresh to command)*/
-#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time estimated fo CL=1 0=force 3 for lpddr*/
-#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 3=Eighth 4=Sixteenth */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 2=quater 3=Eighth */
-#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
#endif
-#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 256)
+#if (ACFG_SDRAM_MBYTE_SYZE == 256)
/* micron 256MB */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
-#define CONFIG_SYS_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 column address bits */
-#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 row address bits */
-#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power down delay */
-#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read cycle delay > 0 */
-#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
-#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register cycle delay 1..4 */
-#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; SDRAM: 0=1ck 1=2ck*/
-#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
-#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
-#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
-#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC refresh to command)*/
-#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time estimated fo CL=1 0=force 3 for lpddr*/
-#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 3=Eighth 4=Sixteenth */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 2=quater 3=Eighth */
-#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
-#endif
-
-/*
- * External interface
- */
-/*
- * CSCRxU_VAL:
- * 31| x | x | x x |x x x x| x x | x | x |x x x x|16
- * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL |
- *
- * 15| x x | x x x x x x | x | x x x x | x x x x |0
- * | CNC | WSC |EW | WWS | EDC |
- *
- * CSCRxL_VAL:
- * 31| x x x x | x x x x | x x x x | x x x x |16
- * | OEA | OEN | EBWA | EBWN |
- * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0
- * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN|
- *
- * CSCRxA_VAL:
- * 31| x x x x | x x x x | x x x x | x x x x |16
- * | EBRA | EBRN | RWA | RWN |
- * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0
- * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE|
- */
-
-/* CS0 configuration for 16 bit nor flash */
-#define CONFIG_SYS_CS0U_VAL 0x0000CC03
-#define CONFIG_SYS_CS0L_VAL 0xa0330D01
-#define CONFIG_SYS_CS0A_VAL 0x00220800
-
-#define CONFIG_SYS_CS1U_VAL 0x00000f00
-#define CONFIG_SYS_CS1L_VAL 0x00000D01
-#define CONFIG_SYS_CS1A_VAL 0
-
-#define CONFIG_SYS_CS2U_VAL 0
-#define CONFIG_SYS_CS2L_VAL 0
-#define CONFIG_SYS_CS2A_VAL 0
-
-#define CONFIG_SYS_CS3U_VAL 0
-#define CONFIG_SYS_CS3L_VAL 0
-#define CONFIG_SYS_CS3A_VAL 0
-
-#define CONFIG_SYS_CS4U_VAL 0
-#define CONFIG_SYS_CS4L_VAL 0
-#define CONFIG_SYS_CS4A_VAL 0
-
-/* FPGA 16 bit data bus */
-#define CONFIG_SYS_CS5U_VAL 0x00000600
-#define CONFIG_SYS_CS5L_VAL 0x00000D01
-#define CONFIG_SYS_CS5A_VAL 0
-
-#define CONFIG_SYS_EIM_VAL 0x00002200
-
-/* FPGA specific settings */
-/* CLKO */
-#define CONFIG_SYS_CCSR_VAL 0x00000305
-/* drive strength CLKO set to 2*/
-#define CONFIG_SYS_DSCR10_VAL 0x00020000
-/* drive strength A1..A12 set to 2*/
-#define CONFIG_SYS_DSCR3_VAL 0x02AAAAA8
-/* drive strength ctrl*/
-#define CONFIG_SYS_DSCR7_VAL 0x00020880
-/* drive strength data*/
-#define CONFIG_SYS_DSCR2_VAL 0xAAAAAAAA
-
-
-/*
- * Default configuration for GPIOs and peripherals
- */
-#define CONFIG_SYS_DDIR_A_VAL 0x00000000
-#define CONFIG_SYS_OCR1_A_VAL 0x00000000
-#define CONFIG_SYS_OCR2_A_VAL 0x00000000
-#define CONFIG_SYS_ICFA1_A_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFA2_A_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB1_A_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB2_A_VAL 0xFFFFFFFF
-#define CONFIG_SYS_DR_A_VAL 0x00000000
-#define CONFIG_SYS_GIUS_A_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICR1_A_VAL 0x00000000
-#define CONFIG_SYS_ICR2_A_VAL 0x00000000
-#define CONFIG_SYS_IMR_A_VAL 0x00000000
-#define CONFIG_SYS_GPR_A_VAL 0x00000000
-#define CONFIG_SYS_PUEN_A_VAL 0xFFFFFFFF
-
-#define CONFIG_SYS_DDIR_B_VAL 0x00000000
-#define CONFIG_SYS_OCR1_B_VAL 0x00000000
-#define CONFIG_SYS_OCR2_B_VAL 0x00000000
-#define CONFIG_SYS_ICFA1_B_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFA2_B_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB1_B_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB2_B_VAL 0xFFFFFFFF
-#define CONFIG_SYS_DR_B_VAL 0x00000000
-#define CONFIG_SYS_GIUS_B_VAL 0xFF3FFFF0
-#define CONFIG_SYS_ICR1_B_VAL 0x00000000
-#define CONFIG_SYS_ICR2_B_VAL 0x00000000
-#define CONFIG_SYS_IMR_B_VAL 0x00000000
-#define CONFIG_SYS_GPR_B_VAL 0x00000000
-#define CONFIG_SYS_PUEN_B_VAL 0xFFFFFFFF
-
-#define CONFIG_SYS_DDIR_C_VAL 0x00000000
-#define CONFIG_SYS_OCR1_C_VAL 0x00000000
-#define CONFIG_SYS_OCR2_C_VAL 0x00000000
-#define CONFIG_SYS_ICFA1_C_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFA2_C_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB1_C_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB2_C_VAL 0xFFFFFFFF
-#define CONFIG_SYS_DR_C_VAL 0x00000000
-#define CONFIG_SYS_GIUS_C_VAL 0xFFFFC07F
-#define CONFIG_SYS_ICR1_C_VAL 0x00000000
-#define CONFIG_SYS_ICR2_C_VAL 0x00000000
-#define CONFIG_SYS_IMR_C_VAL 0x00000000
-#define CONFIG_SYS_GPR_C_VAL 0x00000000
-#define CONFIG_SYS_PUEN_C_VAL 0xFFFFFF87
-
-#define CONFIG_SYS_DDIR_D_VAL 0x00000000
-#define CONFIG_SYS_OCR1_D_VAL 0x00000000
-#define CONFIG_SYS_OCR2_D_VAL 0x00000000
-#define CONFIG_SYS_ICFA1_D_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFA2_D_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB1_D_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB2_D_VAL 0xFFFFFFFF
-#define CONFIG_SYS_DR_D_VAL 0x00000000
-#define CONFIG_SYS_GIUS_D_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICR1_D_VAL 0x00000000
-#define CONFIG_SYS_ICR2_D_VAL 0x00000000
-#define CONFIG_SYS_IMR_D_VAL 0x00000000
-#define CONFIG_SYS_GPR_D_VAL 0x00000000
-#define CONFIG_SYS_PUEN_D_VAL 0xFFFFFFFF
-
-#define CONFIG_SYS_DDIR_E_VAL 0x00000000
-#define CONFIG_SYS_OCR1_E_VAL 0x00000000
-#define CONFIG_SYS_OCR2_E_VAL 0x00000000
-#define CONFIG_SYS_ICFA1_E_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFA2_E_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB1_E_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB2_E_VAL 0xFFFFFFFF
-#define CONFIG_SYS_DR_E_VAL 0x00000000
-#define CONFIG_SYS_GIUS_E_VAL 0xFCFFCCF8
-#define CONFIG_SYS_ICR1_E_VAL 0x00000000
-#define CONFIG_SYS_ICR2_E_VAL 0x00000000
-#define CONFIG_SYS_IMR_E_VAL 0x00000000
-#define CONFIG_SYS_GPR_E_VAL 0x00000000
-#define CONFIG_SYS_PUEN_E_VAL 0xFFFFFFFF
-
-#define CONFIG_SYS_DDIR_F_VAL 0x00000000
-#define CONFIG_SYS_OCR1_F_VAL 0x00000000
-#define CONFIG_SYS_OCR2_F_VAL 0x00000000
-#define CONFIG_SYS_ICFA1_F_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFA2_F_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB1_F_VAL 0xFFFFFFFF
-#define CONFIG_SYS_ICFB2_F_VAL 0xFFFFFFFF
-#define CONFIG_SYS_DR_F_VAL 0x00000000
-#define CONFIG_SYS_GIUS_F_VAL 0xFF7F8000
-#define CONFIG_SYS_ICR1_F_VAL 0x00000000
-#define CONFIG_SYS_ICR2_F_VAL 0x00000000
-#define CONFIG_SYS_IMR_F_VAL 0x00000000
-#define CONFIG_SYS_GPR_F_VAL 0x00000000
-#define CONFIG_SYS_PUEN_F_VAL 0xFFFFFFFF
-
-/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
-#define CONFIG_SYS_GPCR_VAL 0x0003000F
-
-#define CONFIG_SYS_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
-
-/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
-#if (CONFIG_NR_DRAM_BANKS == 1)
-#define CONFIG_SYS_FMCR_VAL 0xFFFFFFF9
-#elif (CONFIG_NR_DRAM_BANKS == 2)
-#define CONFIG_SYS_FMCR_VAL 0xFFFFFFFB
-#endif
-
-#define CONFIG_SYS_AIPI1_PSR0_VAL 0x20040304
-#define CONFIG_SYS_AIPI1_PSR1_VAL 0xDFFBFCFB
-#define CONFIG_SYS_AIPI2_PSR0_VAL 0x00000000
-#define CONFIG_SYS_AIPI2_PSR1_VAL 0xFFFFFFFF
-
-/* PCCR enable DMA FEC I2C1 IIM SDHC1 */
-#define CONFIG_SYS_PCCR0_VAL 0x05070410
-#define CONFIG_SYS_PCCR1_VAL 0xA14A0608
-
-/*
- * From here, there should not be any user configuration.
- * All Equations are automatic
- */
-
-/* fixme none integer value (7.5ns) => 2*hclock = 15ns */
-#define CONFIG_SYS_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */
-
-/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/
-#ifdef CONFIG_MX27_CLK26
-#define CSCR_MASK 0x0303800D
-#else
-#define CSCR_MASK 0x0300800D
#endif
-#define CONFIG_SYS_CSCR_VAL\
- (CSCR_MASK \
- |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07)<<28) \
- |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03)<<12) \
- |((((CONFIG_SYS_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03)<<8))
-
-/* SSIx CLKO NFC H264 MSHC */
-#define CONFIG_SYS_PCDR0_VAL\
- (((((CONFIG_SYS_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \
- |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \
- |(((((CONFIG_SYS_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\
- |(((((CONFIG_SYS_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\
- |(((CONFIG_CLK0_DIV)&0x07)<<22)\
- |(((CONFIG_CLK0_EN)&0x01)<<25)\
- |(((((CONFIG_SYS_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26))
-
-/* PERCLKx */
-#define CONFIG_SYS_PCDR1_VAL\
- (((((CONFIG_SYS_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \
- |((((CONFIG_SYS_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \
- |((((CONFIG_SYS_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \
- |((((CONFIG_SYS_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24))
-
-/* SDRAM controller programming Values */
-#if (((2*CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1)>(3*CONFIG_SYS_2XHCLK_LGTH))\
- ||(CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1<1))
-#define REG_FIELD_SCL_VAL 3
-#define REG_FIELD_SCLIMX_VAL 0
-#else
-#define REG_FIELD_SCL_VAL\
- ((2*CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1+CONFIG_SYS_2XHCLK_LGTH-1)/CONFIG_SYS_2XHCLK_LGTH)
-#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL
-#endif
-
-//#define REG_FIELD_SCL_VAL 3
-//#define REG_FIELD_SCLIMX_VAL 3
-
-#if ((2*CONFIG_SYS_SDRAM_RC_DELAY)>(16*CONFIG_SYS_2XHCLK_LGTH))
-#define REG_FIELD_SRC_VAL 0
-#else
-#define REG_FIELD_SRC_VAL\
- ((2*CONFIG_SYS_SDRAM_RC_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/CONFIG_SYS_2XHCLK_LGTH)
-#endif
-
-/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/
-#define REG_ESDCTL_BASE_CONFIG (0x80020485\
- | (((CONFIG_SYS_SDRAM_NUM_ROW-11)&0x7)<<24)\
- | (((CONFIG_SYS_SDRAM_NUM_COL-8)&0x3)<<20)\
- | (((CONFIG_SYS_SDRAM_REFRESH)&0x7)<<13))
-
-#define CONFIG_SYS_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG)
-#define CONFIG_SYS_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG)
-#define CONFIG_SYS_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG)
-#define CONFIG_SYS_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG)
-
-/* ESDRAMC Configuration Registers : force CL=3 to lpddr */
-#define CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL (0x0\
- | (((((2*CONFIG_SYS_SDRAM_EXIT_PWD+CONFIG_SYS_2XHCLK_LGTH-1)/CONFIG_SYS_2XHCLK_LGTH)-1)&0x3)<<21)\
- | (((CONFIG_SYS_SDRAM_W2R_DELAY-1)&0x1)<<20)\
- | (((((2*CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/CONFIG_SYS_2XHCLK_LGTH)-1)&0x3)<<18)\
- | (((CONFIG_SYS_SDRAM_TMRD_DELAY-1)&0x3)<<16)\
- | (((CONFIG_SYS_SDRAM_TWR_DELAY)&0x1)<<15)\
- | (((((2*CONFIG_SYS_SDRAM_RAS_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/CONFIG_SYS_2XHCLK_LGTH)-1)&0x7)<<12)\
- | (((((2*CONFIG_SYS_SDRAM_RRD_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/CONFIG_SYS_2XHCLK_LGTH)-1)&0x3)<<10)\
- | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\
- | (((((2*CONFIG_SYS_SDRAM_RCD_DELAY+CONFIG_SYS_2XHCLK_LGTH-1)/CONFIG_SYS_2XHCLK_LGTH)-1)&0x7)<<4)\
- | (((REG_FIELD_SRC_VAL)&0x0F)<<0))
-
-/* Issue Mode register Command to SDRAM*/
-#define CONFIG_SYS_SDRAM_MODE_REGISTER_VAL\
- ((((CONFIG_SYS_SDRAM_BURST_LENGTH)&0x7)<<(0))\
- | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\
- | ((0)<<(3)) /* sequentiql access */ \
- /*| (((CONFIG_SYS_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/)
-
-/* Issue Extended Mode register Command to SDRAM*/
-#define CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL\
- ((CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR<<0)\
- | (CONFIG_SYS_SDRAM_DRIVE_STRENGH<<(5))\
- | (1<<(CONFIG_SYS_SDRAM_NUM_COL+CONFIG_SYS_SDRAM_NUM_ROW+1+2)))
-
-/* Issue Precharge all Command to SDRAM*/
-#define CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL (1<<10)
#endif /* __CONFIG_H */
diff --git a/patches/u-boot/2012.10/100-SPL:-Add-u-boot-nand-build-option.patch b/patches/u-boot/2012.10/100-SPL:-Add-u-boot-nand-build-option.patch
new file mode 100644
index 0000000..21e74fb
--- /dev/null
+++ b/patches/u-boot/2012.10/100-SPL:-Add-u-boot-nand-build-option.patch
@@ -0,0 +1,30 @@
+SPL: Add u-boot-nand build option
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+
+---
+ Makefile | 5 +++++
+ 1 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/Makefile b/Makefile
+index 08eecbb..00c9422 100644
+--- a/Makefile
++++ b/Makefile
+@@ -554,8 +554,14 @@ $(obj)u-boot.lds: $(LDSCRIPT)
+ nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C nand_spl/board/$(BOARDDIR) all
+
++ifeq ($(CONFIG_SPL),y)
++$(obj)u-boot-nand.bin: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
++ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin && \
++ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
++else
+ $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
+ cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
++endif
+
+ $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
+ $(MAKE) -C spl all
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.10/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch b/patches/u-boot/2012.10/301-imx27:-Add-missing-constant-to-support-the-armadeus-APF27-board.patch
similarity index 99%
rename from patches/u-boot/2012.10/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
rename to patches/u-boot/2012.10/301-imx27:-Add-missing-constant-to-support-the-armadeus-APF27-board.patch
index 8bb64e7..6f1f1bb 100644
--- a/patches/u-boot/2012.10/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
+++ b/patches/u-boot/2012.10/301-imx27:-Add-missing-constant-to-support-the-armadeus-APF27-board.patch
@@ -1,4 +1,4 @@
-Add WEIM, NFC SYSTEM_CTL constants to the mx27 CPU
+imx27: add missing constant to support the armadeus APF27 board
Signed-off-by: Philippe Reynes <tr...@ya...>
Signed-off-by: Eric Jarrige <eri...@ar...>
diff --git a/patches/u-boot/2012.10/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2012.10/302-Add-support-for-the-armadeus-apf27-board.patch
deleted file mode 100644
index d49e642..0000000
--- a/patches/u-boot/2012.10/302-Add-support-for-the-armadeus-apf27-board.patch
+++ /dev/null
@@ -1,739 +0,0 @@
-Add support for the armadeus APF27 board
-
-Signed-off-by: Philippe Reynes <tr...@ya...>
-Signed-off-by: Eric Jarrige <eri...@ar...>
-Signed-off-by: Nicolas Colombain <nic...@ar...>
----
- board/armadeus/apf27/Makefile | 52 ++++++
- board/armadeus/apf27/apf27.c | 326 ++++++++++++++++++++++++++++++++++
- board/armadeus/apf27/config.mk | 38 ++++
- board/armadeus/apf27/lowlevel_init.S | 275 ++++++++++++++++++++++++++++
- boards.cfg | 1 +
- 5 files changed, 692 insertions(+), 0 deletions(-)
- create mode 100644 board/armadeus/apf27/Makefile
- create mode 100644 board/armadeus/apf27/apf27.c
- create mode 100644 board/armadeus/apf27/config.mk
- create mode 100644 board/armadeus/apf27/lowlevel_init.S
-
-diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
-new file mode 100644
-index 0000000..fe6ba5c
---- /dev/null
-+++ b/board/armadeus/apf27/Makefile
-@@ -0,0 +1,52 @@
-+#
-+# (C) Copyright 2000-2004
-+# Wolfgang Denk, DENX Software Engineering, wd...@de....
-+# (C) Copyright 2012
-+# Eric Jarrige <eri...@ar...>
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB = $(obj)lib$(BOARD).o
-+
-+COBJS := apf27.o
-+SOBJS := lowlevel_init.o
-+
-+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-+OBJS := $(addprefix $(obj),$(COBJS))
-+SOBJS := $(addprefix $(obj),$(SOBJS))
-+
-+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-+
-+clean:
-+ rm -f $(SOBJS) $(OBJS)
-+
-+distclean: clean
-+ rm -f $(LIB) core *.bak $(obj).depend
-+
-+#########################################################################
-+
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
-diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
-new file mode 100644
-index 0000000..c1ca6bd
---- /dev/null
-+++ b/board/armadeus/apf27/apf27.c
-@@ -0,0 +1,318 @@
-+/*
-+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
-+ * Copyright (C) 2008-2012 Eric Jarrige <eri...@ar...>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+#include <common.h>
-+#include "crc.h"
-+#include <jffs2/jffs2.h>
-+#include <nand.h>
-+#include <netdev.h>
-+#include <asm/io.h>
-+#include <asm/arch/imx-regs.h>
-+#include <asm/arch/gpio.h>
-+#include <asm/errno.h>
-+#include <environment.h>
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+/*
-+ * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
-+ * custormer use. The APF27 board uses this fuse to store the board revision:
-+ * 0: initial board revision
-+ * 1: first revision - Presence of the second RAM chip on the board is blown in
-+ * fuse bank 1 row 9 bit 0 - No hardware change
-+ * N: to be defined
-+ */
-+u32 get_board_rev(void)
-+{
-+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-+
-+ return readl(&iim->bank[1].fuse_regs[8]);
-+}
-+
-+/*
-+ * Fuse bank 1 row 9 is "reserved for future use" and therefore available for
-+ * custormer use. The APF27 board revision 1 uses the bit 0 to permanently store
-+ * the presence of the second RAM chip
-+ * 0: AFP27 with 1 RAM of 64 MiB
-+ * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
-+ */
-+int get_num_ram_bank(void)
-+{
-+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-+ int nr_dram_banks = 1;
-+
-+ if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
-+ nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
-+ else
-+ nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
-+
-+ return nr_dram_banks;
-+}
-+
-+static void apf27_gpio_init(void)
-+{
-+ struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
-+
-+ /* PORT A */
-+ writel(CONFIG_SYS_DR_A_VAL, ®s->port[PORTA].gpio_dr);
-+ writel(CONFIG_SYS_OCR1_A_VAL, ®s->port[PORTA].ocr1);
-+ writel(CONFIG_SYS_OCR2_A_VAL, ®s->port[PORTA].ocr2);
-+ writel(CONFIG_SYS_ICFA1_A_VAL, ®s->port[PORTA].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_A_VAL, ®s->port[PORTA].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_A_VAL, ®s->port[PORTA].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_A_VAL, ®s->port[PORTA].iconfb2);
-+ writel(CONFIG_SYS_ICR1_A_VAL, ®s->port[PORTA].icr1);
-+ writel(CONFIG_SYS_ICR2_A_VAL, ®s->port[PORTA].icr2);
-+ writel(CONFIG_SYS_IMR_A_VAL, ®s->port[PORTA].imr);
-+ writel(CONFIG_SYS_DDIR_A_VAL, ®s->port[PORTA].gpio_dir);
-+ writel(CONFIG_SYS_GPR_A_VAL, ®s->port[PORTA].gpr);
-+ writel(CONFIG_SYS_PUEN_A_VAL, ®s->port[PORTA].puen);
-+ writel(CONFIG_SYS_GIUS_A_VAL, ®s->port[PORTA].gius);
-+
-+ /* PORT B */
-+ writel(CONFIG_SYS_DR_B_VAL, ®s->port[PORTB].gpio_dr);
-+ writel(CONFIG_SYS_OCR1_B_VAL, ®s->port[PORTB].ocr1);
-+ writel(CONFIG_SYS_OCR2_B_VAL, ®s->port[PORTB].ocr2);
-+ writel(CONFIG_SYS_ICFA1_B_VAL, ®s->port[PORTB].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_B_VAL, ®s->port[PORTB].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_B_VAL, ®s->port[PORTB].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_B_VAL, ®s->port[PORTB].iconfb2);
-+ writel(CONFIG_SYS_ICR1_B_VAL, ®s->port[PORTB].icr1);
-+ writel(CONFIG_SYS_ICR2_B_VAL, ®s->port[PORTB].icr2);
-+ writel(CONFIG_SYS_IMR_B_VAL, ®s->port[PORTB].imr);
-+ writel(CONFIG_SYS_DDIR_B_VAL, ®s->port[PORTB].gpio_dir);
-+ writel(CONFIG_SYS_GPR_B_VAL, ®s->port[PORTB].gpr);
-+ writel(CONFIG_SYS_PUEN_B_VAL, ®s->port[PORTB].puen);
-+ writel(CONFIG_SYS_GIUS_B_VAL, ®s->port[PORTB].gius);
-+
-+ /* PORT C */
-+ writel(CONFIG_SYS_DR_C_VAL, ®s->port[PORTC].gpio_dr);
-+ writel(CONFIG_SYS_OCR1_C_VAL, ®s->port[PORTC].ocr1);
-+ writel(CONFIG_SYS_OCR2_C_VAL, ®s->port[PORTC].ocr2);
-+ writel(CONFIG_SYS_ICFA1_C_VAL, ®s->port[PORTC].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_C_VAL, ®s->port[PORTC].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_C_VAL, ®s->port[PORTC].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_C_VAL, ®s->port[PORTC].iconfb2);
-+ writel(CONFIG_SYS_ICR1_C_VAL, ®s->port[PORTC].icr1);
-+ writel(CONFIG_SYS_ICR2_C_VAL, ®s->port[PORTC].icr2);
-+ writel(CONFIG_SYS_IMR_C_VAL, ®s->port[PORTC].imr);
-+ writel(CONFIG_SYS_DDIR_C_VAL, ®s->port[PORTC].gpio_dir);
-+ writel(CONFIG_SYS_GPR_C_VAL, ®s->port[PORTC].gpr);
-+ writel(CONFIG_SYS_PUEN_C_VAL, ®s->port[PORTC].puen);
-+ writel(CONFIG_SYS_GIUS_C_VAL, ®s->port[PORTC].gius);
-+
-+ /* PORT D */
-+ writel(CONFIG_SYS_DR_D_VAL, ®s->port[PORTD].gpio_dr);
-+ writel(CONFIG_SYS_OCR1_D_VAL, ®s->port[PORTD].ocr1);
-+ writel(CONFIG_SYS_OCR2_D_VAL, ®s->port[PORTD].ocr2);
-+ writel(CONFIG_SYS_ICFA1_D_VAL, ®s->port[PORTD].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_D_VAL, ®s->port[PORTD].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_D_VAL, ®s->port[PORTD].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_D_VAL, ®s->port[PORTD].iconfb2);
-+ writel(CONFIG_SYS_ICR1_D_VAL, ®s->port[PORTD].icr1);
-+ writel(CONFIG_SYS_ICR2_D_VAL, ®s->port[PORTD].icr2);
-+ writel(CONFIG_SYS_IMR_D_VAL, ®s->port[PORTD].imr);
-+ writel(CONFIG_SYS_DDIR_D_VAL, ®s->port[PORTD].gpio_dir);
-+ writel(CONFIG_SYS_GPR_D_VAL, ®s->port[PORTD].gpr);
-+ writel(CONFIG_SYS_PUEN_D_VAL, ®s->port[PORTD].puen);
-+ writel(CONFIG_SYS_GIUS_D_VAL, ®s->port[PORTD].gius);
-+
-+ /* PORT E */
-+ writel(CONFIG_SYS_DR_E_VAL, ®s->port[PORTE].gpio_dr);
-+ writel(CONFIG_SYS_OCR1_E_VAL, ®s->port[PORTE].ocr1);
-+ writel(CONFIG_SYS_OCR2_E_VAL, ®s->port[PORTE].ocr2);
-+ writel(CONFIG_SYS_ICFA1_E_VAL, ®s->port[PORTE].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_E_VAL, ®s->port[PORTE].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_E_VAL, ®s->port[PORTE].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_E_VAL, ®s->port[PORTE].iconfb2);
-+ writel(CONFIG_SYS_ICR1_E_VAL, ®s->port[PORTE].icr1);
-+ writel(CONFIG_SYS_ICR2_E_VAL, ®s->port[PORTE].icr2);
-+ writel(CONFIG_SYS_IMR_E_VAL, ®s->port[PORTE].imr);
-+ writel(CONFIG_SYS_DDIR_E_VAL, ®s->port[PORTE].gpio_dir);
-+ writel(CONFIG_SYS_GPR_E_VAL, ®s->port[PORTE].gpr);
-+ writel(CONFIG_SYS_PUEN_E_VAL, ®s->port[PORTE].puen);
-+ writel(CONFIG_SYS_GIUS_E_VAL, ®s->port[PORTE].gius);
-+
-+ /* PORT F */
-+ writel(CONFIG_SYS_DR_F_VAL, ®s->port[PORTF].gpio_dr);
-+ writel(CONFIG_SYS_OCR1_F_VAL, ®s->port[PORTF].ocr1);
-+ writel(CONFIG_SYS_OCR2_F_VAL, ®s->port[PORTF].ocr2);
-+ writel(CONFIG_SYS_ICFA1_F_VAL, ®s->port[PORTF].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_F_VAL, ®s->port[PORTF].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_F_VAL, ®s->port[PORTF].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_F_VAL, ®s->port[PORTF].iconfb2);
-+ writel(CONFIG_SYS_ICR1_F_VAL, ®s->port[PORTF].icr1);
-+ writel(CONFIG_SYS_ICR2_F_VAL, ®s->port[PORTF].icr2);
-+ writel(CONFIG_SYS_IMR_F_VAL, ®s->port[PORTF].imr);
-+ writel(CONFIG_SYS_DDIR_F_VAL, ®s->port[PORTF].gpio_dir);
-+ writel(CONFIG_SYS_GPR_F_VAL, ®s->port[PORTF].gpr);
-+ writel(CONFIG_SYS_PUEN_F_VAL, ®s->port[PORTF].puen);
-+ writel(CONFIG_SYS_GIUS_F_VAL, ®s->port[PORTF].gius);
-+}
-+
-+static int apf27_devices_init(void)
-+{
-+ struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
-+ int i;
-+ unsigned int mode[] = {
-+ PD0_AIN_FEC_TXD0,
-+ PD1_AIN_FEC_TXD1,
-+ PD2_AIN_FEC_TXD2,
-+ PD3_AIN_FEC_TXD3,
-+ PD4_AOUT_FEC_RX_ER,
-+ PD5_AOUT_FEC_RXD1,
-+ PD6_AOUT_FEC_RXD2,
-+ PD7_AOUT_FEC_RXD3,
-+ PD8_AF_FEC_MDIO,
-+ PD9_AIN_FEC_MDC | GPIO_PUEN,
-+ PD10_AOUT_FEC_CRS,
-+ PD11_AOUT_FEC_TX_CLK,
-+ PD12_AOUT_FEC_RXD0,
-+ PD13_AOUT_FEC_RX_DV,
-+ PD14_AOUT_FEC_CLR,
-+ PD15_AOUT_FEC_COL,
-+ PD16_AIN_FEC_TX_ER,
-+ PF23_AIN_FEC_TX_EN,
-+ PE12_PF_UART1_TXD,
-+ PE13_PF_UART1_RXD,
-+ };
-+
-+ for (i = 0; i < ARRAY_SIZE(mode); i++)
-+ imx_gpio_mode(mode[i]);
-+
-+#ifdef CONFIG_MXC_MMC
-+ mx27_sd2_init_pins();
-+ imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
-+ writel(readl(®s->port[PORTF].gpio_dr) | (1 << 16),
-+ ®s->port[PORTF].gpio_dr);
-+#endif
-+ return 0;
-+}
-+
-+int
-+board_init(void)
-+{
-+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-+
-+ apf27_gpio_init();
-+ apf27_devices_init();
-+
-+ return 0;
-+}
-+
-+int
-+dram_init(void)
-+{
-+ /* dram_init must store complete ramsize in gd->ram_size */
-+ if (get_num_ram_bank() > 1) {
-+ gd->ram_size = PHYS_SDRAM_2 - CONFIG_SYS_SDRAM_BASE
-+ + get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
-+ } else {
-+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
-+ PHYS_SDRAM_1_SIZE);
-+ }
-+
-+ return 0;
-+}
-+
-+void dram_init_banksize(void)
-+{
-+ phys_size_t ramsize = gd->ram_size;
-+
-+ if (get_num_ram_bank() > 1) {
-+ ramsize -= PHYS_SDRAM_2 - CONFIG_SYS_SDRAM_BASE;
-+ }
-+
-+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-+ gd->bd->bi_dram[0].size = ramsize;
-+ gd->ram_size = gd->bd->bi_dram[0].size;
-+
-+ if (CONFIG_NR_DRAM_BANKS > 1) {
-+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-+ if (get_num_ram_bank() > 1) {
-+ gd->bd->bi_dram[1].size = ramsize;
-+ } else {
-+ gd->bd->bi_dram[1].size = 0;
-+ }
-+ gd->ram_size += gd->bd->bi_dram[1].size;
-+ }
-+}
-+
-+/*
-+ * Miscellaneous intialization
-+ */
-+int
-+misc_init_r(void)
-+{
-+ char *s;
-+ u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + \
-+ CONFIG_SYS_MONITOR_LEN);
-+ size_t size = 0;
-+ size_t offset = -1;
-+ char *autoload = getenv("firmware_autoload");
-+ u8 pnum;
-+ struct mtd_device *dev;
-+ struct part_info *part;
-+
-+ /* detect compatibility issue of environment version */
-+ s = getenv("env_version");
-+ if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
-+ char * const vars[] = {"flash_reset_env"};
-+ printf("*** Warning - Environment version change suggests: "
-+ "run flash_reset_env; reset\n");
-+ set_default_vars(1, vars);
-+ }
-+
-+ /* Unlock whole flash but U-Boot */
-+ s = getenv("env_offset");
-+ offset = CONFIG_ENV_OFFSET;
-+ if ((s != NULL) && (0 != strcmp(s, "0")))
-+ offset = simple_strtoul(s, NULL, 16);
-+
-+ if (nand_unlock(&nand_info[0], offset, nand_info[0].size - offset, 0))
-+ printf("NAND flash lock/unlocked failed\n");
-+
-+
-+ return 0;
-+}
-+
-+void
-+show_boot_progress(int status)
-+{
-+#ifdef CONFIG_SHOW_BOOT_PROGRESS
-+#endif
-+ return;
-+}
-+
-+int checkboard(void)
-+{
-+ printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
-+ return 0;
-+}
-+
-+void enable_caches(void)
-+{
-+#ifndef CONFIG_SYS_DCACHE_OFF
-+
-+ dcache_enable();
-+#endif
-+}
-+
-diff --git a/board/armadeus/apf27/config.mk b/board/armadeus/apf27/config.mk
-new file mode 100644
-index 0000000..9713e69
---- /dev/null
-+++ b/board/armadeus/apf27/config.mk
-@@ -0,0 +1,38 @@
-+#
-+# (C) Copyright 2003
-+# Wolfgang Denk, DENX Software Engineering, wd...@de....
-+# (C) Copyright 2012
-+# Eric Jarrige <eri...@ar...>
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+#
-+# This config file is used for compilation of armadeus sources
-+#
-+# You might change location of U-Boot in memory by setting right TEXT_BASE.
-+# This allows for example having one copy located at the end of ram and stored
-+# in flash device and later on while developing use other location to test
-+# the code in RAM device only.
-+#
-+
-+ifndef TEXT_BASE
-+TEXT_BASE = 0xAFF00000
-+endif
-+
-diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
-new file mode 100644
-index 0000000..f5dbbb4
---- /dev/null
-+++ b/board/armadeus/apf27/lowlevel_init.S
-@@ -0,0 +1,275 @@
-+/*
-+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
-+ * Applications Processor Reference Manual, Rev. 0.2".
-+ *
-+ * (C) Copyright 2008-2012 Eric Jarrige <eri...@ar...>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+
-+#include <config.h>
-+#include <version.h>
-+#include <asm/macro.h>
-+#include <asm/arch/imx-regs.h>
-+#include <generated/asm-offsets.h>
-+
-+
-+
-+
-+.macro port_init
-+ write32 FMCR, CONFIG_SYS_FMCR_VAL
-+.endm /* port_init */
-+
-+.macro init_aipi
-+ /*
-+ * setup AIPI1 and AIPI2
-+ */
-+ write32 AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL
-+ write32 AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL
-+ write32 AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL
-+ write32 AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL
-+
-+ /* Change SDRAM signal strengh */
-+ ldr r0, =GPCR
-+ ldr r1, =CONFIG_SYS_GPCR_VAL
-+ ldr r5, [r0]
-+ orr r5, r5, r1
-+ str r5, [r0]
-+
-+.endm /* init_aipi */
-+
-+.macro init_clock
-+ ldr r0, =CSCR
-+ /* disable MPLL/SPLL first */
-+ ldr r1, [r0]
-+ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
-+ str r1, [r0]
-+
-+ /*
-+ * pll clock initialization predefined in apf27.h
-+ */
-+ write32 MPCTL0, CONFIG_SYS_MPCTL0_VAL
-+ write32 SPCTL0, CONFIG_SYS_SPCTL0_VAL
-+
-+ write32 CSCR, CONFIG_SYS_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
-+
-+ /*
-+ * add some delay here
-+ */
-+ mov r1, #0x1000
-+ 1: subs r1, r1, #0x1
-+ bne 1b
-+
-+ /* peripheral clock divider */
-+ write32 PCDR0, CONFIG_SYS_PCDR0_VAL
-+ write32 PCDR1, CONFIG_SYS_PCDR1_VAL
-+
-+ /* Configure PCCR0 and PCCR1 */
-+ write32 PCCR0, CONFIG_SYS_PCCR0_VAL
-+ write32 PCCR1, CONFIG_SYS_PCCR1_VAL
-+
-+
-+.endm /* init_clock */
-+
-+.macro sdram_init
-+ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-+ ldr r0, =IMX_ESD_BASE
-+ ldr r4, =ESDMISC_SDRAM_RDY
-+2: ldr r1, [r0, #ESDMISC_ROF]
-+ ands r1, r1, r4
-+ bpl 2b
-+
-+ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-+ ldr r0, =IMX_ESD_BASE
-+ ldr r4, =CONFIG_SYS_ESDMISC_VAL
-+ orr r1, r4, #ESDMISC_MDDR_DL_RST
-+ str r1, [r0, #ESDMISC_ROF]
-+
-+ /* Hold for more than 200ns */
-+ ldr r1, =0x10000
-+ 1: subs r1, r1, #0x1
-+ bne 1b
-+
-+ str r4, [r0]
-+
-+ /* write32 ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
-+ ldr r0, =IMX_ESD_BASE
-+ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
-+ str r1, [r0, #ESDCFG0_ROF]
-+
-+ /* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
-+ ldr r0, =IMX_ESD_BASE
-+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
-+ str r1, [r0, #ESDCTL0_ROF]
-+
-+ /* writeb(0xA0001000, any value) */
-+ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+ strb r2, [r1]
-+
-+ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
-+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+ str r1, [r0, #ESDCTL0_ROF]
-+
-+ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
-+
-+ ldr r6,=0x7 /* load loop counter */
-+1: str r5,[r4] /* run auto-refresh cycle to array 0 */
-+ subs r6,r6,#1 /* decrease counter value */
-+ bne 1b
-+
-+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
-+ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+ str r1, [r0, #ESDCTL0_ROF]
-+
-+ /* set standard mode register */
-+ ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+ strb r2, [r4]
-+
-+ /* set extended mode register */
-+ ldr r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+ strb r5, [r4]
-+
-+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
-+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
-+ str r1, [r0, #ESDCTL0_ROF]
-+
-+ /* 2nd sdram */
-+ /* write32 ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
-+ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
-+ str r1, [r0, #ESDCFG1_ROF]
-+
-+ /* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
-+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
-+ str r1, [r0, #ESDCTL1_ROF]
-+
-+ /* writeb(0xB0001000, any value) */
-+ ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+ strb r2, [r1]
-+
-+ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
-+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+ str r1, [r0, #ESDCTL1_ROF]
-+
-+ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
-+
-+ ldr r6,=0x7 /* load loop counter */
-+1: str r5,[r4] /* run auto-refresh cycle to array 0 */
-+ subs r6,r6,#1 /* decrease counter value */
-+ bne 1b
-+
-+ /* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
-+ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+ str r1, [r0, #ESDCTL1_ROF]
-+
-+ /* set standard mode register */
-+ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+ strb r2, [r4]
-+
-+ /* set extended mode register */
-+ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+ strb r2, [r4]
-+
-+ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
-+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
-+ str r1, [r0, #ESDCTL1_ROF]
-+.endm /* sdram_init */
-+
-+.globl board_init_lowlevel
-+board_init_lowlevel:
-+.globl lowlevel_init
-+lowlevel_init:
-+
-+ init_aipi
-+
-+ /* configure csx */
-+ write32 CS0U, CONFIG_SYS_CS0U_VAL
-+ write32 CS0L, CONFIG_SYS_CS0L_VAL
-+ write32 CS0A, CONFIG_SYS_CS0A_VAL
-+
-+ write32 CS1U, CONFIG_SYS_CS1U_VAL
-+ write32 CS1L, CONFIG_SYS_CS1L_VAL
-+ write32 CS1A, CONFIG_SYS_CS1A_VAL
-+
-+ write32 CS2U, CONFIG_SYS_CS2U_VAL
-+ write32 CS2L, CONFIG_SYS_CS2L_VAL
-+ write32 CS2A, CONFIG_SYS_CS2A_VAL
-+
-+ write32 CS3U, CONFIG_SYS_CS3U_VAL
-+ write32 CS3L, CONFIG_SYS_CS3L_VAL
-+ write32 CS3A, CONFIG_SYS_CS3A_VAL
-+
-+ write32 CS4U, CONFIG_SYS_CS4U_VAL
-+ write32 CS4L, CONFIG_SYS_CS4L_VAL
-+ write32 CS4A, CONFIG_SYS_CS4A_VAL
-+
-+ write32 CS5U, CONFIG_SYS_CS5U_VAL
-+ write32 CS5L, CONFIG_SYS_CS5L_VAL
-+ write32 CS5A, CONFIG_SYS_CS5A_VAL
-+
-+ write32 EIM, CONFIG_SYS_EIM_VAL
-+
-+ port_init
-+
-+ /* Configure FPGA CLKO */
-+ write32 CCSR, CONFIG_SYS_CCSR_VAL
-+
-+ /* Configure strentgh for FPGA */
-+ write32 DSCR10, CONFIG_SYS_DSCR10_VAL
-+ write32 DSCR3, CONFIG_SYS_DSCR3_VAL
-+ write32 DSCR7, CONFIG_SYS_DSCR7_VAL
-+ write32 DSCR2, CONFIG_SYS_DSCR2_VAL
-+
-+ init_clock
-+
-+ /* skip clock and sdram initialization if we run from ram */
-+ cmp pc, #0xa0000000
-+ bls 1f
-+ cmp pc, #0xc0000000
-+ bhi 1f
-+
-+ b copy2ram
-+1:
-+ sdram_init
-+
-+/* make U-Boot runnable form "almost" anywhere */
-+/* but SYS_TEXT_BASE should be in RAM */
-+copy2ram: /* populate _TEXT_BASE with U-Boot from load addr */
-+ ldr r0, _start_adr
-+ ldr r1, _copy2ram
-+ sub r1, r1, r0
-+ adr r0, copy2ram
-+ sub r0, r0, r1
-+ ldr r1, =CONFIG_SYS_TEXT_BASE
-+ cmp r0, r1
-+ beq end_of_copy2ram /* skip U-Boot copy */
-+ ldr r2, =CONFIG_SYS_MONITOR_LEN
-+ add r2, r2, r0 /* r2 <- source end address */
-+
-+copy_loop:
-+ ldmia r0!, {r9-r10} /* copy from source address [r0] */
-+ stmia r1!, {r9-r10} /* copy to target address [r1] */
-+ cmp r0, r2 /* until source end address [r2] */
-+ blo copy_loop
-+
-+end_of_copy2ram:
-+ mov pc,lr
-+
-+_copy2ram:
-+ .word copy2ram
-+_start_adr:
-+ .word _start /* r12 saved upper lr*/
-+
-diff --git a/boards.cfg b/boards.cfg
-index 8a40643..9df6212 100644
---- a/boards.cfg
-+++ b/boards.cfg
-@@ -77,6 +77,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd
- aspenite arm arm926ejs - Marvell armada100
- gplugd arm arm926ejs - Marvell armada100
- afeb9260 arm arm926ejs - - at91
-+apf27 arm arm926ejs apf27 armadeus mx27
- at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
- at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
- at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
---
-1.7.2.5
-
diff --git a/patches/u-boot/2012.10/302-apf27:-add-support-for-the-armadeus-APF27-board.patch b/patches/u-boot/2012.10/302-apf27:-add-support-for-the-armadeus-APF27-board.patch
new file mode 100644
index 0000000..2b90aec
--- /dev/null
+++ b/patches/u-boot/2012.10/302-apf27:-add-support-for-the-armadeus-APF27-board.patch
@@ -0,0 +1,1456 @@
+Add support for the armadeus APF27 board
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Nicolas Colombain <nic...@ar...>
+---
+ create mode 100644 board/armadeus/apf27/Makefile
+ create mode 100644 board/armadeus/apf27/apf27.c
+ create mode 100644 board/armadeus/apf27/apf27.h
+ create mode 100644 include/configs/apf27.h
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 1b2da94..297467a 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -1011,6 +1011,11 @@ Nobuhiro Iwamatsu <nob...@re...>
+
+ armadillo-800eva R8A7740 (RMOBILE SoC)
+
++Eric Jarrige <eri...@ar...>
++Philippe Reynes <tr...@ya...>
++
++ apf27 ARM926EJS (imx27 SoC)
++
+ -------------------------------------------------------------------------
+
+ Unknown / orphaned boards:
+diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
+new file mode 100644
+index 0000000..1da9548
+--- /dev/null
++++ b/board/armadeus/apf27/Makefile
+@@ -0,0 +1,45 @@
++#
++# (C) Copyright 2000-2004
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++# (C) Copyright 2012
++# Eric Jarrige <eri...@ar...>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).o
++
++COBJS := apf27.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++#########################################################################
++
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
+new file mode 100644
+index 0000000..bf3e5ec
+--- /dev/null
++++ b/board/armadeus/apf27/apf27.c
+@@ -0,0 +1,410 @@
++/*
++ * Copyright (C) 2007 Sascha Hauer, Pengutronix
++ * Copyright (C) 2008-2012 Eric Jarrige <eri...@ar...>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++#include <common.h>
++#include "crc.h"
++#include <jffs2/jffs2.h>
++#include <nand.h>
++#include <netdev.h>
++#include <asm/io.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/arch/gpio.h>
++#include <asm/errno.h>
++#include <environment.h>
++#include "apf27.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++/*
++ * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
++ * custormer use. The APF27 board uses this fuse to store the board revision:
++ * 0: initial board revision
++ * 1: first revision - Presence of the second RAM chip on the board is blown in
++ * fuse bank 1 row 9 bit 0 - No hardware change
++ * N: to be defined
++ */
++u32 get_board_rev(void)
++{
++ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
++
++ return readl(&iim->bank[1].fuse_regs[8]);
++}
++
++/*
++ * Fuse bank 1 row 9 is "reserved for future use" and therefore available for
++ * custormer use. The APF27 board revision 1 uses the bit 0 to permanently store
++ * the presence of the second RAM chip
++ * 0: AFP27 with 1 RAM of 64 MiB
++ * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
++ */
++int get_num_ram_bank(void)
++{
++ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
++ int nr_dram_banks = 1;
++
++ if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
++ nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
++ else
++ nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
++
++ return nr_dram_banks;
++}
++
++static void apf27_gpio_init(void)
++{
++ struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
++
++ /* PORT A */
++ writel(ACFG_DR_A_VAL, ®s->port[PORTA].gpio_dr);
++ writel(ACFG_OCR1_A_VAL, ®s->port[PORTA].ocr1);
++ writel(ACFG_OCR2_A_VAL, ®s->port[PORTA].ocr2);
++ writel(ACFG_ICFA1_A_VAL, ®s->port[PORTA].iconfa1);
++ writel(ACFG_ICFA2_A_VAL, ®s->port[PORTA].iconfa2);
++ writel(ACFG_ICFB1_A_VAL, ®s->port[PORTA].iconfb1);
++ writel(ACFG_ICFB2_A_VAL, ®s->port[PORTA].iconfb2);
++ writel(AC...
[truncated message content] |
