[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.0-46-ge234208
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.0-46-ge234208
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From: jorasse <jo...@us...> - 2012-09-27 10:50:58
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via e234208166da276abf33a404371540d484724560 (commit)
from d3dce819b710e63185e8c9782c80add1bdcb2247 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit e234208166da276abf33a404371540d484724560
Author: Eric Jarrige <eri...@ar...>
Date: Thu Sep 27 12:53:19 2012 +0200
[DEBUG] imxregs: add imx28 USB registers
-----------------------------------------------------------------------
Summary of changes:
buildroot/package/armadeus/imxregs/imxregs.mk | 2 +-
target/linux/debug/imxregs/imx28regs.h | 93 +++++++++++++++++++++++++
2 files changed, 94 insertions(+), 1 deletions(-)
diff --git a/buildroot/package/armadeus/imxregs/imxregs.mk b/buildroot/package/armadeus/imxregs/imxregs.mk
index 2711674..28909bf 100644
--- a/buildroot/package/armadeus/imxregs/imxregs.mk
+++ b/buildroot/package/armadeus/imxregs/imxregs.mk
@@ -4,7 +4,7 @@
#
#############################################################
-IMXREGS_VERSION = 1.2
+IMXREGS_VERSION = 1.3
IMXREGS_SITE = $(TOPDIR)/../target/linux/debug/imxregs/
IMXREGS_SITE_METHOD = copy
diff --git a/target/linux/debug/imxregs/imx28regs.h b/target/linux/debug/imxregs/imx28regs.h
index 251bf43..c5947da 100644
--- a/target/linux/debug/imxregs/imx28regs.h
+++ b/target/linux/debug/imxregs/imx28regs.h
@@ -117,4 +117,97 @@ static struct reg_info regs[] =
{ "HW_LRADC_THRESHOLD0", 0x80050150, 0, 0xffffffff, 'x', "LRADC Theshold0 Register" },
{ "HW_LRADC_THRESHOLD1", 0x80050160, 0, 0xffffffff, 'x', "LRADC Theshold1 Register" },
{ "HW_LRADC_VERSION", 0x80050170, 0, 0xffffffff, 'x', "LRADC Version Register" },
+/* USBCTRL0 */
+{ "HW_USBCTRL0_ID", 0x80080000, 0, 0xffffffff, 'x', "USBCTRL0 Host ID" },
+{ "HW_USBCTRL0_HWGENERAL", 0x80080004, 0, 0xffffffff, 'x', "USBCTRL0 Host General" },
+{ "HW_USBCTRL0_HWHOST", 0x80080008, 0, 0xffffffff, 'x', "USBCTRL0 Host h/w params" },
+{ "HW_USBCTRL0_HWTXBUF", 0x80080010, 0, 0xffffffff, 'x', "USBCTRL0 TX buffer h/w params" },
+{ "HW_USBCTRL0_HWRXBUF", 0x80080014, 0, 0xffffffff, 'x', "USBCTRL0 RX buffer h/w params" },
+{ "HW_USBCTRL0_CAPLENGTH", 0x80080100, 0, 0xffffffff, 'x', "USBCTRL0 Capability register length" },
+{ "HW_USBCTRL0_HCIVERSION", 0x80080102, 0, 0xffffffff, 'x', "USBCTRL0 Host Interface version" },
+{ "HW_USBCTRL0_HCSPARAMS", 0x80080104, 0, 0xffffffff, 'x', "USBCTRL0 Host control structural params" },
+{ "HW_USBCTRL0_HCCPARAMS", 0x80080108, 0, 0xffffffff, 'x', "USBCTRL0 control capability params" },
+{ "HW_USBCTRL0_DCIVERSION", 0x80080120, 0, 0xffffffff, 'x', "USBCTRL0 device interface version" },
+/* start EHCI registers: */
+{ "HW_USBCTRL0_USBCMD", 0x80080140, 0, 0xffffffff, 'x', "USBCTRL0 USB command register" },
+{ "HW_USBCTRL0_USBSTS", 0x80080144, 0, 0xffffffff, 'x', "USBCTRL0 USB status register" },
+{ "HW_USBCTRL0_USBINTR", 0x80080148, 0, 0xffffffff, 'x', "USBCTRL0 interrupt enable register" },
+{ "HW_USBCTRL0_FRINDEX", 0x8008014c, 0, 0xffffffff, 'x', "USBCTRL0 USB frame index" },
+/* segment 0x80080150) addr bits 63:32 if needed */
+{ "HW_USBCTRL0_PERIODICLISTBASE", 0x80080154, 0, 0xffffffff, 'x', "USBCTRL0 host crtlr frame list base addr" },
+{ "HW_USBCTRL0_DEVICEADDR", 0x80080154, 0, 0xffffffff, 'x', "USBCTRL0 device crtlr device address" },
+{ "HW_USBCTRL0_ASYNCLISTADDR", 0x80080158, 0, 0xffffffff, 'x', "USBCTRL0 host ctrlr next async addr" },
+{ "HW_USBCTRL0_EPLISTADDR", 0x80080158, 0, 0xffffffff, 'x', "USBCTRL0 device ctrlr endpoint list addr" },
+{ "HW_USBCTRL0_BURSTSIZE", 0x80080160, 0, 0xffffffff, 'x', "USBCTRL0 host ctrlr burst size register" },
+{ "HW_USBCTRL0_TXFILLTUNING", 0x80080164, 0, 0xffffffff, 'x', "USBCTRL0 TX FIFO fill tuning" },
+{ "HW_USBCTRL0_ULPIVIEW", 0x80080170, 0, 0xffffffff, 'x', "USBCTRL0 ULPI viewport" },
+{ "HW_USBCTRL0_CFGFLAG", 0x80080180, 0, 0xffffffff, 'x', "USBCTRL0 configflag (supports HS)" },
+{ "HW_USBCTRL0_PORTSC1", 0x80080184, 0, 0xffffffff, 'x', "USBCTRL0 port status and control" },
+/* end EHCI registers: */
+{ "HW_USBCTRL0_OTGSC", 0x800801a4, 0, 0xffffffff, 'x', "USBCTRL0 OTG status and control" },
+{ "HW_USBCTRL0_USBMODE", 0x800801a8, 0, 0xffffffff, 'x', "USBCTRL0 USB device mode" },
+{ "HW_USBCTRL0_ENDPTSETUPSTAT", 0x800801ac, 0, 0xffffffff, 'x', "USBCTRL0 endpoint setup status" },
+{ "HW_USBCTRL0_ENDPTPRIME", 0x800801b0, 0, 0xffffffff, 'x', "USBCTRL0 endpoint initialization" },
+{ "HW_USBCTRL0_ENDPTFLUSH", 0x800801b4, 0, 0xffffffff, 'x', "USBCTRL0 endpoint de-initialize" },
+{ "HW_USBCTRL0_ENDPTSTAT", 0x800801b8, 0, 0xffffffff, 'x', "USBCTRL0 endpoint status" },
+{ "HW_USBCTRL0_ENDPTCOMPLETE", 0x800801bc, 0, 0xffffffff, 'x', "USBCTRL0 endpoint complete" },
+{ "HW_USBCTRL0_EPCTRL0", 0x800801c0, 0, 0xffffffff, 'x', "USBCTRL0 endpoint control0" },
+/* USBCTRL1 */
+{ "HW_USBCTRL1_ID", 0x80090000, 0, 0xffffffff, 'x', "USBCTRL1 Host ID" },
+{ "HW_USBCTRL1_HWGENERAL", 0x80090004, 0, 0xffffffff, 'x', "USBCTRL1 Host General" },
+{ "HW_USBCTRL1_HWHOST", 0x80090008, 0, 0xffffffff, 'x', "USBCTRL1 Host h/w params" },
+{ "HW_USBCTRL1_HWTXBUF", 0x80090010, 0, 0xffffffff, 'x', "USBCTRL1 TX buffer h/w params" },
+{ "HW_USBCTRL1_HWRXBUF", 0x80090014, 0, 0xffffffff, 'x', "USBCTRL1 RX buffer h/w params" },
+{ "HW_USBCTRL1_CAPLENGTH", 0x80090100, 0, 0xffffffff, 'x', "USBCTRL1 Capability register length" },
+{ "HW_USBCTRL1_HCIVERSION", 0x80090102, 0, 0xffffffff, 'x', "USBCTRL1 Host Interface version" },
+{ "HW_USBCTRL1_HCSPARAMS", 0x80090104, 0, 0xffffffff, 'x', "USBCTRL1 Host control structural params" },
+{ "HW_USBCTRL1_HCCPARAMS", 0x80090108, 0, 0xffffffff, 'x', "USBCTRL1 control capability params" },
+{ "HW_USBCTRL1_DCIVERSION", 0x80090120, 0, 0xffffffff, 'x', "USBCTRL1 device interface version" },
+/* start EHCI registers: */
+{ "HW_USBCTRL1_USBCMD", 0x80090140, 0, 0xffffffff, 'x', "USBCTRL1 USB command register" },
+{ "HW_USBCTRL1_USBSTS", 0x80090144, 0, 0xffffffff, 'x', "USBCTRL1 USB status register" },
+{ "HW_USBCTRL1_USBINTR", 0x80090148, 0, 0xffffffff, 'x', "USBCTRL1 interrupt enable register" },
+{ "HW_USBCTRL1_FRINDEX", 0x8009014c, 0, 0xffffffff, 'x', "USBCTRL1 USB frame index" },
+/* segment 0x80090150) addr bits 63:32 if needed */
+{ "HW_USBCTRL1_PERIODICLISTBASE", 0x80090154, 0, 0xffffffff, 'x', "USBCTRL1 host crtlr frame list base addr" },
+{ "HW_USBCTRL1_DEVICEADDR", 0x80090154, 0, 0xffffffff, 'x', "USBCTRL1 device crtlr device address" },
+{ "HW_USBCTRL1_ASYNCLISTADDR", 0x80090158, 0, 0xffffffff, 'x', "USBCTRL1 host ctrlr next async addr" },
+{ "HW_USBCTRL1_EPLISTADDR", 0x80090158, 0, 0xffffffff, 'x', "USBCTRL1 device ctrlr endpoint list addr" },
+{ "HW_USBCTRL1_BURSTSIZE", 0x80090160, 0, 0xffffffff, 'x', "USBCTRL1 host ctrlr burst size register" },
+{ "HW_USBCTRL1_TXFILLTUNING", 0x80090164, 0, 0xffffffff, 'x', "USBCTRL1 TX FIFO fill tuning" },
+{ "HW_USBCTRL1_ULPIVIEW", 0x80090170, 0, 0xffffffff, 'x', "USBCTRL1 ULPI viewport" },
+{ "HW_USBCTRL1_CFGFLAG", 0x80090180, 0, 0xffffffff, 'x', "USBCTRL1 configflag (supports HS)" },
+{ "HW_USBCTRL1_PORTSC1", 0x80090184, 0, 0xffffffff, 'x', "USBCTRL1 port status and control" },
+/* end EHCI registers: */
+{ "HW_USBCTRL1_OTGSC", 0x800901a4, 0, 0xffffffff, 'x', "USBCTRL1 OTG status and control" },
+{ "HW_USBCTRL1_USBMODE", 0x800901a8, 0, 0xffffffff, 'x', "USBCTRL1 USB device mode" },
+{ "HW_USBCTRL1_ENDPTSETUPSTAT", 0x800901ac, 0, 0xffffffff, 'x', "USBCTRL1 endpoint setup status" },
+{ "HW_USBCTRL1_ENDPTPRIME", 0x800901b0, 0, 0xffffffff, 'x', "USBCTRL1 endpoint initialization" },
+{ "HW_USBCTRL1_ENDPTFLUSH", 0x800901b4, 0, 0xffffffff, 'x', "USBCTRL1 endpoint de-initialize" },
+{ "HW_USBCTRL1_ENDPTSTAT", 0x800901b8, 0, 0xffffffff, 'x', "USBCTRL1 endpoint status" },
+{ "HW_USBCTRL1_ENDPTCOMPLETE", 0x800901bc, 0, 0xffffffff, 'x', "USBCTRL1 endpoint complete" },
+{ "HW_USBCTRL1_EPCTRL0", 0x800901c0, 0, 0xffffffff, 'x', "USBCTRL1 endpoint control0" },
+/* USBPHY0 */
+{ "HW_USBPHY0_PWD", 0x8007c000, 0, 0xffffffff, 'x', "USBPHY0 power down register" },
+{ "HW_USBPHY0_TX", 0x8007c010, 0, 0xffffffff, 'x', "USBPHY0 transmitter control register" },
+{ "HW_USBPHY0_RX", 0x8007c020, 0, 0xffffffff, 'x', "USBPHY0 receiver control register" },
+{ "HW_USBPHY0_CTRL", 0x8007c030, 0, 0xffffffff, 'x', "USBPHY0 general control register" },
+{ "HW_USBPHY0_STATUS", 0x8007c040, 0, 0xffffffff, 'x', "USBPHY0 status register" },
+{ "HW_USBPHY0_DEBUG", 0x8007c050, 0, 0xffffffff, 'x', "USBPHY0 debug register" },
+{ "HW_USBPHY0_DEBUG0_STATUS", 0x8007c060, 0, 0xffffffff, 'x', "USBPHY0 debug status register 0" },
+{ "HW_USBPHY0_DEBUG1", 0x8007c070, 0, 0xffffffff, 'x', "USBPHY0 debug status register 1" },
+{ "HW_USBPHY0_VERSION", 0x8007c080, 0, 0xffffffff, 'x', "USBPHY0 RTL version" },
+{ "HW_USBPHY0_IP", 0x8007c090, 0, 0xffffffff, 'x', "USBPHY0 IP block register" },
+/* USBPHY1 */
+{ "HW_USBPHY1_PWD", 0x8007e000, 0, 0xffffffff, 'x', "USBPHY1 power down register" },
+{ "HW_USBPHY1_TX", 0x8007e010, 0, 0xffffffff, 'x', "USBPHY1 transmitter control register" },
+{ "HW_USBPHY1_RX", 0x8007e020, 0, 0xffffffff, 'x', "USBPHY1 receiver control register" },
+{ "HW_USBPHY1_CTRL", 0x8007e030, 0, 0xffffffff, 'x', "USBPHY1 general control register" },
+{ "HW_USBPHY1_STATUS", 0x8007e040, 0, 0xffffffff, 'x', "USBPHY1 status register" },
+{ "HW_USBPHY1_DEBUG", 0x8007e050, 0, 0xffffffff, 'x', "USBPHY1 debug register" },
+{ "HW_USBPHY1_DEBUG0_STATUS", 0x8007e060, 0, 0xffffffff, 'x', "USBPHY1 debug status register 0" },
+{ "HW_USBPHY1_DEBUG1", 0x8007e070, 0, 0xffffffff, 'x', "USBPHY1 debug status register 1" },
+{ "HW_USBPHY1_VERSION", 0x8007e080, 0, 0xffffffff, 'x', "USBPHY1 RTL version" },
+{ "HW_USBPHY1_IP", 0x8007e090, 0, 0xffffffff, 'x', "USBPHY1 IP block register" },
+
};
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armadeus
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