[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-423-g7fca8b9
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-423-g7fca8b9
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From: jorasse <jo...@us...> - 2012-06-26 11:46:44
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 7fca8b9e7544ff0c73fa9244e0e9e9bc446db7d2 (commit)
from 248a99404d5029b9d8d82776d8e4dbde47c57e29 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7fca8b9e7544ff0c73fa9244e0e9e9bc446db7d2
Author: Eric Jarrige <eri...@ar...>
Date: Tue Jun 26 13:49:12 2012 +0200
[UBOOT] apf51: fix typo / checkpatch
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf51/apf51-u-boot-2012.04.h | 66 ++++----
patches/u-boot/2012.04/400-imx51.patch | 7 +-
patches/u-boot/2012.04/401-apf51.patch | 87 ++++++------
.../u-boot/2012.04/405-remove_extra_printk.patch | 10 +-
patches/u-boot/2012.04/407-imx51-nand.patch | 158 ++++++++++---------
5 files changed, 170 insertions(+), 158 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2012.04.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2012.04.h
index 6b9d2ed..5fe195a 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2012.04.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2012.04.h
@@ -24,7 +24,7 @@
#define __CONFIG_H
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "1.2"
+#define CONFIG_ENV_VERSION "1.2"
#define CONFIG_IDENT_STRING " apf51 patch 1.5"
#define CONFIG_BOARD_NAME apf51
@@ -33,7 +33,7 @@
*/
#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU */
#define CONFIG_MX51 /* in a Freescale i.MX51 Chip */
-#define CONFIG_MACH_TYPE 2795 /* APF51 */
+#define CONFIG_MACH_TYPE 2795 /* APF51 */
/*
* Enable the call to miscellaneous platform dependent initialization.
@@ -114,7 +114,7 @@
#define PHYS_SDRAM_SIZE 256
#define PHYS_SDRAM_1_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
#define PHYS_SDRAM_2_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 * 1024 * 1024) )
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 * 1024 * 1024))
#define CONFIG_SYS_MEMTEST_START 0x90000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x90100000 /* 1st MiB in DRAM */
@@ -145,13 +145,13 @@
#define CONFIG_KERNEL_OFFSET 0x00400000
#define CONFIG_ROOTFS_OFFSET 0x00C00000
-#define CONFIG_MTDMAP "mxc_nand"
+#define CONFIG_MTDMAP "mxc_nand"
#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
- ":1M(u-boot)ro," \
+ ":1M(u-boot)ro,"\
"512K(env)," \
"512K(env2)," \
- "1M(firmware)," \
+ "1M(firmware)," \
"512K(dtb)," \
"512K(splash)," \
"8M(kernel)," \
@@ -163,7 +163,7 @@
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE \
+#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 16 /* max command args */
@@ -178,7 +178,7 @@
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
#define CONFIG_INITRD_TAG /* send initrd params */
/* #define CONFIG_REVISION_TAG */
@@ -187,7 +187,7 @@
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
-#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
+#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
" ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
@@ -221,7 +221,7 @@
"addubifsargs=setenv bootargs ${bootargs} " \
"ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
"addmmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
+ "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
"addipargs=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"${hostname}:eth0:off\0" \
@@ -292,7 +292,7 @@
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART3_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BAUDRATE 115200
/*
@@ -349,7 +349,7 @@
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
-/*-----------------------------------------------------------------------
+/*
* FPGA
*/
#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
@@ -448,21 +448,21 @@
#define APF_PERCLK 55 /* 55.4 MHZ PERCLK frequency */
#define APF_NFC_CLK 23 /* MHZ NFC Clock from EMI clk */
#define APF_USB_CLK 54 /* external USB serial bus frequency PLL3 */
-#define APF_ESDHC_CLK 54 /* MHz ESDHC controller frequency / PLL3 */
+#define APF_ESDHC_CLK 54 /* MHz ESDHC controller frequency / PLL3 */
#define APF_UART_CLK 66 /* 66.5 MHz UART frequency from PLL2 */
-//#define APF_SSI_CLK 54 /* MHz SSI controller frequency */
-//#define APF_TVE_CLK 216 /* MHz TVE controller frequency */
-//#define APF_DI_CLK 0 /* MHz DISPLAY controller frequency*/
-//#define APF_VPU_CLK 0 /* MHz VPU controller frequency*/
-//#define APF_SPDIF_CLK 10 /* MHz SPDIF controller frequency 10.3 MHz*/
-//#define APF_SIM_CLK 54 /* MHz SIM controller frequency */
-//#define APF_FIRI_CLK 54 /* MHz FIRI controller frequency */
-//#define APF_HSI2C_CLK 54 /* MHz HS I2C controller frequency */
-//#define APF_CSI_CLK 54 /* MHz HS CSI controller frequency */
-//#define APF_ECSPI_CLK 54 /* MHz HECSPI controller frequency */
-//#define APF_WRCK_CLK 13 /* MHz WRCK 13.3 MHz */
-//#define APF_LPSR_CLK 0 /* MHz */
+/*#define APF_SSI_CLK 54*/ /* MHz SSI controller frequency */
+/*#define APF_TVE_CLK 216*/ /* MHz TVE controller frequency */
+/*#define APF_DI_CLK 0*/ /* MHz DISPLAY controller frequency*/
+/*#define APF_VPU_CLK 0*/ /* MHz VPU controller frequency*/
+/*#define APF_SPDIF_CLK 10*/ /* MHz SPDIF controller frequency 10.3 MHz*/
+/*#define APF_SIM_CLK 54*/ /* MHz SIM controller frequency */
+/*#define APF_FIRI_CLK 54*/ /* MHz FIRI controller frequency */
+/*#define APF_HSI2C_CLK 54*/ /* MHz HS I2C controller frequency */
+/*#define APF_CSI_CLK 54*/ /* MHz HS CSI controller frequency */
+/*#define APF_ECSPI_CLK 54*/ /* MHz HECSPI controller frequency */
+/*#define APF_WRCK_CLK 13*/ /* MHz WRCK 13.3 MHz */
+/*#define APF_LPSR_CLK 0*/ /* MHz */
#define APF_PGC_CLK 66 /* MHz 66.5 MHz */
/* PLL parameters assuming 32.768kHz *1024 input clock with doubler ON */
@@ -601,7 +601,7 @@
#include <asm/arch/imx-regs.h>
/* Issue Mode register Command to SDRAM*/
-#define ACFG_DRR_MR_VAL ( 0x0\
+#define ACFG_DRR_MR_VAL (0x0\
| (((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\
| ((3)<<(4)) \
| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(3)))
@@ -709,14 +709,14 @@
/* CCM Configuration */
#define CONFIG_SYS_PLL_DP_CTL 0x00001332 /* use fpm_clk */
-#define CONFIG_SYS_CLKCTL_CCMR 0x00001FFF
-#define CONFIG_SYS_CLKCTL_CSR 0x0000003E
-#define CONFIG_SYS_CLKCTL_CCSR 0x00000200
+#define CONFIG_SYS_CLKCTL_CCMR 0x00001FFF
+#define CONFIG_SYS_CLKCTL_CSR 0x0000003E
+#define CONFIG_SYS_CLKCTL_CCSR 0x00000200
#define CCBDR_MASK 0x40000000
#define CONFIG_SYS_CLKTL_CBCDR\
- (CCBDR_MASK \
+ (CCBDR_MASK \
|((((ACFG_PLL1_CLK/APF_DDR_CLK)-1)&0x07)<<27) \
|((((ACFG_PLL2_CLK/APF_EMI_CLK)-1)&0x07)<<22) \
|((((ACFG_PLL2_CLK/APF_AXIB_CLK)-1)&0x07)<<19) \
@@ -734,7 +734,7 @@
#define CONFIG_SYS_CLKTL_CBCMR1 0xA5A2A020
#define CONFIG_SYS_CLKTL_CSCDR1\
- ( 0x0 \
+ (0x0 \
|((((ACFG_PLL3_CLK/APF_ESDHC_CLK)/8)&0x07)<<19) \
|(((((ACFG_PLL3_CLK/APF_ESDHC_CLK) \
/((ACFG_PLL3_CLK/APF_ESDHC_CLK)/8+1))-1)&0x07)<<22) \
@@ -755,7 +755,7 @@
#define ACFG_SDRAM_ESDMISC_REGISTER_VAL 0x000a5680
-#if ((2*ACFG_SDRAM_RC_DELAY)>(16*CONFIG_SYS_2XDDRCLK_LGTH))
+#if ((2*ACFG_SDRAM_RC_DELAY) > (16*CONFIG_SYS_2XDDRCLK_LGTH))
#define REG_FIELD_RC_VAL 0
#else
#define REG_FIELD_RC_VAL \
@@ -763,7 +763,7 @@
/CONFIG_SYS_2XDDRCLK_LGTH)-1)
#endif
-#if ((2*ACFG_SDRAM_RFC_DELAY)>(25*CONFIG_SYS_2XDDRCLK_LGTH))
+#if ((2*ACFG_SDRAM_RFC_DELAY) > (25*CONFIG_SYS_2XDDRCLK_LGTH))
#define REG_FIELD_RFC_VAL \
(((2*ACFG_SDRAM_RFC_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1) \
/CONFIG_SYS_2XDDRCLK_LGTH/2)-10)
diff --git a/patches/u-boot/2012.04/400-imx51.patch b/patches/u-boot/2012.04/400-imx51.patch
index fd09a3d..e27535a 100644
--- a/patches/u-boot/2012.04/400-imx51.patch
+++ b/patches/u-boot/2012.04/400-imx51.patch
@@ -76,7 +76,7 @@ index f972498..ba46365 100644
+ DEFINE(ESDCTL_ESDPRCT0, offsetof(struct esdctl_regs, esdprct0));
+ DEFINE(ESDCTL_ESDPRCT1, offsetof(struct esdctl_regs, esdprct1));
+ BLANK();
-+ COMMENT( "IOMUX" );
++ COMMENT("IOMUX");
+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDRPKS, PAD_I_START
+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDRPKS));
+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_PKEDDR, PAD_I_START
@@ -374,7 +374,7 @@ new file mode 100644
index 0000000..c1707af
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx5/regs_esdctl.h
-@@ -0,0 +1,130 @@
+@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2012
+ * Eric Jarrige, Armadeus Project, <eri...@ar...>
@@ -502,7 +502,8 @@ index 0000000..c1707af
+#define DDR_NOP_CMD(cs) (0x00008000 + (cs << 2))
+#define DRR_PRECHARGE_CMD(cs, ba) (0x04008008 + (cs << 2) + ba)
+#define DRR_AUTOREFRESH_CMD(cs) (0x00008010 + (cs << 2))
-+#define DRR_LMR_CMD(cs, ba, addr) (0x00008018 + (addr << 16) + (cs << 2) + ba)
++#define DRR_LMR_CMD(cs, ba, addr) (0x00008018 + (addr << 16)\
++ + (cs << 2) + ba)
+
+#endif /* __REGS_ESDCTL_H__ */
--
diff --git a/patches/u-boot/2012.04/401-apf51.patch b/patches/u-boot/2012.04/401-apf51.patch
index 043867e..fa56207 100644
--- a/patches/u-boot/2012.04/401-apf51.patch
+++ b/patches/u-boot/2012.04/401-apf51.patch
@@ -67,7 +67,7 @@ new file mode 100644
index 0000000..e09b561
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,1220 @@
+@@ -0,0 +1,1222 @@
+/*
+ * (C) Copyright 2010-2012 Eric Jarrige, Armadeus Project
+ *
@@ -111,7 +111,7 @@ index 0000000..e09b561
+
+DECLARE_GLOBAL_DATA_PTR;
+
-+unsigned long boot_verb = 0;
++unsigned long boot_verb;
+
+u32 get_board_rev(void)
+{
@@ -136,10 +136,10 @@ index 0000000..e09b561
+
+int dram_init(void)
+{
-+
++
+ gd->ram_size = get_ram_size((void *)CSD0_BASE_ADDR, PHYS_SDRAM_1_SIZE);
+ if (get_num_ram_bank() > 1) {
-+ gd->ram_size +=
++ gd->ram_size +=
+ get_ram_size((void *)CSD1_BASE_ADDR, PHYS_SDRAM_2_SIZE);
+ }
+
@@ -152,9 +152,10 @@ index 0000000..e09b561
+ gd->bd->bi_dram[0].size = gd->ram_size / get_num_ram_bank();
+ if (CONFIG_NR_DRAM_BANKS > 1) {
+ gd->bd->bi_dram[1].start = CSD1_BASE_ADDR;
-+ gd->bd->bi_dram[1].size = gd->ram_size -gd->bd->bi_dram[0].size;
++ gd->bd->bi_dram[1].size = gd->ram_size
++ - gd->bd->bi_dram[0].size;
+ }
-+
++
+}
+
+void setup_usb(void)
@@ -407,10 +408,10 @@ index 0000000..e09b561
+ mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_EIM_DTACK, IOMUX_CONFIG_ALT0);
-+// missing in DS mxc_request_iomux(MX51_PIN_EIM_WAIT, IOMUX_CONFIG_ALT0);
++/* missing in DS mxc_request_iomux(MX51_PIN_EIM_WAIT, IOMUX_CONFIG_ALT0); */
+ mxc_request_iomux(MX51_PIN_EIM_LBA, IOMUX_CONFIG_ALT0);
-+// missing in DS mxc_request_iomux(MX51_PIN_EIM_BCLK, IOMUX_CONFIG_ALT0);
-+// missing in DS mxc_request_iomux(MX51_PIN_EIM_RW , IOMUX_CONFIG_ALT0);
++/* missing in DS mxc_request_iomux(MX51_PIN_EIM_BCLK, IOMUX_CONFIG_ALT0); */
++/* missing in DS mxc_request_iomux(MX51_PIN_EIM_RW , IOMUX_CONFIG_ALT0); */
+
+ /*
+ * Configure Register for each chip select
@@ -551,10 +552,10 @@ index 0000000..e09b561
+ * Configure iomux for display 1 interface
+ */
+ mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
-+// missing in DS mxc_request_iomux(MX51_PIN_DI1_DISP_CLK, IOMUX_CONFIG_ALT0);
++/* missing in DS mxc_request_iomux(MX51_PIN_DI1_DISP_CLK, IOMUX_CONFIG_ALT0);*/
+ mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0);
-+// missing in DS mxc_request_iomux(MX51_PIN_DI1_PIN15, IOMUX_CONFIG_ALT0);
++/* missing in DS mxc_request_iomux(MX51_PIN_DI1_PIN15, IOMUX_CONFIG_ALT0);*/
+
+ mxc_request_iomux(MX51_PIN_DISP1_DAT0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_DISP1_DAT1, IOMUX_CONFIG_ALT0);
@@ -588,12 +589,12 @@ index 0000000..e09b561
+ * Configure iomux for NFC interface
+ */
+#define NAND_PAD47K_CFG (PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | \
-+ PAD_CTL_PKE_ENABLE | PAD_CTL_47K_PU | \
-+ PAD_CTL_DRV_HIGH)
++ PAD_CTL_PKE_ENABLE | PAD_CTL_47K_PU | \
++ PAD_CTL_DRV_HIGH)
+
+#define NAND_PAD100K_CFG (PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | \
-+ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | \
-+ PAD_CTL_DRV_HIGH)
++ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | \
++ PAD_CTL_DRV_HIGH)
+
+ mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, NAND_PAD47K_CFG);
@@ -612,8 +613,8 @@ index 0000000..e09b561
+
+ mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, PAD_CTL_DRV_VOT_HIGH |
-+ PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE |
-+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
++ PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE |
++ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+
@@ -653,8 +654,8 @@ index 0000000..e09b561
+ * Configure iomux for SPI interface
+ */
+#define CSPI_PAD_CFG (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | \
-+ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | \
-+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST)
++ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | \
++ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST)
+ /*
+ * ECSPI1
+ */
@@ -808,7 +809,7 @@ index 0000000..e09b561
+ mxc_request_iomux(MX51_PIN_DISP2_DAT15, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_DISP2_DAT15, CFG_FEC_PAD);
+
-+ /*
++ /*
+ * FEC signals involved in daisy chain should be mapped
+ * to DISP2/DI2 pads
+ */
@@ -830,7 +831,7 @@ index 0000000..e09b561
+#endif
+}
+
-+int board_eth_init(bd_t * bis)
++int board_eth_init(bd_t *bis)
+{
+#define STR_ENV_ETHADDR "ethaddr"
+ int rc = -ENODEV;
@@ -1011,8 +1012,8 @@ index 0000000..e09b561
+#if defined(CONFIG_FPGA)
+ /* init and download fpga */
+ if ((autoload) && (0 == strcmp(autoload, "1"))) {
-+ if (mtdparts_init() == 0)
-+ if (find_dev_and_part("firmware", &dev, &pnum, &part) == 0) {
++ if ((mtdparts_init() == 0) && (find_dev_and_part("firmware",
++ &dev, &pnum, &part) == 0)) {
+ size = part->size;
+ if (nand_read_skip_bad(&nand_info[0], part->offset,
+ &size, firmware_buffer))
@@ -1086,7 +1087,8 @@ index 0000000..e09b561
+/*
+ * display dcd table. to delete
+ */
-+int do_mx51_show_dcd_tab(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
++int do_mx51_show_dcd_tab(cmd_tbl_t *cmdtp, int flag, int argc,
++ char *const argv[])
+{
+ ulong i = 1;
+ struct esdctl_regs *esdctl = (struct esdctl_regs *)ESDCTL_BASE_ADDR;
@@ -1286,14 +1288,14 @@ index 0000000..e09b561
+/***************************************************/
+
+U_BOOT_CMD(dcdshow, 1, 1, do_mx51_show_dcd_tab,
-+ "display mx51 dcd tab\n", "");
++ "display mx51 dcd tab\n", "");
+#endif /* CONFIG_CMD_BSP */
diff --git a/board/armadeus/apf51/fpga.c b/board/armadeus/apf51/fpga.c
new file mode 100644
index 0000000..52f1869
--- /dev/null
+++ b/board/armadeus/apf51/fpga.c
-@@ -0,0 +1,267 @@
+@@ -0,0 +1,266 @@
+/*
+ * (C) Copyright 2002-2010
+ * Nicolas Colombain <nic...@ar...>
@@ -1335,9 +1337,9 @@ index 0000000..52f1869
+#include <spartan3.h>
+
+#ifdef FPGA_DEBUG
-+#define PRINTF(fmt,args...) printf (fmt ,##args)
++#define PRINTF(fmt, args...) printf(fmt , ##args)
+#else
-+#define PRINTF(fmt,args...)
++#define PRINTF(fmt, args...)
+#endif
+
+u32 temp_clk; /* use to restore the emi_clk_sel after donwload */
@@ -1384,7 +1386,7 @@ index 0000000..52f1869
+
+ temp_rcr1 = readl(&weim->cs1rcr1);
+ writel(0x01000010, &weim->cs1rcr1);
-+ temp_wcr1 = readl(&weim->cs1wcr1);
++ temp_wcr1 = readl(&weim->cs1wcr1);
+ writel(0x01000008, &weim->cs1wcr1);
+
+ /* change emi_clk_sel to ensure blck smaller than 50MHz */
@@ -1419,8 +1421,8 @@ index 0000000..52f1869
+ */
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
-+ PRINTF("%s:%d: FPGA PROGRAM %s\n", __FUNCTION__, __LINE__,
-+ assert ? "high" : "low");
++ PRINTF("%s:%d: FPGA PROGRAM %s\n", __func__, __LINE__,
++ assert ? "high" : "low");
+ gpio_set_value(IOMUX_TO_GPIO(ACFG_FPGA_PRG), !assert);
+ return assert;
+}
@@ -1440,7 +1442,7 @@ index 0000000..52f1869
+int fpga_init_fn(int cookie)
+{
+ int value;
-+ PRINTF("%s:%d: INIT check... \n", __FUNCTION__, __LINE__);
++ PRINTF("%s:%d: INIT check...\n", __func__, __LINE__);
+ value = gpio_get_value(IOMUX_TO_GPIO(ACFG_FPGA_INIT));
+ PRINTF("init value read %x\n", value);
+ if (value)
@@ -1455,9 +1457,9 @@ index 0000000..52f1869
+{
+ int value;
+ value = gpio_get_value(IOMUX_TO_GPIO(ACFG_FPGA_DONE));
-+ PRINTF("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
++ PRINTF("%s:%d: DONE check... %s", __func__, __LINE__,
+ value ? "high" : "low");
-+ return (value ? FPGA_SUCCESS : FPGA_FAIL);
++ return value ? FPGA_SUCCESS : FPGA_FAIL;
+}
+
+/*
@@ -1475,7 +1477,7 @@ index 0000000..52f1869
+
+int fpga_rdata_fn(unsigned char *data, int cookie)
+{
-+ PRINTF("%s:%d: FPGA READ DATA %02X \n", __FUNCTION__, __LINE__,
++ PRINTF("%s:%d: FPGA READ DATA %02X\n", __func__, __LINE__,
+ *((char *)ACFG_FPGA_RDATA));
+ *data =
+ (unsigned char)((*((unsigned short *)ACFG_FPGA_RDATA)) &
@@ -1485,9 +1487,9 @@ index 0000000..52f1869
+
+int fpga_wdata_fn(unsigned char data, int flush, int cookie)
+{
-+ PRINTF("%s:%d: FPGA WRITE DATA %02X \n", __FUNCTION__, __LINE__, data);
++ PRINTF("%s:%d: FPGA WRITE DATA %02X\n", __func__, __LINE__, data);
+ static u32 temp;
-+ static u32 index = 0;
++ static u32 index;
+
+ switch (index++) {
+ case 0:
@@ -1500,8 +1502,7 @@ index 0000000..52f1869
+ temp = temp + (data << 24);
+ break;
+ default:
-+ *((volatile unsigned long *)ACFG_FPGA_WDATA) =
-+ temp + (data << 16);
++ *((unsigned long *)ACFG_FPGA_WDATA) = temp + (data << 16);
+ index = 0;
+ break;
+ }
@@ -1523,7 +1524,7 @@ index 0000000..52f1869
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct weim *weim = (struct weim *)WEIM_BASE_ADDR;
-+ PRINTF("%s:%d: FPGA POST \n", __FUNCTION__, __LINE__);
++ PRINTF("%s:%d: FPGA POST\n", __func__, __LINE__);
+ /* restore emi_clk_sel */
+ writel(temp_clk, &mxc_ccm->cbcdr);
+ udelay(10); /* wait a few us after emi_clk_sel change */
@@ -1536,14 +1537,14 @@ index 0000000..52f1869
+/*
+ * Initialize the fpga. Return 1 on success, 0 on failure.
+ */
-+int APF51_init_fpga(u_char * buffer, size_t size)
++int APF51_init_fpga(u_char *buffer, size_t size)
+{
+ int i, lout = 0;
+
+ fpga_init();
+
+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
-+ PRINTF("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
++ PRINTF("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
+ fpga_add(fpga_xilinx, &fpga[i]);
+ }
+
@@ -1592,7 +1593,7 @@ index 0000000..f7a0064
+ * MA 02111-1307 USA
+ *
+ */
-+extern int APF51_init_fpga(u_char * buffer, size_t size);
++extern int APF51_init_fpga(u_char *buffer, size_t size);
+
+extern int fpga_pre_fn(int cookie);
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
diff --git a/patches/u-boot/2012.04/405-remove_extra_printk.patch b/patches/u-boot/2012.04/405-remove_extra_printk.patch
index 768e829..2a1831c 100644
--- a/patches/u-boot/2012.04/405-remove_extra_printk.patch
+++ b/patches/u-boot/2012.04/405-remove_extra_printk.patch
@@ -10,24 +10,26 @@ diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 2b730e0..922f82f 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
-@@ -261,8 +261,9 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
+@@ -261,8 +261,10 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
}
/* Leave it for now, if its matured we can move this
* message to MTD_DEBUG_LEVEL0 */
- printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n",
- (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
-+ debug(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n",
++ debug(KERN_DEBUG "nand_read_bbt: "
++ "Bad block at 0x%012llx\n",
+ (loff_t)((offs << 2) + (act >> 1)) <<
+ this->bbt_erase_shift);
/* Factory marked bad or worn ou |
