[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-422-g248a994
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-422-g248a994
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From: jorasse <jo...@us...> - 2012-06-26 10:26:37
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 248a99404d5029b9d8d82776d8e4dbde47c57e29 (commit)
from 7a1c774b3a3b583567a7fb846e3188445e33b382 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 248a99404d5029b9d8d82776d8e4dbde47c57e29
Author: Eric Jarrige <eri...@ar...>
Date: Tue Jun 26 12:29:04 2012 +0200
[UBOOT] apf28: fix typo / checkpatch
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf28/apf28-u-boot-2012.04.h | 49 +++++++-------
.../503-imx28_suppport_battery_power_supply.patch | 67 +++++++++----------
2 files changed, 57 insertions(+), 59 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
index 0154045..0b9257a 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
+++ b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
@@ -25,7 +25,7 @@
#include <asm/arch/regs-base.h>
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "1.2"
+#define CONFIG_ENV_VERSION "1.2"
#define CONFIG_IDENT_STRING " apf28 patch 1.5"
#define CONFIG_BOARD_NAME apf28
@@ -38,7 +38,7 @@
/*
* Enable the call to miscellaneous platform dependent initialization.
*/
-#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
+#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h>*/
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
@@ -141,12 +141,12 @@
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
/* Point initial SP in SRAM so SPL can use it too. */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000
-#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
+#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000
+#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_SYS_TEXT_BASE 0x40000000
@@ -200,7 +200,7 @@
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
#define CONFIG_INITRD_TAG /* send initrd params */
/* #define CONFIG_REVISION_TAG */
@@ -209,7 +209,7 @@
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
-#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
+#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
" ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
@@ -227,22 +227,22 @@
* Extra Environments
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "env_version=" CONFIG_ENV_VERSION "\0" \
- "consoledev=" MK_STR(ACFG_CONSOLE_DEV) "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "env_version=" CONFIG_ENV_VERSION "\0" \
+ "consoledev=" MK_STR(ACFG_CONSOLE_DEV) "\0"\
+ "mtdparts=" MTDPARTS_DEFAULT "\0"\
"partition=nand0,6\0" \
- "u-boot_addr=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0" \
- "u-boot_len=" MK_STR(CONFIG_SYS_MONITOR_LEN) "\0" \
- "kernel_addr=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \
- "rootfs_addr=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0" \
- "board_name=" MK_STR(CONFIG_BOARD_NAME) "\0" \
+ "u-boot_addr=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0"\
+ "u-boot_len=" MK_STR(CONFIG_SYS_MONITOR_LEN) "\0"\
+ "kernel_addr=" MK_STR(CONFIG_KERNEL_OFFSET) "\0"\
+ "rootfs_addr=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0"\
+ "board_name=" MK_STR(CONFIG_BOARD_NAME) "\0"\
"kernel_addr_r=40000000\0" \
"addnfsargs=setenv bootargs ${bootargs} " \
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"addubifsargs=setenv bootargs ${bootargs} " \
"ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
"addmmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
+ "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
"addipargs=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"${hostname}:eth0:off\0" \
@@ -270,12 +270,13 @@
"nand erase ${u-boot_addr} ${u-boot_len} ; " \
"nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};" \
"nand erase ${u-boot2_addr} ${u-boot_len};" \
- "if nand write.trimffs ${fileaddr} ${u-boot2_addr} ${filesize};"\
- "then echo Flashing of uboot succeed;" \
+ "if nand write.trimffs ${fileaddr} ${u-boot2_addr}" \
+ " ${filesize};" \
+ "then echo Flashing of uboot succeed;" \
"else echo Flashing of uboot failed;" \
"fi; " \
"fi; \0" \
- "flash_kernel=nand erase.part kernel;" \
+ "flash_kernel=nand erase.part kernel;" \
"if nand write.trimffs ${fileaddr} ${kernel_addr} ${filesize};"\
"then echo Flashing of kernel succeed;" \
"else echo Flashing of kernel failed;" \
@@ -293,13 +294,13 @@
"flash_reset_env=env default -f; saveenv;" \
"echo Flash environment variables erased!\0" \
"download_uboot=tftpboot ${loadaddr} ${board_name}-u-boot.sb\0" \
- "download_kernel=tftpboot ${loadaddr} ${board_name}-linux.bin\0" \
- "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ubi\0" \
- "download_dtb=tftpboot ${loadaddr} imx28-${board_name}.dtb\0" \
+ "download_kernel=tftpboot ${loadaddr} ${board_name}-linux.bin\0"\
+ "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ubi\0"\
+ "download_dtb=tftpboot ${loadaddr} imx28-${board_name}.dtb\0" \
"update_uboot=run download_uboot flash_uboot\0" \
"update_kernel=run download_kernel flash_kernel\0" \
"update_rootfs=run download_rootfs flash_rootfs\0" \
- "update_dtb=run download_dtb flash_dtb\0" \
+ "update_dtb=run download_dtb flash_dtb\0" \
"update_all=run download_kernel flash_kernel download_rootfs " \
"flash_rootfs download_uboot flash_uboot\0" \
"unlock_regs=echo unlock_reg not needed anymore\0"
diff --git a/patches/u-boot/2012.04/503-imx28_suppport_battery_power_supply.patch b/patches/u-boot/2012.04/503-imx28_suppport_battery_power_supply.patch
index f84f9a4..2863ee1 100644
--- a/patches/u-boot/2012.04/503-imx28_suppport_battery_power_supply.patch
+++ b/patches/u-boot/2012.04/503-imx28_suppport_battery_power_supply.patch
@@ -164,7 +164,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
if (xfer) {
setbits_le32(&power_regs->hw_power_5vctrl,
-@@ -230,19 +227,25 @@ void mx28_enable_4p2_dcdc_input(int xfer
+@@ -230,19 +227,24 @@ void mx28_enable_4p2_dcdc_input(int xfer
early_delay(25);
@@ -176,8 +176,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
-
- if (!pwd_bo)
- clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
-+ if(readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
-+ {
++ if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
@@ -198,7 +197,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
if (prev_5v_brnout) {
writel(POWER_5VCTRL_PWDN_5VBRNOUT,
&power_regs->hw_power_5vctrl_set);
-@@ -255,10 +258,6 @@ void mx28_enable_4p2_dcdc_input(int xfer
+@@ -255,10 +257,6 @@ void mx28_enable_4p2_dcdc_input(int xfer
&power_regs->hw_power_reset);
}
@@ -209,7 +208,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
if (prev_5v_droop)
clrbits_le32(&power_regs->hw_power_ctrl,
POWER_CTRL_ENIRQ_VDD5V_DROOP);
-@@ -299,55 +298,38 @@ void mx28_power_init_4p2_regulator(void)
+@@ -299,55 +297,38 @@ void mx28_power_init_4p2_regulator(void)
* not present. Exiting to not enable DCDC power during 5V
* connected state.
*/
@@ -290,7 +289,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
}
-@@ -356,20 +338,14 @@ void mx28_power_init_dcdc_4p2_source(voi
+@@ -356,20 +337,14 @@ void mx28_power_init_dcdc_4p2_source(voi
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
@@ -316,7 +315,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
}
}
-@@ -450,15 +426,6 @@ void mx28_boot_valid_5v(void)
+@@ -450,15 +425,6 @@ void mx28_boot_valid_5v(void)
mx28_power_enable_4p2();
}
@@ -332,7 +331,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
void mx28_handle_5v_conflict(void)
{
struct mx28_power_regs *power_regs =
-@@ -530,10 +497,10 @@ void mx28_init_batt_bo(void)
+@@ -530,10 +496,10 @@ void mx28_init_batt_bo(void)
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
@@ -345,21 +344,19 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
-@@ -601,15 +568,418 @@ int mx28_is_batt_good(void)
+@@ -601,15 +567,416 @@ int mx28_is_batt_good(void)
return 0;
}
-void mx28_power_configure_power_source(void)
+void mx28_lradc_init(int bEnableOnChipGroundRef, int eFreq)
-+{
-+ static int lradcInitialized = 0;
+ {
++ static int lradcInitialized;
+ struct mx28_lradc_regs *lradc_regs =
+ (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+
-+ if( lradcInitialized )
-+ {
++ if (lradcInitialized)
+ return;
-+ }
+
+ /* Clear the Soft Reset for normal operation */
+ clrbits_le32(&lradc_regs->hw_lradc_ctrl0, LRADC_CTRL0_SFTRST);
@@ -368,7 +365,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ clrbits_le32(&lradc_regs->hw_lradc_ctrl0, LRADC_CTRL0_CLKGATE);
+
+ /* Set on-chip ground ref */
-+ if(bEnableOnChipGroundRef) {
++ if (bEnableOnChipGroundRef) {
+ /* Enable the onchip ground ref of LRADC conversions */
+ setbits_le32(&lradc_regs->hw_lradc_ctrl0,
+ LRADC_CTRL0_ONCHIP_GROUNDREF);
@@ -400,7 +397,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ lradcInitialized = 1;
+}
+
-+void mx28_lradc_configure_channel( int eChannel,
++void mx28_lradc_configure_channel(int eChannel,
+ int bEnableDivideByTwo,
+ int bEnableAccum,
+ uint8_t u8NumSamples)
@@ -409,7 +406,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+
+ /* Set the analog divide-by two function */
-+ if(bEnableDivideByTwo) {
++ if (bEnableDivideByTwo) {
+ /* Enable the divide-by-two of a LRADC channel */
+ setbits_le32(&lradc_regs->hw_lradc_ctrl2,
+ LRADC_CTRL2_DIVIDE_BY_TWO(1 << eChannel));
@@ -429,7 +426,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ LRADC_CHn_NUM_SAMPLES(u8NumSamples));
+
+ /* Set ACCUMULATE bit of HW_LRADC_CHn register */
-+ if(bEnableAccum) {
++ if (bEnableAccum) {
+ /* Enable the accumulation of a LRADC channel */
+ setbits_le32(&lradc_regs->hw_lradc_ch0 + (eChannel * 4),
+ LRADC_CHn_ACCUMULATE);
@@ -468,7 +465,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ LRADC_DELAYn_DELAY(u32DelayCount));
+}
+
-+int mx28_lradc_enable_battery_measurement( int eTrigger,
++int mx28_lradc_enable_battery_measurement(int eTrigger,
+ uint16_t u16SamplingInterval)
+{
+ struct mx28_lradc_regs *lradc_regs =
@@ -478,8 +475,9 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ * Check if the lradc battery voltage channel
+ * is present in this product
+ */
-+ if ( (readl(&lradc_regs->hw_lradc_status)
-+ & LRADC_STATUS_CHANNEL7_PRESENT) == 0 ) return 0;
++ if ((readl(&lradc_regs->hw_lradc_status)
++ & LRADC_STATUS_CHANNEL7_PRESENT) == 0)
++ return 0;
+
+ /* Disable the channel interrupt */
+ clrbits_le32(&lradc_regs->hw_lradc_ctrl1, LRADC_CTRL1_LRADC7_IRQ_EN);
@@ -499,7 +497,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ setbits_le32(&lradc_regs->hw_lradc_conversion,
+ LRADC_CONVERSION_AUTOMATIC);
+
-+ mx28_lradc_configure_channel( 7, /* Lradc battery voltage channel */
++ mx28_lradc_configure_channel(7, /* Lradc battery voltage channel */
+ 0, /* DIVIDE_BY_TWO */
+ 0, /* ACCUMULATE */
+ 0); /* NUM_SAMPLES */
@@ -509,7 +507,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ setbits_le32(&lradc_regs->hw_lradc_ctrl0, LRADC_CTRL0_SCHEDULE(1<<7));
+
+ /* Setup the trigger loop forever, */
-+ mx28_lradc_set_delay_trigger( eTrigger, /* Trigger Index */
++ mx28_lradc_set_delay_trigger(eTrigger, /* Trigger Index */
+ (1 << 7), /* Lradc channels */
+ (1 << eTrigger), /* Restart the triggers */
+ 0, /* No loop count */
@@ -523,9 +521,9 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ LRADC_DELAYn_KICK);
+
+
-+ /* Wait for first measurement of battery. Should occur in 13 LRADC clock
-+ * cycles from the time of channel kickoff. Also add some wait time for
-+ * copy to the power supply BATT_VAL field to occur.
++ /* Wait for first measurement of battery. Should occur in 13 LRADC
++ * clock cycles from the time of channel kickoff. Also add some wait
++ * time for copy to the power supply BATT_VAL field to occur.
+ */
+ early_delay(10);
+
@@ -545,7 +543,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+}
+
+void mx28_power_setup_batt_boot(void)
- {
++{
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
@@ -648,7 +646,6 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+
+ /* bit 11 of PERSISTENT1 */
+ writel(0x800, &rtc_regs->hw_rtc_persistent1_set);
-+
+
+ battery_ready = 0;
+
@@ -729,8 +726,8 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ * power source to use during bootup.
+ */
+ int battery_good = mx28_is_batt_good();
-+ if(!battery_ready) {
-+ if(!battery_good) {
++ if (!battery_ready) {
++ if (!battery_good) {
+ struct mx28_lradc_regs *lradc_regs =
+ (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+
@@ -765,7 +762,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
}
void mx28_enable_output_rail_protection(void)
-@@ -640,7 +1010,7 @@ int mx28_get_vddio_power_source_off(void
+@@ -640,7 +1007,7 @@ int mx28_get_vddio_power_source_off(void
tmp = readl(&power_regs->hw_power_vddioctrl);
if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
@@ -774,7 +771,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
return 1;
}
}
-@@ -648,7 +1018,7 @@ int mx28_get_vddio_power_source_off(void
+@@ -648,7 +1015,7 @@ int mx28_get_vddio_power_source_off(void
if (!(readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_ENABLE_DCDC)) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
@@ -783,7 +780,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
return 1;
}
}
-@@ -887,12 +1257,14 @@ void mx28_power_init(void)
+@@ -887,12 +1254,14 @@ void mx28_power_init(void)
{
struct mx28_power_regs *power_regs =
(struct mx28_power_regs *)MXS_POWER_BASE;
@@ -799,7 +796,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
mx28_enable_output_rail_protection();
mx28_power_set_vddio(3300, 3150);
-@@ -904,8 +1276,23 @@ void mx28_power_init(void)
+@@ -904,8 +1273,23 @@ void mx28_power_init(void)
POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
@@ -817,7 +814,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ * now as the latest release kernel versions aren't aware of it
+ * and thus don't handle the proper setting/clearing of this bit.
+ */
-+ writel( 1<<7, &power_regs->hw_power_refctrl_set);
++ writel(1<<7, &power_regs->hw_power_refctrl_set);
+#endif /* CONFIG_SYS_NO_DCDC_BATT_SOURCE */
+ }
hooks/post-receive
--
armadeus
|
