[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-421-g7a1c774
Brought to you by:
sszy
Menu
▾
▴
[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-421-g7a1c774
|
From: jorasse <jo...@us...> - 2012-06-26 09:26:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 7a1c774b3a3b583567a7fb846e3188445e33b382 (commit)
from a409f2c8c84f4de478cbe30f96f2318dc1c70c81 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7a1c774b3a3b583567a7fb846e3188445e33b382
Author: Eric Jarrige <eri...@ar...>
Date: Tue Jun 26 11:25:16 2012 +0200
[UBOOT] apf9328: fix typo
-----------------------------------------------------------------------
Summary of changes:
.../armadeus/apf9328/apf9328-u-boot-2012.04.h | 410 ++++++++++++--------
1 files changed, 238 insertions(+), 172 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2012.04.h b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2012.04.h
index afeb415..ca95091 100644
--- a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2012.04.h
+++ b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2012.04.h
@@ -23,7 +23,7 @@
#define __CONFIG_H
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "5.3"
+#define CONFIG_ENV_VERSION "5.3"
#define CONFIG_IDENT_STRING " apf9328 patch 5.5"
#define CONFIG_BOARD_NAME apf9328
@@ -32,7 +32,7 @@
*/
#define CONFIG_ARM920T /* this is an ARM920T CPU */
#define CONFIG_IMX /* in a Motorola MC9328MXL Chip */
-#define CONFIG_MACH_TYPE 906 /* APF9328 */
+#define CONFIG_MACH_TYPE 906 /* APF9328 */
/*
* Enable the call to miscellaneous platform dependent initialization.
@@ -132,8 +132,8 @@
#define MTDIDS_DEFAULT "nor0=" CONFIG_MTDMAP
#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
":256k(u-boot)ro," \
- "128k(env)," \
- "128k(env2)," \
+ "128k(env)," \
+ "128k(env2)," \
"256k(firmware)," \
"2048k(kernel)," \
"-(rootfs)"
@@ -143,8 +143,8 @@
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
-#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE \
+#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer*/
+#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 16 /* max command args */
@@ -159,7 +159,7 @@
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
#define CONFIG_INITRD_TAG /* send initrd params */
/*
#define CONFIG_REVISION_TAG
@@ -168,7 +168,7 @@
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
-#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
+#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
" root=/dev/mtdblock5 rootfstype=jffs2 "
@@ -189,7 +189,7 @@
"env_version=" CONFIG_ENV_VERSION "\0" \
"consoledev=" MK_STR(ACFG_CONSOLE_DEV) "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nor0,5\0" \
+ "partition=nor0,5\0" \
"uboot_addr=" MK_STR(CONFIG_SYS_MONITOR_BASE) "\0" \
"firmware_addr=" MK_STR(CONFIG_FIRMWARE_ADDR) "\0" \
"kernel_addr=" MK_STR(CONFIG_KERNEL_ADDR) "\0" \
@@ -209,44 +209,44 @@
"${mtdparts} ${extrabootargs}; run addnfsargs addipargs; "\
"nfs ${loadaddr} " \
"${serverip}:${rootpath}/boot/${board_name}-linux.bin;" \
- "bootm ${loadaddr}\0" \
+ "bootm ${loadaddr}\0" \
"jffsboot=setenv bootargs console=${consoledev},${baudrate} " \
"${mtdparts} ${extrabootargs}; run addjffsargs addipargs; "\
"bootm ${kernel_addr}\0" \
"mmcboot=setenv bootargs console=${consoledev},${baudrate} " \
"${mtdparts} ${extrabootargs}; run addmmcargs addipargs; "\
- "bootm ${kernel_addr}\0" \
- "flash_uboot=protect off nor0,0;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_uboot=protect off nor0,0;" \
"echo Erasing FLASH;" \
- "era nor0,0;" \
+ "era nor0,0;" \
"if cp.b ${fileaddr} ${uboot_addr} ${filesize};" \
- "then protect on nor0,0;" \
+ "then protect on nor0,0;" \
"echo Flashing of uboot succeed;" \
"else echo Flashing of uboot failed;" \
"fi; \0" \
"flash_firmware=echo Erasing FLASH;" \
- "era nor0,3;" \
+ "era nor0,3;" \
"if cp.b ${fileaddr} ${firmware_addr} ${filesize} ;" \
"then echo Flashing of Firmware succeed;" \
"else echo Flashing of Firmware failed;" \
"fi\0" \
"flash_kernel=echo Erasing FLASH;" \
- "era nor0,4;" \
+ "era nor0,4;" \
"if cp.b ${fileaddr} ${kernel_addr} ${filesize} ;" \
"then echo Flashing of kernel succeed;" \
"else echo Flashing of kernel failed;" \
"fi\0" \
"flash_rootfs=echo Erasing FLASH;" \
- "era nor0,5;" \
+ "era nor0,5;" \
"if cp.b ${fileaddr} ${rootfs_addr} ${filesize};" \
"then echo Flashing of rootfs succeed;" \
"else echo Flashing of rootfs failed;" \
"fi\0" \
"flash_reset_env=env default -f; saveenv;" \
"echo Flash environment variables erased!\0" \
- "download_uboot=tftpboot ${loadaddr} ${board_name}-u-boot.bin\0" \
- "download_kernel=tftpboot ${loadaddr} ${board_name}-linux.bin\0" \
- "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.jffs2\0" \
+ "download_uboot=tftpboot ${loadaddr} ${board_name}-u-boot.bin\0"\
+ "download_kernel=tftpboot ${loadaddr} ${board_name}-linux.bin\0"\
+ "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.jffs2\0"\
"update_uboot=run download_uboot flash_uboot\0" \
"update_kernel=run download_kernel flash_kernel\0" \
"update_rootfs=run download_rootfs flash_rootfs\0" \
@@ -260,7 +260,7 @@
#define CONFIG_IMX_SERIAL
#define CONFIG_IMX_SERIAL1
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BAUDRATE 115200
/*
* GPIO
@@ -271,7 +271,7 @@
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max 32MB of FLASH memory */
-#define CONFIG_SYS_FLASH_BASE 0x10000000 /* location of flash memory*/
+#define CONFIG_SYS_FLASH_BASE 0x10000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
@@ -369,35 +369,35 @@
#define CONFIG_SYS_OSC32 32768 /* 32768 or 32000 Hz crystal */
#undef CONFIG_SYS_OSC16 /* there is no external 16MHz external clock */
-/* MPU CLOCK source before PLL (should be named CONFIG_SYS_SYS_CLK_FREQ) */
+/* MPU CLOCK source before PLL */
#define CONFIG_SYS_CLK_FREQ (512*CONFIG_SYS_OSC32)
#define CONFIG_SYS_MPCTL0_VAL 0x07B32DA5 /* 192.000017 MHz */
#define CONFIG_SYS_MPCTL1_VAL 0
-/* system clock source before PLL (should be named CONFIG_SYS_SYSPLL_CLK_FREQ)*/
+/* system clock source before PLL */
#ifndef CONFIG_SYS_OSC16
#define CONFIG_SYSPLL_CLK_FREQ (512*CONFIG_SYS_OSC32)
#if (CONFIG_SYS_OSC32 == 32000)
#define CONFIG_SYS_SPCTL0_VAL 0x043F1437 /* 96 MHz */
#define CONFIG_SYS_SPCTL1_VAL 0
-#define CONFIG_SYS_FREQ 96 /* MHz */
+#define CONFIG_SYS_FREQ 96 /* MHz */
#else /* CONFIG_SYS_OSC32 == 32768 */
#define CONFIG_SYS_SPCTL0_VAL 0x0FB32DA5 /* 96.000009 MHz */
#define CONFIG_SYS_SPCTL1_VAL 0
-#define CONFIG_SYS_FREQ 96 /* MHz */
+#define CONFIG_SYS_FREQ 96 /* MHz */
#endif /* CONFIG_SYS_OSC32 */
#else /* CONFIG_SYS_OSC16 in use */
#define CONFIG_SYSPLL_CLK_FREQ CONFIG_SYS_OSC16
#define CONFIG_SYS_SPCTL0_VAL 0x04001401 /* 96 MHz */
#define CONFIG_SYS_SPCTL1_VAL 0x0C000040
-#define CONFIG_SYS_FREQ 96 /* MHz */
+#define CONFIG_SYS_FREQ 96 /* MHz */
#endif /* CONFIG_SYS_OSC16 */
-/* external bus frequency (have to be a CONFIG_SYS_FREQ ratio) */
-#define CONFIG_SYS_BUS_FREQ 96 /* 96|48... MHz (BCLOCK and HCLOCK) */
+/* external bus frequency */
+#define CONFIG_SYS_BUS_FREQ 96 /* 96|48... MHz (BCLOCK and HCLOCK) */
#define CONFIG_USB_FREQ 48 /* 48 MHz */
#define CONFIG_PERIF1_FREQ 16 /* 16 MHz UART, Timer PWM */
-#define CONFIG_PERIF2_FREQ 48 /* 48 MHz LCD SD SPI */
+#define CONFIG_PERIF2_FREQ 48 /* 48 MHz LCD SD SPI */
#define CONFIG_PERIF3_FREQ 16 /* 16 MHz SSI */
/*
@@ -478,15 +478,15 @@
#define CONFIG_SYS_CS0_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 */
#define CONFIG_SYS_CS0_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] */
/* 3=8bits on D[7:0] 6=32 bits..*/
-#define CONFIG_SYS_CS0_SUPERVISOR_PROTECT 0 /* 1: user access prohibited*/
-#define CONFIG_SYS_CS0_WRITE_PROTECT 0 /* 1: write prohibited*/
-#define CONFIG_SYS_CS0_EB_SIGNAL_CONTROL_WRITE 1 /* 1 EB is as write signal */
+#define CONFIG_SYS_CS0_SUPERVISOR_PROTECT 0 /* 1 user access prohibited*/
+#define CONFIG_SYS_CS0_WRITE_PROTECT 0 /* 1 wr access prohibited*/
+#define CONFIG_SYS_CS0_EB_SIGNAL_CONTROL_WRITE 1 /* 1 EB used as wr signal*/
#define CONFIG_SYS_CS0_READ_CYC_LGTH 150 /* ns */
#define CONFIG_SYS_CS0_OE_ASSERT_DLY 0 /* ns */
#define CONFIG_SYS_CS0_OE_NEG_DLY 0 /* ns */
-#define CONFIG_SYS_CS0_CS_NEG_LGTH 0 /* ns CS HIGH to CS LOW : tCWH*/
-#define CONFIG_SYS_CS0_XTRA_DEAD_CYC 35 /* ns from CS HIGH to tristate*/
+#define CONFIG_SYS_CS0_CS_NEG_LGTH 0 /* max 30ns CS HIGH to LOW */
+#define CONFIG_SYS_CS0_XTRA_DEAD_CYC 35 /* ns CS HIGH to tristate */
#define CONFIG_SYS_CS0_WRITE_XTRA_LGTH 0 /* ns */
#define CONFIG_SYS_CS0_EB_ASSERT_DLY 0 /* ns */
@@ -494,155 +494,155 @@
#define CONFIG_SYS_CS0_CS_ASSERT_NEG_DLY 0 /* ns */
#define CONFIG_SYS_CS0_SYNC_ENABLE 1 /* enable sync burst mode */
-#define CONFIG_SYS_CS0_SYNC_PAGE_MODE_EMUL 1 /* enable page mode emulation*/
-#define CONFIG_SYS_CS0_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes)*/
+#define CONFIG_SYS_CS0_SYNC_PAGE_MODE_EMUL 1
+#define CONFIG_SYS_CS0_SYNC_PAGE_SIZE 0 /* 4 words page size */
#define CONFIG_SYS_CS0_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
#define CONFIG_SYS_CS0_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
#define CONFIG_SYS_CS0_SYNC_DAT_OUT_LGTH 25 /* ns */
/* CS1 configuration for */
-#define CONFIG_SYS_CS1_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 peripherals */
-#define CONFIG_SYS_CS1_PIN_ASSERT 0 /* chip select pin state when */
- /* chip select disabled */
-#define CONFIG_SYS_CS1_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
- /* 3=8bits on D[7:0] 6=32 bits.. */
-#define CONFIG_SYS_CS1_SUPERVISOR_PROTECT 0 /* 1 : user mode access prohibited */
-#define CONFIG_SYS_CS1_WRITE_PROTECT 0 /* 1 : write access prohibited */
-#define CONFIG_SYS_CS1_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal */
+#define CONFIG_SYS_CS1_CHIP_SELECT_ENABLE 1 /* 1: enable CS1 */
+#define CONFIG_SYS_CS1_PIN_ASSERT 0 /* chip select pin state */
+ /* when chip select disabled */
+#define CONFIG_SYS_CS1_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] */
+ /* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS1_SUPERVISOR_PROTECT 0 /* 1 user access prohibited*/
+#define CONFIG_SYS_CS1_WRITE_PROTECT 0 /* 1 wr access prohibited */
+#define CONFIG_SYS_CS1_EB_SIGNAL_CONTROL_WRITE 1 /* 1 EB used as wr signal*/
#define CONFIG_SYS_CS1_READ_CYC_LGTH 50 /* ns */
#define CONFIG_SYS_CS1_OE_ASSERT_DLY 0 /* ns */
#define CONFIG_SYS_CS1_OE_NEG_DLY 0 /* ns */
-#define CONFIG_SYS_CS1_CS_NEG_LGTH 0 /* max 30 ns CS HIGH to CS LOW at 100MHz */
-#define CONFIG_SYS_CS1_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
+#define CONFIG_SYS_CS1_CS_NEG_LGTH 0 /* max 30ns CS HIGH to LOW*/
+#define CONFIG_SYS_CS1_XTRA_DEAD_CYC 0 /* ns CS HIGH to tristate */
#define CONFIG_SYS_CS1_WRITE_XTRA_LGTH 0 /* ns */
#define CONFIG_SYS_CS1_EB_ASSERT_DLY 0 /* ns */
#define CONFIG_SYS_CS1_EB_NEG_DLY 0 /* ns */
#define CONFIG_SYS_CS1_CS_ASSERT_NEG_DLY 0 /* ns */
-#define CONFIG_SYS_CS1_SYNC_ENABLE 0 /* enable synchronous burst mode */
-#define CONFIG_SYS_CS1_SYNC_PAGE_MODE_EMUL 0 /* enable page mode emulation */
-#define CONFIG_SYS_CS1_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS1_SYNC_ENABLE 0 /* enable sync burst mode */
+#define CONFIG_SYS_CS1_SYNC_PAGE_MODE_EMUL 0
+#define CONFIG_SYS_CS1_SYNC_PAGE_SIZE 0 /* 4 words page size */
#define CONFIG_SYS_CS1_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
#define CONFIG_SYS_CS1_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
#define CONFIG_SYS_CS1_SYNC_DAT_OUT_LGTH 0 /* ns */
/* CS2 configuration for */
-#define CONFIG_SYS_CS2_CHIP_SELECT_ENABLE 0 /* 1 : enable CS0 peripherals */
-#define CONFIG_SYS_CS2_PIN_ASSERT 0 /* chip select pin state when */
- /*chip select disabled */
-#define CONFIG_SYS_CS2_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
- /* 3=8bits on D[7:0] 6=32 bits.. */
-#define CONFIG_SYS_CS2_SUPERVISOR_PROTECT 0 /* 1 : user mode access prohibited */
-#define CONFIG_SYS_CS2_WRITE_PROTECT 0 /* 1 : write access prohibited */
-#define CONFIG_SYS_CS2_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal */
+#define CONFIG_SYS_CS2_CHIP_SELECT_ENABLE 0 /* 1 : enable CS0 */
+#define CONFIG_SYS_CS2_PIN_ASSERT 0 /* chip select pin state */
+ /* when chip select disabled */
+#define CONFIG_SYS_CS2_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] */
+ /* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS2_SUPERVISOR_PROTECT 0 /* 1 user access prohibited*/
+#define CONFIG_SYS_CS2_WRITE_PROTECT 0 /* 1 wr access prohibited */
+#define CONFIG_SYS_CS2_EB_SIGNAL_CONTROL_WRITE 1 /* 1 EB used as wr signal*/
#define CONFIG_SYS_CS2_READ_CYC_LGTH 0 /* ns */
#define CONFIG_SYS_CS2_OE_ASSERT_DLY 0 /* ns */
#define CONFIG_SYS_CS2_OE_NEG_DLY 0 /* ns */
-#define CONFIG_SYS_CS2_CS_NEG_LGTH 0 /* max 30 ns CS HIGH to CS LOW at 100MHz */
-#define CONFIG_SYS_CS2_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
+#define CONFIG_SYS_CS2_CS_NEG_LGTH 0 /* max 30ns CS HIGH to LOW*/
+#define CONFIG_SYS_CS2_XTRA_DEAD_CYC 0 /* ns CS HIGH to tristate */
#define CONFIG_SYS_CS2_WRITE_XTRA_LGTH 0 /* ns */
#define CONFIG_SYS_CS2_EB_ASSERT_DLY 0 /* ns */
#define CONFIG_SYS_CS2_EB_NEG_DLY 0 /* ns */
#define CONFIG_SYS_CS2_CS_ASSERT_NEG_DLY 0 /* ns */
-#define CONFIG_SYS_CS2_SYNC_ENABLE 0 /* enable synchronous burst mode */
-#define CONFIG_SYS_CS2_SYNC_PAGE_MODE_EMUL 0 /* enable page mode emulation */
-#define CONFIG_SYS_CS2_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS2_SYNC_ENABLE 0 /* enable sync burst mode */
+#define CONFIG_SYS_CS2_SYNC_PAGE_MODE_EMUL 0
+#define CONFIG_SYS_CS2_SYNC_PAGE_SIZE 0 /* 4 words page size */
#define CONFIG_SYS_CS2_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
#define CONFIG_SYS_CS2_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
#define CONFIG_SYS_CS2_SYNC_DAT_OUT_LGTH 0 /* ns */
/* CS3 configuration for ISP1760 */
-#define CONFIG_SYS_CS3_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 peripherals */
-#define CONFIG_SYS_CS3_PIN_ASSERT 0 /* chip select pin state when */
- /* chip select disabled */
-#define CONFIG_SYS_CS3_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
- /* 3=8bits on D[7:0] 6=32 bits.. */
-#define CONFIG_SYS_CS3_SUPERVISOR_PROTECT 0 /* 1: user mode access prohibited */
-#define CONFIG_SYS_CS3_WRITE_PROTECT 0 /* 1: write access prohibited */
-#define CONFIG_SYS_CS3_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal */
+#define CONFIG_SYS_CS3_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 */
+#define CONFIG_SYS_CS3_PIN_ASSERT 0 /* chip select pin state */
+ /* when chip select disabled */
+#define CONFIG_SYS_CS3_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] */
+ /* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS3_SUPERVISOR_PROTECT 0 /* 1 user access prohibited*/
+#define CONFIG_SYS_CS3_WRITE_PROTECT 0 /* 1 wr access prohibited */
+#define CONFIG_SYS_CS3_EB_SIGNAL_CONTROL_WRITE 1 /* 1 EB used as wr signal*/
#define CONFIG_SYS_CS3_READ_CYC_LGTH 110 /* ns */
#define CONFIG_SYS_CS3_OE_ASSERT_DLY 45 /* ns */
#define CONFIG_SYS_CS3_OE_NEG_DLY 40 /* ns */
-#define CONFIG_SYS_CS3_CS_NEG_LGTH 30 /* max 30 ns CS HIGH to CS LOW at 100MHz */
-#define CONFIG_SYS_CS3_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
+#define CONFIG_SYS_CS3_CS_NEG_LGTH 30 /* max 30ns CS HIGH to LOW*/
+#define CONFIG_SYS_CS3_XTRA_DEAD_CYC 0 /* ns CS HIGH to tristate */
#define CONFIG_SYS_CS3_WRITE_XTRA_LGTH 0 /* ns */
#define CONFIG_SYS_CS3_EB_ASSERT_DLY 45 /* ns */
#define CONFIG_SYS_CS3_EB_NEG_DLY 45 /* ns */
#define CONFIG_SYS_CS3_CS_ASSERT_NEG_DLY 35 /* ns */
-#define CONFIG_SYS_CS3_SYNC_ENABLE 0 /* enable synchronous burst mode */
-#define CONFIG_SYS_CS3_SYNC_PAGE_MODE_EMUL 0 /* enable page mode emulation */
-#define CONFIG_SYS_CS3_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS3_SYNC_ENABLE 0 /* enable sync burst mode */
+#define CONFIG_SYS_CS3_SYNC_PAGE_MODE_EMUL 0
+#define CONFIG_SYS_CS3_SYNC_PAGE_SIZE 0 /* 4 words page size */
#define CONFIG_SYS_CS3_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
#define CONFIG_SYS_CS3_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
#define CONFIG_SYS_CS3_SYNC_DAT_OUT_LGTH 0 /* ns */
/* CS4 configuration for DM9000 ethernet chipset */
-#define CONFIG_SYS_CS4_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 peripherals */
-#define CONFIG_SYS_CS4_PIN_ASSERT 0 /* chip select pin state when */
- /* chip select disabled */
-#define CONFIG_SYS_CS4_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
- /* 3=8bits on D[7:0] 6=32 bits.. */
-#define CONFIG_SYS_CS4_SUPERVISOR_PROTECT 0 /* 1 : user mode access prohibited */
-#define CONFIG_SYS_CS4_WRITE_PROTECT 0 /* 1 : write access prohibited */
-#define CONFIG_SYS_CS4_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal */
+#define CONFIG_SYS_CS4_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 */
+#define CONFIG_SYS_CS4_PIN_ASSERT 0 /* chip select pin state */
+ /* when chip select disabled */
+#define CONFIG_SYS_CS4_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] */
+ /* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS4_SUPERVISOR_PROTECT 0 /* 1 user access prohibited*/
+#define CONFIG_SYS_CS4_WRITE_PROTECT 0 /* 1 wr access prohibited */
+#define CONFIG_SYS_CS4_EB_SIGNAL_CONTROL_WRITE 1 /* 1 EB used as wr signal*/
#define CONFIG_SYS_CS4_READ_CYC_LGTH 72 /* ns */
#define CONFIG_SYS_CS4_OE_ASSERT_DLY 5 /* ns */
#define CONFIG_SYS_CS4_OE_NEG_DLY 45 /* ns */
-#define CONFIG_SYS_CS4_CS_NEG_LGTH 30 /* max 30 ns CS HIGH to CS LOW at 100MHz */
-#define CONFIG_SYS_CS4_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
+#define CONFIG_SYS_CS4_CS_NEG_LGTH 30 /* max 30ns CS HIGH to LOW*/
+#define CONFIG_SYS_CS4_XTRA_DEAD_CYC 0 /* ns CS HIGH to tristate */
#define CONFIG_SYS_CS4_WRITE_XTRA_LGTH 0 /* ns */
#define CONFIG_SYS_CS4_EB_ASSERT_DLY 5 /* ns */
#define CONFIG_SYS_CS4_EB_NEG_DLY 45 /* ns */
#define CONFIG_SYS_CS4_CS_ASSERT_NEG_DLY 0 /* ns */
-#define CONFIG_SYS_CS4_SYNC_ENABLE 0 /* enable synchronous burst mode */
-#define CONFIG_SYS_CS4_SYNC_PAGE_MODE_EMUL 0 /* enable page mode emulation */
-#define CONFIG_SYS_CS4_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS4_SYNC_ENABLE 0 /* enable sync burst mode */
+#define CONFIG_SYS_CS4_SYNC_PAGE_MODE_EMUL 0
+#define CONFIG_SYS_CS4_SYNC_PAGE_SIZE 0 /* 4 words page size */
#define CONFIG_SYS_CS4_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
#define CONFIG_SYS_CS4_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
#define CONFIG_SYS_CS4_SYNC_DAT_OUT_LGTH 0 /* ns */
/* CS5 configuration for */
-#define CONFIG_SYS_CS5_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 peripherals */
-#define CONFIG_SYS_CS5_PIN_ASSERT 0 /* chip select pin state when */
- /* chip select disabled */
-#define CONFIG_SYS_CS5_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
- /* 3=8bits on D[7:0] 6=32 bits.. */
-#define CONFIG_SYS_CS5_SUPERVISOR_PROTECT 0 /* 1: user mode access prohibited */
-#define CONFIG_SYS_CS5_WRITE_PROTECT 0 /* 1 : write access prohibited */
-#define CONFIG_SYS_CS5_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal */
+#define CONFIG_SYS_CS5_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 */
+#define CONFIG_SYS_CS5_PIN_ASSERT 0 /* chip select pin state */
+ /* when chip select disabled */
+#define CONFIG_SYS_CS5_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] */
+ /* 3=8bits on D[7:0] 6=32 bits.. */
+#define CONFIG_SYS_CS5_SUPERVISOR_PROTECT 0 /* 1 user access prohibited*/
+#define CONFIG_SYS_CS5_WRITE_PROTECT 0 /* 1 wr access prohibited */
+#define CONFIG_SYS_CS5_EB_SIGNAL_CONTROL_WRITE 1 /* 1 EB used as wr signal*/
#define CONFIG_SYS_CS5_DTACK_SELECT 1 /* Activate DTACK fonction */
/* (asynchrone bus) */
-#define CONFIG_SYS_CS5_READ_CYC_LGTH -1 /* ns or -1 to DTACK function */
+#define CONFIG_SYS_CS5_READ_CYC_LGTH -1 /* ns or -1 DTACK function*/
#define CONFIG_SYS_CS5_OE_ASSERT_DLY 10 /* ns */
#define CONFIG_SYS_CS5_OE_NEG_DLY 10 /* ns */
-#define CONFIG_SYS_CS5_CS_NEG_LGTH 10 /* max 30 ns CS HIGH to CS LOW at 100MHz */
-#define CONFIG_SYS_CS5_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
+#define CONFIG_SYS_CS5_CS_NEG_LGTH 10 /* max 30ns CS HIGH to LOW*/
+#define CONFIG_SYS_CS5_XTRA_DEAD_CYC 0 /* ns CS HIGH to tristate */
#define CONFIG_SYS_CS5_WRITE_XTRA_LGTH 0 /* ns */
#define CONFIG_SYS_CS5_EB_ASSERT_DLY 10 /* ns */
#define CONFIG_SYS_CS5_EB_NEG_DLY 10 /* ns */
#define CONFIG_SYS_CS5_CS_ASSERT_NEG_DLY 0 /* ns */
-#define CONFIG_SYS_CS5_SYNC_ENABLE 0 /* enable synchron burst mode */
-#define CONFIG_SYS_CS5_SYNC_PAGE_MODE_EMUL 0 /* enable page mode emulation */
-#define CONFIG_SYS_CS5_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
+#define CONFIG_SYS_CS5_SYNC_ENABLE 0 /* enable sync burst mode */
+#define CONFIG_SYS_CS5_SYNC_PAGE_MODE_EMUL 0
+#define CONFIG_SYS_CS5_SYNC_PAGE_SIZE 0 /* 4 words page size */
#define CONFIG_SYS_CS5_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
#define CONFIG_SYS_CS5_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
#define CONFIG_SYS_CS5_SYNC_DAT_OUT_LGTH 0 /* ns */
@@ -726,7 +726,7 @@
* All Equations are automatic
*/
-#define CONFIG_SYS_HCLK_LGTH (1000/CONFIG_SYS_BUS_FREQ) /* ns */
+#define CONFIG_SYS_HCLK_LGTH (1000/CONFIG_SYS_BUS_FREQ) /* ns */
/* USB 48 MHz ; BUS 96MHz*/
#ifdef CONFIG_SYS_OSC16
@@ -735,7 +735,7 @@
#define CSCR_MASK 0x23000003
#endif
#define CONFIG_SYS_CSCR_VAL\
- (CSCR_MASK \
+ (CSCR_MASK \
|((((CONFIG_SYS_FREQ/CONFIG_USB_FREQ)-1)&0x07)<<26) \
|((((CONFIG_SYS_FREQ/CONFIG_SYS_BUS_FREQ)-1)&0x0F)<<10))
@@ -801,7 +801,7 @@
/* Issue Precharge all Command to SDRAM*/
#define CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL\
- (((CONFIG_SYS_SDRAM_SINGLE_ACCESS)&0x1)<<(CONFIG_SYS_SDRAM_NUM_COL+4+9))
+ (((CONFIG_SYS_SDRAM_SINGLE_ACCESS)&0x1)<<(CONFIG_SYS_SDRAM_NUM_COL+13))
/*
* CSxU_VAL:
@@ -818,15 +818,21 @@
* | CSA |EBC| DSZ | 0|SP|0|WP|0 0|PA |CSEN |
*/
#define CONFIG_SYS_CS0U_VAL\
- ((((CONFIG_SYS_CS0_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
- |((((CONFIG_SYS_CS0_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
- |(((((CONFIG_SYS_CS0_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
- |((((CONFIG_SYS_CS0_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
- |((((CONFIG_SYS_CS0_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ ((((CONFIG_SYS_CS0_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)\
+ |((((CONFIG_SYS_CS0_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+ |(((((CONFIG_SYS_CS0_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+ |((((CONFIG_SYS_CS0_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+ |((((CONFIG_SYS_CS0_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
|((CONFIG_SYS_CS0_SYNC_ENABLE&0x01)<<20)\
|((CONFIG_SYS_CS0_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
|((CONFIG_SYS_CS0_SYNC_PAGE_SIZE&0x03)<<22)\
- |((((CONFIG_SYS_CS0_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |((((CONFIG_SYS_CS0_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
|((CONFIG_SYS_CS0_SYNC_BURST_CLK_DIV&0x03)<<28))
#define CONFIG_SYS_CS0L_VAL\
@@ -835,22 +841,33 @@
|((CONFIG_SYS_CS0_SUPERVISOR_PROTECT&0x01)<<6)\
|((CONFIG_SYS_CS0_DATA_PORT_SIZE&0x07)<<8)\
|((CONFIG_SYS_CS0_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
- |((((CONFIG_SYS_CS0_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
- |(((((CONFIG_SYS_CS0_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
- |(((((CONFIG_SYS_CS0_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
- |(((((CONFIG_SYS_CS0_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
- |(((((CONFIG_SYS_CS0_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+ |((((CONFIG_SYS_CS0_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+ |(((((CONFIG_SYS_CS0_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ |(((((CONFIG_SYS_CS0_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+ |(((((CONFIG_SYS_CS0_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |(((((CONFIG_SYS_CS0_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
#define CONFIG_SYS_CS1U_VAL\
- ((((CONFIG_SYS_CS1_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
- |((((CONFIG_SYS_CS1_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
- |(((((CONFIG_SYS_CS1_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
- |((((CONFIG_SYS_CS1_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
- |((((CONFIG_SYS_CS1_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ ((((CONFIG_SYS_CS1_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)\
+ |((((CONFIG_SYS_CS1_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+ |(((((CONFIG_SYS_CS1_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+ |((((CONFIG_SYS_CS1_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+ |((((CONFIG_SYS_CS1_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
|((CONFIG_SYS_CS1_SYNC_ENABLE&0x01)<<20)\
|((CONFIG_SYS_CS1_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
|((CONFIG_SYS_CS1_SYNC_PAGE_SIZE&0x03)<<22)\
- |((((CONFIG_SYS_CS1_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |((((CONFIG_SYS_CS1_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
|((CONFIG_SYS_CS1_SYNC_BURST_CLK_DIV&0x03)<<28))
#define CONFIG_SYS_CS1L_VAL\
@@ -860,22 +877,33 @@
|((CONFIG_SYS_CS1_SUPERVISOR_PROTECT&0x01)<<6)\
|((CONFIG_SYS_CS1_DATA_PORT_SIZE&0x07)<<8)\
|((CONFIG_SYS_CS1_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
- |((((CONFIG_SYS_CS1_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
- |(((((CONFIG_SYS_CS1_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
- |(((((CONFIG_SYS_CS1_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
- |(((((CONFIG_SYS_CS1_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
- |(((((CONFIG_SYS_CS1_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+ |((((CONFIG_SYS_CS1_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+ |(((((CONFIG_SYS_CS1_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ |(((((CONFIG_SYS_CS1_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+ |(((((CONFIG_SYS_CS1_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |(((((CONFIG_SYS_CS1_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
#define CONFIG_SYS_CS2U_VAL\
- (((((CONFIG_SYS_CS2_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
- |((((CONFIG_SYS_CS2_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
- |(((((CONFIG_SYS_CS2_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
- |((((CONFIG_SYS_CS2_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
- |(((CONFIG_SYS_CS2_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ (((((CONFIG_SYS_CS2_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)\
+ |((((CONFIG_SYS_CS2_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+ |(((((CONFIG_SYS_CS2_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+ |((((CONFIG_SYS_CS2_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+ |(((CONFIG_SYS_CS2_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
|((CONFIG_SYS_CS2_SYNC_ENABLE&0x01)<<20)\
|((CONFIG_SYS_CS2_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
|((CONFIG_SYS_CS2_SYNC_PAGE_SIZE&0x03)<<22)\
- |((((CONFIG_SYS_CS2_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |((((CONFIG_SYS_CS2_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
|((CONFIG_SYS_CS2_SYNC_BURST_CLK_DIV&0x03)<<28))
#define CONFIG_SYS_CS2L_VAL\
@@ -885,22 +913,33 @@
|((CONFIG_SYS_CS2_SUPERVISOR_PROTECT&0x01)<<6)\
|((CONFIG_SYS_CS2_DATA_PORT_SIZE&0x07)<<8)\
|((CONFIG_SYS_CS2_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
- |((((CONFIG_SYS_CS2_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
- |(((((CONFIG_SYS_CS2_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
- |(((((CONFIG_SYS_CS2_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
- |(((((CONFIG_SYS_CS2_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
- |(((((CONFIG_SYS_CS2_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+ |((((CONFIG_SYS_CS2_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+ |(((((CONFIG_SYS_CS2_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ |(((((CONFIG_SYS_CS2_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+ |(((((CONFIG_SYS_CS2_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |(((((CONFIG_SYS_CS2_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
#define CONFIG_SYS_CS3U_VAL\
- ((((CONFIG_SYS_CS3_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
- |((((CONFIG_SYS_CS3_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
- |(((((CONFIG_SYS_CS3_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
- |((((CONFIG_SYS_CS3_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
- |((((CONFIG_SYS_CS3_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ ((((CONFIG_SYS_CS3_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)\
+ |((((CONFIG_SYS_CS3_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+ |(((((CONFIG_SYS_CS3_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+ |((((CONFIG_SYS_CS3_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+ |((((CONFIG_SYS_CS3_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
|((CONFIG_SYS_CS3_SYNC_ENABLE&0x01)<<20)\
|((CONFIG_SYS_CS3_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
|((CONFIG_SYS_CS3_SYNC_PAGE_SIZE&0x03)<<22)\
- |((((CONFIG_SYS_CS3_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |((((CONFIG_SYS_CS3_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
|((CONFIG_SYS_CS3_SYNC_BURST_CLK_DIV&0x03)<<28))
#define CONFIG_SYS_CS3L_VAL\
@@ -910,22 +949,33 @@
|((CONFIG_SYS_CS3_SUPERVISOR_PROTECT&0x01)<<6)\
|((CONFIG_SYS_CS3_DATA_PORT_SIZE&0x07)<<8)\
|((CONFIG_SYS_CS3_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
- |((((CONFIG_SYS_CS3_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
- |(((((CONFIG_SYS_CS3_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
- |(((((CONFIG_SYS_CS3_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
- |(((((CONFIG_SYS_CS3_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
- |(((((CONFIG_SYS_CS3_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+ |((((CONFIG_SYS_CS3_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+ |(((((CONFIG_SYS_CS3_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ |(((((CONFIG_SYS_CS3_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+ |(((((CONFIG_SYS_CS3_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |(((((CONFIG_SYS_CS3_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
#define CONFIG_SYS_CS4U_VAL\
- (((((CONFIG_SYS_CS4_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
- |((((CONFIG_SYS_CS4_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
- |(((((CONFIG_SYS_CS4_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
- |((((CONFIG_SYS_CS4_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
- |((((CONFIG_SYS_CS4_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16))\
+ (((((CONFIG_SYS_CS4_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)\
+ |((((CONFIG_SYS_CS4_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+ |(((((CONFIG_SYS_CS4_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+ |((((CONFIG_SYS_CS4_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+ |((((CONFIG_SYS_CS4_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16))\
|((CONFIG_SYS_CS4_SYNC_ENABLE&0x01)<<20)\
|((CONFIG_SYS_CS4_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
|((CONFIG_SYS_CS4_SYNC_PAGE_SIZE&0x03)<<22)\
- |((((CONFIG_SYS_CS4_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |((((CONFIG_SYS_CS4_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
|((CONFIG_SYS_CS4_SYNC_BURST_CLK_DIV&0x03)<<28))
#define CONFIG_SYS_CS4L_VAL\
@@ -935,22 +985,33 @@
|((CONFIG_SYS_CS4_SUPERVISOR_PROTECT&0x01)<<6)\
|((CONFIG_SYS_CS4_DATA_PORT_SIZE&0x07)<<8)\
|((CONFIG_SYS_CS4_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
- |((((CONFIG_SYS_CS4_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
- |(((((CONFIG_SYS_CS4_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
- |(((((CONFIG_SYS_CS4_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
- |(((((CONFIG_SYS_CS4_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
- |(((((CONFIG_SYS_CS4_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+ |((((CONFIG_SYS_CS4_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+ |(((((CONFIG_SYS_CS4_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ |(((((CONFIG_SYS_CS4_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+ |(((((CONFIG_SYS_CS4_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |(((((CONFIG_SYS_CS4_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
#define CONFIG_SYS_CS5U_VAL\
- ((((CONFIG_SYS_CS5_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)\
- |((((CONFIG_SYS_CS5_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
- |(((((CONFIG_SYS_CS5_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
- |((((CONFIG_SYS_CS5_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
- |((((CONFIG_SYS_CS5_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ ((((CONFIG_SYS_CS5_XTRA_DEAD_CYC+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)\
+ |((((CONFIG_SYS_CS5_WRITE_XTRA_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<4)\
+ |(((((CONFIG_SYS_CS5_READ_CYC_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)-1)&0x3F)<<8)\
+ |((((CONFIG_SYS_CS5_CS_NEG_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x03)<<14)\
+ |((((CONFIG_SYS_CS5_SYNC_DAT_OUT_LGTH+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
|((CONFIG_SYS_CS5_SYNC_ENABLE&0x01)<<20)\
|((CONFIG_SYS_CS5_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
|((CONFIG_SYS_CS5_SYNC_PAGE_SIZE&0x03)<<22)\
- |((((CONFIG_SYS_CS5_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |((((CONFIG_SYS_CS5_SYNC_BURST_CLK_START+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
|((CONFIG_SYS_CS5_SYNC_BURST_CLK_DIV&0x03)<<28)\
|((CONFIG_SYS_CS5_DTACK_SELECT&0x01)<<31))
@@ -961,10 +1022,15 @@
|((CONFIG_SYS_CS5_SUPERVISOR_PROTECT&0x01)<<6)\
|((CONFIG_SYS_CS5_DATA_PORT_SIZE&0x07)<<8)\
|((CONFIG_SYS_CS5_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
- |((((CONFIG_SYS_CS5_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
- |(((((CONFIG_SYS_CS5_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
- |(((((CONFIG_SYS_CS5_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
- |(((((CONFIG_SYS_CS5_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
- |(((((CONFIG_SYS_CS5_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)/CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
+ |((((CONFIG_SYS_CS5_CS_ASSERT_NEG_DLY+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<12)\
+ |(((((CONFIG_SYS_CS5_EB_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<16)\
+ |(((((CONFIG_SYS_CS5_EB_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<20)\
+ |(((((CONFIG_SYS_CS5_OE_NEG_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<24)\
+ |(((((CONFIG_SYS_CS5_OE_ASSERT_DLY*2)+CONFIG_SYS_HCLK_LGTH-1)\
+ /CONFIG_SYS_HCLK_LGTH)&0x0F)<<28))
#endif /* __CONFIG_H */
hooks/post-receive
--
armadeus
|
