[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-420-ga409f2c
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-420-ga409f2c
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From: jorasse <jo...@us...> - 2012-06-25 22:27:18
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via a409f2c8c84f4de478cbe30f96f2318dc1c70c81 (commit)
from 3da68edb55e2da1289437c5928c3c8d70f6ded8a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a409f2c8c84f4de478cbe30f96f2318dc1c70c81
Author: Eric Jarrige <eri...@ar...>
Date: Tue Jun 26 00:29:39 2012 +0200
[UBOOT] apf28: fix typo / checkpatch
-----------------------------------------------------------------------
Summary of changes:
.../u-boot/2012.04/501-imx28-update-and-fix.patch | 2 +-
patches/u-boot/2012.04/502-add-apf28.patch | 104 ++++++++++----------
2 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/patches/u-boot/2012.04/501-imx28-update-and-fix.patch b/patches/u-boot/2012.04/501-imx28-update-and-fix.patch
index ecb9f6c..0cddc29 100644
--- a/patches/u-boot/2012.04/501-imx28-update-and-fix.patch
+++ b/patches/u-boot/2012.04/501-imx28-update-and-fix.patch
@@ -36,7 +36,7 @@ index 963e4f3..112ae6e 100644
return (0);
}
-+ sync ();
++ sync();
+ *addr = save[i];
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
diff --git a/patches/u-boot/2012.04/502-add-apf28.patch b/patches/u-boot/2012.04/502-add-apf28.patch
index c1831cd..b80c581 100644
--- a/patches/u-boot/2012.04/502-add-apf28.patch
+++ b/patches/u-boot/2012.04/502-add-apf28.patch
@@ -51,7 +51,7 @@ index 0000000..30906a0
+
+ifndef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_IMX_OCOTP) += cmd_ocotp.o
-+COBJS := $(COBJS-y) mx28_bcb.o apf28.o
++COBJS := $(COBJS-y) mx28_bcb.o apf28.o
+else
+COBJS := spl_boot.o
+endif
@@ -81,7 +81,7 @@ index 0000000..c00b55c
+/*
+ * APF28 motherboard based on DENX M28 module
+ *
-+ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
+ * Copyright (C) 2011 Marek Vasut <mar...@gm...>
+ * on behalf of DENX Software Engineering GmbH
+ *
@@ -260,8 +260,8 @@ index 0000000..c00b55c
+
+ writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_clr);
+
-+ mac[0] = (ACFG_OUI>> 16) & 0xff;
-+ mac[1] = (ACFG_OUI>> 8) & 0xff;
++ mac[0] = (ACFG_OUI >> 16) & 0xff;
++ mac[1] = (ACFG_OUI >> 8) & 0xff;
+
+ if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
+ mac[5] += 1;
@@ -274,9 +274,9 @@ new file mode 100644
index 0000000..e025334
--- /dev/null
+++ b/board/armadeus/apf28/cmd_ocotp.c
-@@ -0,0 +1,275 @@
+@@ -0,0 +1,269 @@
+/*
-+ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
@@ -314,16 +314,14 @@ index 0000000..e025334
+ u32 otpctrl;
+
+ if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
-+ MXS_OCOTP_MAX_TIMEOUT))
-+ {
-+ printf("OCOTP still busy after timeout \n");
++ MXS_OCOTP_MAX_TIMEOUT)) {
++ printf("OCOTP still busy after timeout\n");
+ return -1;
+ }
+
+ otpctrl = readl(&ocotp_regs->hw_ocotp_ctrl_reg);
+
-+ if (otpctrl & OCOTP_CTRL_ERROR)
-+ {
++ if (otpctrl & OCOTP_CTRL_ERROR) {
+ printf("OCOTP error: CTRLÂ register value: 0x%x\n", otpctrl);
+ return -1;
+ }
@@ -335,24 +333,21 @@ index 0000000..e025334
+{
+ u32 val = 0, otpctrl;
+
-+ if ((addr < 0) || (addr > 0x27))
-+ {
++ if ((addr < 0) || (addr > 0x27)) {
+ printf("Invalid address! (should be between 0 and 0x27)\n");
+ return val;
+ }
-+
++
+ if (otp_error())
-+ {
+ return val;
-+ }
++
+ otpctrl = readl(&ocotp_regs->hw_ocotp_ctrl_reg);
+
-+ if (otpctrl & OCOTP_CTRL_ERROR)
-+ {
++ if (otpctrl & OCOTP_CTRL_ERROR) {
+ printf("OCOTP in error: CTRLÂ register value: 0x%x\n", otpctrl);
+ return val;
+ }
-+
++
+ writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+ if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
@@ -377,8 +372,7 @@ index 0000000..e025334
+ struct mx28_power_regs *power_regs =
+ (struct mx28_power_regs *)MXS_POWER_BASE;
+
-+ if ((addr < 0) || (addr > 0x27))
-+ {
++ if ((addr < 0) || (addr > 0x27)) {
+ printf("Invalid address! (should be between 0 and 0x27)\n");
+ return -1;
+ }
@@ -390,7 +384,8 @@ index 0000000..e025334
+
+ /* Force HBUS and CPU down to 24 MHz */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, &clkctrl_regs->hw_clkctrl_clkseq_set);
-+ writel(1 << CLKCTRL_HBUS_DIV_OFFSET, &clkctrl_regs->hw_clkctrl_hbus_set);
++ writel(1 << CLKCTRL_HBUS_DIV_OFFSET,
++ &clkctrl_regs->hw_clkctrl_hbus_set);
+ writel(CLKCTRL_HBUS_DIV_MASK - 1, &clkctrl_regs->hw_clkctrl_hbus_clr);
+
+ /* Change VDDIO to 2.8V while burning the fuses */
@@ -399,9 +394,8 @@ index 0000000..e025334
+ /* Disable read bank */
+ writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_clr);
+
-+ /* Check ocotp status busy and error */
-+ if (!otp_error())
-+ {
++ /* Check ocotp status busy and error */
++ if (!otp_error()) {
+ /* initiate fuse blow at addr.. */
+ writel(OCOTP_CTRL_WR_UNLOCK_KEY | (addr & OCOTP_CTRL_ADDR_MASK),
+ &ocotp_regs->hw_ocotp_ctrl);
@@ -410,21 +404,21 @@ index 0000000..e025334
+ writel(data, &ocotp_regs->hw_ocotp_data);
+
+ /* wait end of blowing process + 2us wrtie postamble*/
-+ if (otp_error())
-+ {
-+ printf("OCOTP blow failed!\n");
++ if (otp_error()) {
++ printf("OCOTP blow failed!\n");
+ err = -1;
+ }
+ udelay(2);
+
-+ } else err = -1;
++ } else
++ err = -1;
+
+
+ /*Â restore HBUS, CLKSEQ and VDDIO */
+ writel(vddio, &power_regs->hw_power_vddioctrl);
+ writel(hbus, &clkctrl_regs->hw_clkctrl_hbus);
+ writel(clkseq, &clkctrl_regs->hw_clkctrl_clkseq);
-+
++
+ return err;
+}
+
@@ -433,7 +427,7 @@ index 0000000..e025334
+ s32 err = 0;
+
+ if (0 == strncmp(func_name, "fecmac", 6)) {
-+ s32 addr = func_name[6] -'0';
++ s32 addr = func_name[6] - '0';
+
+ if ((addr >= 0) && (addr < 2)) {
+ /* Read the Mac address and print it */
@@ -441,7 +435,7 @@ index 0000000..e025334
+
+ printf("%s address: ", func_name);
+ printf("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n\n",
-+ (ACFG_OUI>> 16) & 0xff, (ACFG_OUI>> 8) & 0xff,
++ (ACFG_OUI >> 16) & 0xff, (ACFG_OUI >> 8) & 0xff,
+ (val >> 24) & 0xff, (val >> 16) & 0xff,
+ (val >> 8) & 0xff, val & 0xff);
+ } else {
@@ -461,7 +455,7 @@ index 0000000..e025334
+ s32 err = 0;
+
+ if (0 == strncmp(func_name, "fecmac", 6)) {
-+ s32 addr = func_name[6] -'0';
++ s32 addr = func_name[6] - '0';
+
+ if ((addr >= 0) && (addr < 2)) {
+ u8 ea[6] = { 0 };
@@ -555,11 +549,11 @@ new file mode 100644
index 0000000..b69513a
--- /dev/null
+++ b/board/armadeus/apf28/mx28_bcb.c
-@@ -0,0 +1,554 @@
+@@ -0,0 +1,559 @@
+/*
+ * i.MX28 NANDÂ Boot Control Blocks generator
+ *
-+ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
+ *
+ * Based on code from mxsboot:
+ * Freescale i.MX28 image generator
@@ -758,14 +752,16 @@ index 0000000..b69513a
+static inline uint32_t mx28_nand_mark_byte_offset(nand_info_t *nand)
+{
+ uint32_t ecc_strength;
-+ ecc_strength = mx28_nand_get_ecc_strength(nand->writesize, nand->oobsize);
++ ecc_strength =
++ mx28_nand_get_ecc_strength(nand->writesize, nand->oobsize);
+ return mx28_nand_get_mark_offset(nand->writesize, ecc_strength) >> 3;
+}
+
+static inline uint32_t mx28_nand_mark_bit_offset(nand_info_t *nand)
+{
+ uint32_t ecc_strength;
-+ ecc_strength = mx28_nand_get_ecc_strength(nand->writesize, nand->oobsize);
++ ecc_strength =
++ mx28_nand_get_ecc_strength(nand->writesize, nand->oobsize);
+ return mx28_nand_get_mark_offset(nand->writesize, ecc_strength) & 0x7;
+}
+
@@ -908,7 +904,8 @@ index 0000000..b69513a
+ return parity;
+}
+
-+static uint8_t *mx28_nand_fcb_block(nand_info_t *nand, struct mx28_nand_fcb *fcb)
++static uint8_t *mx28_nand_fcb_block
++ (nand_info_t *nand, struct mx28_nand_fcb *fcb)
+{
+ uint8_t *block;
+ uint8_t *ecc;
@@ -971,7 +968,8 @@ index 0000000..b69513a
+
+ printf("Writing FCB...\n");
+
-+ for (i = 0; i < stride_pages * stride_count; i += stride_pages) {
++ for (i = 0; i < stride_pages * stride_count;
++ i += stride_pages) {
+ offset = i * nand->writesize;
+ ret = nand->write_oob(nand, offset, &ops);
+ }
@@ -1026,14 +1024,16 @@ index 0000000..b69513a
+ nand_info_t *nand = &nand_info[0];
+ struct mx28_ocotp_regs *ocotp_regs =
+ (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
-+ char buf [12];
++ char buf[12];
+
+ stride_pages = ((readl(&ocotp_regs->hw_ocotp_rom1) >> 4) & 0x0f) * 64;
-+ if (stride_pages < 64) stride_pages = 64;
-+
++ if (stride_pages < 64)
++ stride_pages = 64;
++
+ stride_count = 1 << ((readl(&ocotp_regs->hw_ocotp_rom1) >> 8) & 0x0f);
-+ if (stride_count < 2) stride_count = 4;
-+
++ if (stride_count < 2)
++ stride_count = 4;
++
+ if (firmware_max_size <= nand->erasesize)
+ firmware_max_size = 1 * 1024 * 1024;
+
@@ -1066,9 +1066,11 @@ index 0000000..b69513a
+ goto err2;
+ }
+
-+ sprintf(buf, "0x%08x", fcb->firmware1_starting_sector * nand->writesize);
++ sprintf(buf, "0x%08x",
++ fcb->firmware1_starting_sector * nand->writesize);
+ setenv("u-boot_addr", buf);
-+ sprintf(buf, "0x%08x", fcb->firmware2_starting_sector * nand->writesize);
++ sprintf(buf, "0x%08x",
++ fcb->firmware2_starting_sector * nand->writesize);
+ setenv("u-boot2_addr", buf);
+
+ printf("NAND BCB tables updated\n");
@@ -1091,13 +1093,11 @@ index 0000000..b69513a
+ goto usage;
+
+ if (strcmp(argv[1], "nand.write") == 0) {
-+ if (argc == 3) {
++ if (argc == 3)
+ arg = simple_strtoul(argv[2], NULL, 16);
-+ }
+ err = mx28_update_nand_bcb(arg);
-+ } else {
++ } else
+ goto usage;
-+ }
+
+ return err;
+usage:
@@ -1119,7 +1119,7 @@ index 0000000..3769d44
+/*
+ * Freescale i.MX28 Boot setup for the APF28 board
+ *
-+ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2012 Eric Jarrige <eri...@ar...>
+ * Copyright (C) 2011 Marek Vasut <mar...@gm...>
+ * on behalf of DENX Software Engineering GmbH
+ *
@@ -1318,7 +1318,7 @@ index 0000000..3769d44
+ A logic reset is more appropriate */
+ setbits_le32(&clkctrl_regs->hw_clkctrl_reset,
+ CLKCTRL_RESET_WDOG_POR_DISABLE);
-+
++
+ mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+}
+
hooks/post-receive
--
armadeus
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