[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-362-g75ea404
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-362-g75ea404
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From: jorasse <jo...@us...> - 2012-06-11 19:11:37
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 75ea404046b43a99632421ddd02ed1ce232b8c18 (commit)
from 9f7dc4ae66b9db2601bfb53190a2bd7b4a911489 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 75ea404046b43a99632421ddd02ed1ce232b8c18
Author: Philippe Reynes <tr...@ya...>
Date: Mon Jun 11 21:12:24 2012 +0200
[UBOOT] 2012.04: refactor apf27 patchwork - Thx Trem
-----------------------------------------------------------------------
Summary of changes:
...dule-and-I-O-Multiplexer-constant-for-mx2.patch | 110 +-
...-Add-support-for-the-armadeus-apf27-board.patch | 1383 +++-----------------
.../303-Add-nand-spl-support-on-apf27.patch | 753 +++++++++++
.../2012.04/304-Add-FPGA-support-apf27.patch | 386 ++++++
.../u-boot/2012.04/311-imx-nand-lock-unlock.patch | 2 +
patches/u-boot/2012.04/320-spartan.patch | 2 +
patches/u-boot/2012.04/321-add_spartan6.patch | 2 +
patches/u-boot/2012.04/330-arm926-relocation.patch | 1 -
.../u-boot/2012.04/340-apf27-misc-commands.patch | 6 +-
.../2012.04/350-nand_large_file_download.patch | 2 +
10 files changed, 1379 insertions(+), 1268 deletions(-)
create mode 100644 patches/u-boot/2012.04/303-Add-nand-spl-support-on-apf27.patch
create mode 100644 patches/u-boot/2012.04/304-Add-FPGA-support-apf27.patch
diff --git a/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch b/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
index c05dfce..39fe89f 100644
--- a/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
+++ b/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
@@ -1,16 +1,16 @@
-Add WEIM, NFC SYSTEM_CTLconstants to the mx27 CPU
+Add WEIM, NFC SYSTEM_CTL constants to the mx27 CPU
Signed-off-by: Philippe Reynes <tr...@ya...>
Signed-off-by: Eric Jarrige <eri...@ar...>
---
- arch/arm/cpu/arm926ejs/mx27/asm-offsets.c | 28 +++++++++++
- arch/arm/include/asm/arch-mx27/imx-regs.h | 9 ++++
- arch/arm/include/asm/arch-mx27/mxc_nand.h | 73 +++++++++++++++++++++++++++++
- 3 files changed, 110 insertions(+), 0 deletions(-)
+ arch/arm/cpu/arm926ejs/mx27/asm-offsets.c | 34 ++++++++++++
+ arch/arm/include/asm/arch-mx27/imx-regs.h | 11 ++++-
+ arch/arm/include/asm/arch-mx27/mxc_nand.h | 83 +++++++++++++++++++++++++++++
+ 3 files changed, 127 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h
diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
-index f3a8d7b..7dad00f 100644
+index f3a8d7b..b95c58c 100644
--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
@@ -34,6 +34,7 @@ int main(void)
@@ -21,16 +21,22 @@ index f3a8d7b..7dad00f 100644
DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
-@@ -41,5 +42,32 @@ int main(void)
+@@ -41,5 +42,38 @@ int main(void)
DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
-+ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, gpcr));
-+ DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, fmcr));
-+ DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr2));
-+ DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr3));
-+ DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr7));
-+ DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr10));
++ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
++ offsetof(struct system_control_regs, gpcr));
++ DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
++ offsetof(struct system_control_regs, fmcr));
++ DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE +
++ offsetof(struct system_control_regs, dscr2));
++ DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE +
++ offsetof(struct system_control_regs, dscr3));
++ DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE +
++ offsetof(struct system_control_regs, dscr7));
++ DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE +
++ offsetof(struct system_control_regs, dscr10));
+
+ DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u));
+ DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l));
@@ -55,7 +61,7 @@ index f3a8d7b..7dad00f 100644
return 0;
}
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
-index ced5b2a..4df67d6 100644
+index ced5b2a..fe2861e 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -206,7 +206,7 @@ struct iim_regs {
@@ -83,10 +89,10 @@ index ced5b2a..4df67d6 100644
#endif /* _IMX_REGS_H */
diff --git a/arch/arm/include/asm/arch-mx27/mxc_nand.h b/arch/arm/include/asm/arch-mx27/mxc_nand.h
new file mode 100644
-index 0000000..99af18b
+index 0000000..3429601
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx27/mxc_nand.h
-@@ -0,0 +1,73 @@
+@@ -0,0 +1,83 @@
+/*
+ * (c) 2012 Philippe Reynes <tr...@ya...>
+ *
@@ -116,48 +122,58 @@ index 0000000..99af18b
+ * NFC registers address offest
+ */
+#define NFC_OFFSET_BUFSIZE (0x00) /* Internal SRAM Size */
-+#define NFC_OFFSET_BLCK_ADD_LOCK (0x02) /* NAND Flash Block Address for Lock Check */
-+#define NFC_OFFSET_BUF_ADDR (0x04) /* Buffer Number for Page Data Transfer To/
-+ From Flash Memory */
++#define NFC_OFFSET_BLCK_ADD_LOCK (0x02) /* NAND Flash Block Address for
++ Lock Check */
++#define NFC_OFFSET_BUF_ADDR (0x04) /* Buffer Number for Page Data
++ Transfer To/From Flash Mem */
+#define NFC_OFFSET_FLASH_ADDR (0x06) /* NAND Flash Address */
+#define NFC_OFFSET_FLASH_CMD (0x08) /* NAND Flash Command */
-+#define NFC_OFFSET_CONFIG (0x0A) /* NFC Internal Buffer Lock Control */
-+#define NFC_OFFSET_ECC_STATUS_RESULT (0x0C) /* Controller Status/Result of Flash Operation */
-+#define NFC_OFFSET_ECC_RSLT_MAIN_AREA (0x0E) /* ECC Error Position of Main Area Data Error */
-+#define NFC_OFFSET_ECC_RSLT_SPARE_AREA (0x10) /* ECC Error Position of Spare Area Data Error */
++#define NFC_OFFSET_CONFIG (0x0A) /* NFC Internal Buffer Lock
++ Control */
++#define NFC_OFFSET_ECC_STATUS_RESULT (0x0C) /* Controller Status/Result of
++ Flash Operation */
++#define NFC_OFFSET_ECC_RSLT_MAIN_AREA (0x0E) /* ECC Error Position of Main
++ Area Data Error */
++#define NFC_OFFSET_ECC_RSLT_SPARE_AREA (0x10) /* ECC Error Position of Spare
++ Area Data Error */
+#define NFC_OFFSET_WRPROT (0x12) /* Nand Flash Write Protection */
-+#define NFC_OFFSET_UNLOCKSTART_BLKADDR (0x14) /* Start Address for Write Protection Unlock */
-+#define NFC_OFFSET_UNLOCKEND_BLKADDR (0x16) /* End Address for Write Protection Unlock */
-+#define NFC_OFFSET_WRPR_STAT (0x18) /* Current Nand Flash Write Protection Status */
-+#define NFC_OFFSET_CONFIG1 (0x1A) /* Nand Flash Operation Configuration 1 */
-+#define NFC_OFFSET_CONFIG2 (0x1C) /* Nand Flash Operation Configuration 2 */
++#define NFC_OFFSET_UNLOCKSTART_BLKADDR (0x14) /* Start Address for Write
++ Protection Unlock */
++#define NFC_OFFSET_UNLOCKEND_BLKADDR (0x16) /* End Address for Write
++ Protection Unlock */
++#define NFC_OFFSET_WRPR_STAT (0x18) /* Current Nand Flash Write
++ Protection Status */
++#define NFC_OFFSET_CONFIG1 (0x1A) /* Nand Flash Operation
++ Configuration 1 */
++#define NFC_OFFSET_CONFIG2 (0x1C) /* Nand Flash Operation
++ Configuration 2 */
+
+/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */
-+#define NFC_ECC_STAT_ERM_SHFT (2) /* ERM shift */
-+#define NFC_ECC_STAT_ERS_MASK (0x03) /* ERS mask */
-+#define NFC_ECC_STAT_ERROR1 (1<<0) /* correctable error */
-+#define NFC_ECC_STAT_ERROR2 (1<<1) /* non correctable error */
++#define NFC_ECC_STAT_ERM_SHFT (2) /* ERM shift */
++#define NFC_ECC_STAT_ERS_MASK (0x03) /* ERS mask */
++#define NFC_ECC_STAT_ERROR1 (1<<0) /* correctable error */
++#define NFC_ECC_STAT_ERROR2 (1<<1) /* non correctable error */
+
+/* NFC_CONFIG Control Register Bit Fields */
-+#define NFC_CONFIG_UNLOCKED (1<<1) /* unlocked */
-+#define NFC_CONFIG_LOCKED (1<<0) /* locked */
++#define NFC_CONFIG_UNLOCKED (1<<1) /* unlocked */
++#define NFC_CONFIG_LOCKED (1<<0) /* locked */
+
+/* NFC_CONFIG1 Control Register Bit Fields */
-+#define NFC_CONFIG1_CEn (1<<7) /* Flash force CE */
-+#define NFC_CONFIG1_RST (1<<6) /* Reset */
-+#define NFC_CONFIG1_BIG (1<<5) /* Big Endian Mode */
-+#define NFC_CONFIG1_INT_MSK (1<<4) /* Mask Interrupt Bit */
-+#define NFC_CONFIG1_ECC_EN (1<<3) /* ECC operation enable */
-+#define NFC_CONFIG1_SP_EN (1<<2) /* Flash spare enable */
++#define NFC_CONFIG1_CEn (1<<7) /* Flash force CE */
++#define NFC_CONFIG1_RST (1<<6) /* Reset */
++#define NFC_CONFIG1_BIG (1<<5) /* Big Endian Mode */
++#define NFC_CONFIG1_INT_MSK (1<<4) /* Mask Interrupt Bit */
++#define NFC_CONFIG1_ECC_EN (1<<3) /* ECC operation enable */
++#define NFC_CONFIG1_SP_EN (1<<2) /* Flash spare enable */
+
+/* NFC_CONFIG2 Control Register Bit Fields */
-+#define NFC_CONFIG2_INT (1<<15) /* Interrupt */
-+#define NFC_CONFIG2_FDO_STATUS (4<<3) /* Flash status output */
-+#define NFC_CONFIG2_FDO_ID (2<<3) /* Flash ID output */
-+#define NFC_CONFIG2_FDO_PAGE (1<<3) /* Flash data output */
-+#define NFC_CONFIG2_FDI (1<<2) /* Flash data input */
-+#define NFC_CONFIG2_FADD (1<<1) /* Flash address input */
-+#define NFC_CONFIG2_FCMD (1<<0) /* Flash command input */
++#define NFC_CONFIG2_INT (1<<15) /* Interrupt */
++#define NFC_CONFIG2_FDO_STATUS (4<<3) /* Flash status output */
++#define NFC_CONFIG2_FDO_ID (2<<3) /* Flash ID output */
++#define NFC_CONFIG2_FDO_PAGE (1<<3) /* Flash data output */
++#define NFC_CONFIG2_FDI (1<<2) /* Flash data input */
++#define NFC_CONFIG2_FADD (1<<1) /* Flash address input */
++#define NFC_CONFIG2_FCMD (1<<0) /* Flash command input */
+
+#endif
--
diff --git a/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
index 76ed5d0..acc36d1 100644
--- a/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -4,38 +4,28 @@ Signed-off-by: Philippe Reynes <tr...@ya...>
Signed-off-by: Eric Jarrige <eri...@ar...>
Signed-off-by: Nicolas Colombain <nic...@ar...>
---
- board/armadeus/apf27/Makefile | 50 +++
- board/armadeus/apf27/apf27.c | 305 +++++++++++++++++
- board/armadeus/apf27/config.mk | 13 +
- board/armadeus/apf27/fpga.c | 269 +++++++++++++++
- board/armadeus/apf27/fpga.h | 39 +++
- board/armadeus/apf27/lowlevel_init.S | 277 +++++++++++++++
- boards.cfg | 1 +
- nand_spl/board/armadeus/apf27/Makefile | 77 +++++
- nand_spl/board/armadeus/apf27/config.mk | 43 +++
- nand_spl/board/armadeus/apf27/start.S | 552 ++++++++++++++++++++++++++++++
- nand_spl/board/armadeus/apf27/u-boot.lds | 37 ++
- 11 files changed, 1663 insertions(+), 0 deletions(-)
+ board/armadeus/apf27/Makefile | 52 ++++++
+ board/armadeus/apf27/apf27.c | 310 ++++++++++++++++++++++++++++++++++
+ board/armadeus/apf27/config.mk | 38 ++++
+ board/armadeus/apf27/lowlevel_init.S | 275 ++++++++++++++++++++++++++++++
+ boards.cfg | 1 +
+ 5 files changed, 676 insertions(+), 0 deletions(-)
create mode 100644 board/armadeus/apf27/Makefile
create mode 100644 board/armadeus/apf27/apf27.c
create mode 100644 board/armadeus/apf27/config.mk
- create mode 100644 board/armadeus/apf27/fpga.c
- create mode 100644 board/armadeus/apf27/fpga.h
create mode 100644 board/armadeus/apf27/lowlevel_init.S
- create mode 100644 nand_spl/board/armadeus/apf27/Makefile
- create mode 100644 nand_spl/board/armadeus/apf27/config.mk
- create mode 100644 nand_spl/board/armadeus/apf27/start.S
- create mode 100644 nand_spl/board/armadeus/apf27/u-boot.lds
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
new file mode 100644
-index 0000000..b67334c
+index 0000000..fe6ba5c
--- /dev/null
+++ b/board/armadeus/apf27/Makefile
-@@ -0,0 +1,50 @@
+@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd...@de....
++# (C) Copyright 2012
++# Eric Jarrige <eri...@ar...>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
@@ -60,7 +50,7 @@ index 0000000..b67334c
+
+LIB = $(obj)lib$(BOARD).o
+
-+COBJS := apf27.o fpga.o
++COBJS := apf27.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
@@ -85,13 +75,13 @@ index 0000000..b67334c
+#########################################################################
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
new file mode 100644
-index 0000000..1f1bd42
+index 0000000..c55da1a
--- /dev/null
+++ b/board/armadeus/apf27/apf27.c
-@@ -0,0 +1,325 @@
+@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
-+ * Copyright (C) 2008,2009 Eric Jarrige <jo...@us...>
++ * Copyright (C) 2008-2012 Eric Jarrige <eri...@ar...>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
@@ -112,7 +102,6 @@ index 0000000..1f1bd42
+
+#include <common.h>
+#include "crc.h"
-+#include "fpga.h"
+#include <jffs2/jffs2.h>
+#include <nand.h>
+#include <netdev.h>
@@ -144,103 +133,103 @@ index 0000000..1f1bd42
+
+static void apf27_gpio_init(void)
+{
-+ struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
-+
-+ /* PORT A */
-+ writel(CONFIG_SYS_DR_A_VAL, ®s->port[PORTA].dr);
-+ writel(CONFIG_SYS_OCR1_A_VAL, ®s->port[PORTA].ocr1);
-+ writel(CONFIG_SYS_OCR2_A_VAL, ®s->port[PORTA].ocr2);
-+ writel(CONFIG_SYS_ICFA1_A_VAL, ®s->port[PORTA].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_A_VAL, ®s->port[PORTA].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_A_VAL, ®s->port[PORTA].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_A_VAL, ®s->port[PORTA].iconfb2);
-+ writel(CONFIG_SYS_ICR1_A_VAL, ®s->port[PORTA].icr1);
-+ writel(CONFIG_SYS_ICR2_A_VAL, ®s->port[PORTA].icr2);
-+ writel(CONFIG_SYS_IMR_A_VAL, ®s->port[PORTA].imr);
-+ writel(CONFIG_SYS_DDIR_A_VAL, ®s->port[PORTA].ddir);
-+ writel(CONFIG_SYS_GPR_A_VAL, ®s->port[PORTA].gpr);
-+ writel(CONFIG_SYS_PUEN_A_VAL, ®s->port[PORTA].puen);
-+ writel(CONFIG_SYS_GIUS_A_VAL, ®s->port[PORTA].gius);
-+
-+ /* PORT B */
-+ writel(CONFIG_SYS_DR_B_VAL, ®s->port[PORTB].dr);
-+ writel(CONFIG_SYS_OCR1_B_VAL, ®s->port[PORTB].ocr1);
-+ writel(CONFIG_SYS_OCR2_B_VAL, ®s->port[PORTB].ocr2);
-+ writel(CONFIG_SYS_ICFA1_B_VAL, ®s->port[PORTB].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_B_VAL, ®s->port[PORTB].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_B_VAL, ®s->port[PORTB].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_B_VAL, ®s->port[PORTB].iconfb2);
-+ writel(CONFIG_SYS_ICR1_B_VAL, ®s->port[PORTB].icr1);
-+ writel(CONFIG_SYS_ICR2_B_VAL, ®s->port[PORTB].icr2);
-+ writel(CONFIG_SYS_IMR_B_VAL, ®s->port[PORTB].imr);
-+ writel(CONFIG_SYS_DDIR_B_VAL, ®s->port[PORTB].ddir);
-+ writel(CONFIG_SYS_GPR_B_VAL, ®s->port[PORTB].gpr);
-+ writel(CONFIG_SYS_PUEN_B_VAL, ®s->port[PORTB].puen);
-+ writel(CONFIG_SYS_GIUS_B_VAL, ®s->port[PORTB].gius);
-+
-+ /* PORT C */
-+ writel(CONFIG_SYS_DR_C_VAL, ®s->port[PORTC].dr);
-+ writel(CONFIG_SYS_OCR1_C_VAL, ®s->port[PORTC].ocr1);
-+ writel(CONFIG_SYS_OCR2_C_VAL, ®s->port[PORTC].ocr2);
-+ writel(CONFIG_SYS_ICFA1_C_VAL, ®s->port[PORTC].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_C_VAL, ®s->port[PORTC].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_C_VAL, ®s->port[PORTC].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_C_VAL, ®s->port[PORTC].iconfb2);
-+ writel(CONFIG_SYS_ICR1_C_VAL, ®s->port[PORTC].icr1);
-+ writel(CONFIG_SYS_ICR2_C_VAL, ®s->port[PORTC].icr2);
-+ writel(CONFIG_SYS_IMR_C_VAL, ®s->port[PORTC].imr);
-+ writel(CONFIG_SYS_DDIR_C_VAL, ®s->port[PORTC].ddir);
-+ writel(CONFIG_SYS_GPR_C_VAL, ®s->port[PORTC].gpr);
-+ writel(CONFIG_SYS_PUEN_C_VAL, ®s->port[PORTC].puen);
-+ writel(CONFIG_SYS_GIUS_C_VAL, ®s->port[PORTC].gius);
-+
-+ /* PORT D */
-+ writel(CONFIG_SYS_DR_D_VAL, ®s->port[PORTD].dr);
-+ writel(CONFIG_SYS_OCR1_D_VAL, ®s->port[PORTD].ocr1);
-+ writel(CONFIG_SYS_OCR2_D_VAL, ®s->port[PORTD].ocr2);
-+ writel(CONFIG_SYS_ICFA1_D_VAL, ®s->port[PORTD].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_D_VAL, ®s->port[PORTD].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_D_VAL, ®s->port[PORTD].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_D_VAL, ®s->port[PORTD].iconfb2);
-+ writel(CONFIG_SYS_ICR1_D_VAL, ®s->port[PORTD].icr1);
-+ writel(CONFIG_SYS_ICR2_D_VAL, ®s->port[PORTD].icr2);
-+ writel(CONFIG_SYS_IMR_D_VAL, ®s->port[PORTD].imr);
-+ writel(CONFIG_SYS_DDIR_D_VAL, ®s->port[PORTD].ddir);
-+ writel(CONFIG_SYS_GPR_D_VAL, ®s->port[PORTD].gpr);
-+ writel(CONFIG_SYS_PUEN_D_VAL, ®s->port[PORTD].puen);
-+ writel(CONFIG_SYS_GIUS_D_VAL, ®s->port[PORTD].gius);
-+
-+ /* PORT E */
-+ writel(CONFIG_SYS_DR_E_VAL, ®s->port[PORTE].dr);
-+ writel(CONFIG_SYS_OCR1_E_VAL, ®s->port[PORTE].ocr1);
-+ writel(CONFIG_SYS_OCR2_E_VAL, ®s->port[PORTE].ocr2);
-+ writel(CONFIG_SYS_ICFA1_E_VAL, ®s->port[PORTE].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_E_VAL, ®s->port[PORTE].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_E_VAL, ®s->port[PORTE].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_E_VAL, ®s->port[PORTE].iconfb2);
-+ writel(CONFIG_SYS_ICR1_E_VAL, ®s->port[PORTE].icr1);
-+ writel(CONFIG_SYS_ICR2_E_VAL, ®s->port[PORTE].icr2);
-+ writel(CONFIG_SYS_IMR_E_VAL, ®s->port[PORTE].imr);
-+ writel(CONFIG_SYS_DDIR_E_VAL, ®s->port[PORTE].ddir);
-+ writel(CONFIG_SYS_GPR_E_VAL, ®s->port[PORTE].gpr);
-+ writel(CONFIG_SYS_PUEN_E_VAL, ®s->port[PORTE].puen);
-+ writel(CONFIG_SYS_GIUS_E_VAL, ®s->port[PORTE].gius);
-+
-+ /* PORT F */
-+ writel(CONFIG_SYS_DR_F_VAL, ®s->port[PORTF].dr);
-+ writel(CONFIG_SYS_OCR1_F_VAL, ®s->port[PORTF].ocr1);
-+ writel(CONFIG_SYS_OCR2_F_VAL, ®s->port[PORTF].ocr2);
-+ writel(CONFIG_SYS_ICFA1_F_VAL, ®s->port[PORTF].iconfa1);
-+ writel(CONFIG_SYS_ICFA2_F_VAL, ®s->port[PORTF].iconfa2);
-+ writel(CONFIG_SYS_ICFB1_F_VAL, ®s->port[PORTF].iconfb1);
-+ writel(CONFIG_SYS_ICFB2_F_VAL, ®s->port[PORTF].iconfb2);
-+ writel(CONFIG_SYS_ICR1_F_VAL, ®s->port[PORTF].icr1);
-+ writel(CONFIG_SYS_ICR2_F_VAL, ®s->port[PORTF].icr2);
-+ writel(CONFIG_SYS_IMR_F_VAL, ®s->port[PORTF].imr);
-+ writel(CONFIG_SYS_DDIR_F_VAL, ®s->port[PORTF].ddir);
-+ writel(CONFIG_SYS_GPR_F_VAL, ®s->port[PORTF].gpr);
-+ writel(CONFIG_SYS_PUEN_F_VAL, ®s->port[PORTF].puen);
-+ writel(CONFIG_SYS_GIUS_F_VAL, ®s->port[PORTF].gius);
++ struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
++
++ /* PORT A */
++ writel(CONFIG_SYS_DR_A_VAL, ®s->port[PORTA].dr);
++ writel(CONFIG_SYS_OCR1_A_VAL, ®s->port[PORTA].ocr1);
++ writel(CONFIG_SYS_OCR2_A_VAL, ®s->port[PORTA].ocr2);
++ writel(CONFIG_SYS_ICFA1_A_VAL, ®s->port[PORTA].iconfa1);
++ writel(CONFIG_SYS_ICFA2_A_VAL, ®s->port[PORTA].iconfa2);
++ writel(CONFIG_SYS_ICFB1_A_VAL, ®s->port[PORTA].iconfb1);
++ writel(CONFIG_SYS_ICFB2_A_VAL, ®s->port[PORTA].iconfb2);
++ writel(CONFIG_SYS_ICR1_A_VAL, ®s->port[PORTA].icr1);
++ writel(CONFIG_SYS_ICR2_A_VAL, ®s->port[PORTA].icr2);
++ writel(CONFIG_SYS_IMR_A_VAL, ®s->port[PORTA].imr);
++ writel(CONFIG_SYS_DDIR_A_VAL, ®s->port[PORTA].ddir);
++ writel(CONFIG_SYS_GPR_A_VAL, ®s->port[PORTA].gpr);
++ writel(CONFIG_SYS_PUEN_A_VAL, ®s->port[PORTA].puen);
++ writel(CONFIG_SYS_GIUS_A_VAL, ®s->port[PORTA].gius);
++
++ /* PORT B */
++ writel(CONFIG_SYS_DR_B_VAL, ®s->port[PORTB].dr);
++ writel(CONFIG_SYS_OCR1_B_VAL, ®s->port[PORTB].ocr1);
++ writel(CONFIG_SYS_OCR2_B_VAL, ®s->port[PORTB].ocr2);
++ writel(CONFIG_SYS_ICFA1_B_VAL, ®s->port[PORTB].iconfa1);
++ writel(CONFIG_SYS_ICFA2_B_VAL, ®s->port[PORTB].iconfa2);
++ writel(CONFIG_SYS_ICFB1_B_VAL, ®s->port[PORTB].iconfb1);
++ writel(CONFIG_SYS_ICFB2_B_VAL, ®s->port[PORTB].iconfb2);
++ writel(CONFIG_SYS_ICR1_B_VAL, ®s->port[PORTB].icr1);
++ writel(CONFIG_SYS_ICR2_B_VAL, ®s->port[PORTB].icr2);
++ writel(CONFIG_SYS_IMR_B_VAL, ®s->port[PORTB].imr);
++ writel(CONFIG_SYS_DDIR_B_VAL, ®s->port[PORTB].ddir);
++ writel(CONFIG_SYS_GPR_B_VAL, ®s->port[PORTB].gpr);
++ writel(CONFIG_SYS_PUEN_B_VAL, ®s->port[PORTB].puen);
++ writel(CONFIG_SYS_GIUS_B_VAL, ®s->port[PORTB].gius);
++
++ /* PORT C */
++ writel(CONFIG_SYS_DR_C_VAL, ®s->port[PORTC].dr);
++ writel(CONFIG_SYS_OCR1_C_VAL, ®s->port[PORTC].ocr1);
++ writel(CONFIG_SYS_OCR2_C_VAL, ®s->port[PORTC].ocr2);
++ writel(CONFIG_SYS_ICFA1_C_VAL, ®s->port[PORTC].iconfa1);
++ writel(CONFIG_SYS_ICFA2_C_VAL, ®s->port[PORTC].iconfa2);
++ writel(CONFIG_SYS_ICFB1_C_VAL, ®s->port[PORTC].iconfb1);
++ writel(CONFIG_SYS_ICFB2_C_VAL, ®s->port[PORTC].iconfb2);
++ writel(CONFIG_SYS_ICR1_C_VAL, ®s->port[PORTC].icr1);
++ writel(CONFIG_SYS_ICR2_C_VAL, ®s->port[PORTC].icr2);
++ writel(CONFIG_SYS_IMR_C_VAL, ®s->port[PORTC].imr);
++ writel(CONFIG_SYS_DDIR_C_VAL, ®s->port[PORTC].ddir);
++ writel(CONFIG_SYS_GPR_C_VAL, ®s->port[PORTC].gpr);
++ writel(CONFIG_SYS_PUEN_C_VAL, ®s->port[PORTC].puen);
++ writel(CONFIG_SYS_GIUS_C_VAL, ®s->port[PORTC].gius);
++
++ /* PORT D */
++ writel(CONFIG_SYS_DR_D_VAL, ®s->port[PORTD].dr);
++ writel(CONFIG_SYS_OCR1_D_VAL, ®s->port[PORTD].ocr1);
++ writel(CONFIG_SYS_OCR2_D_VAL, ®s->port[PORTD].ocr2);
++ writel(CONFIG_SYS_ICFA1_D_VAL, ®s->port[PORTD].iconfa1);
++ writel(CONFIG_SYS_ICFA2_D_VAL, ®s->port[PORTD].iconfa2);
++ writel(CONFIG_SYS_ICFB1_D_VAL, ®s->port[PORTD].iconfb1);
++ writel(CONFIG_SYS_ICFB2_D_VAL, ®s->port[PORTD].iconfb2);
++ writel(CONFIG_SYS_ICR1_D_VAL, ®s->port[PORTD].icr1);
++ writel(CONFIG_SYS_ICR2_D_VAL, ®s->port[PORTD].icr2);
++ writel(CONFIG_SYS_IMR_D_VAL, ®s->port[PORTD].imr);
++ writel(CONFIG_SYS_DDIR_D_VAL, ®s->port[PORTD].ddir);
++ writel(CONFIG_SYS_GPR_D_VAL, ®s->port[PORTD].gpr);
++ writel(CONFIG_SYS_PUEN_D_VAL, ®s->port[PORTD].puen);
++ writel(CONFIG_SYS_GIUS_D_VAL, ®s->port[PORTD].gius);
++
++ /* PORT E */
++ writel(CONFIG_SYS_DR_E_VAL, ®s->port[PORTE].dr);
++ writel(CONFIG_SYS_OCR1_E_VAL, ®s->port[PORTE].ocr1);
++ writel(CONFIG_SYS_OCR2_E_VAL, ®s->port[PORTE].ocr2);
++ writel(CONFIG_SYS_ICFA1_E_VAL, ®s->port[PORTE].iconfa1);
++ writel(CONFIG_SYS_ICFA2_E_VAL, ®s->port[PORTE].iconfa2);
++ writel(CONFIG_SYS_ICFB1_E_VAL, ®s->port[PORTE].iconfb1);
++ writel(CONFIG_SYS_ICFB2_E_VAL, ®s->port[PORTE].iconfb2);
++ writel(CONFIG_SYS_ICR1_E_VAL, ®s->port[PORTE].icr1);
++ writel(CONFIG_SYS_ICR2_E_VAL, ®s->port[PORTE].icr2);
++ writel(CONFIG_SYS_IMR_E_VAL, ®s->port[PORTE].imr);
++ writel(CONFIG_SYS_DDIR_E_VAL, ®s->port[PORTE].ddir);
++ writel(CONFIG_SYS_GPR_E_VAL, ®s->port[PORTE].gpr);
++ writel(CONFIG_SYS_PUEN_E_VAL, ®s->port[PORTE].puen);
++ writel(CONFIG_SYS_GIUS_E_VAL, ®s->port[PORTE].gius);
++
++ /* PORT F */
++ writel(CONFIG_SYS_DR_F_VAL, ®s->port[PORTF].dr);
++ writel(CONFIG_SYS_OCR1_F_VAL, ®s->port[PORTF].ocr1);
++ writel(CONFIG_SYS_OCR2_F_VAL, ®s->port[PORTF].ocr2);
++ writel(CONFIG_SYS_ICFA1_F_VAL, ®s->port[PORTF].iconfa1);
++ writel(CONFIG_SYS_ICFA2_F_VAL, ®s->port[PORTF].iconfa2);
++ writel(CONFIG_SYS_ICFB1_F_VAL, ®s->port[PORTF].iconfb1);
++ writel(CONFIG_SYS_ICFB2_F_VAL, ®s->port[PORTF].iconfb2);
++ writel(CONFIG_SYS_ICR1_F_VAL, ®s->port[PORTF].icr1);
++ writel(CONFIG_SYS_ICR2_F_VAL, ®s->port[PORTF].icr2);
++ writel(CONFIG_SYS_IMR_F_VAL, ®s->port[PORTF].imr);
++ writel(CONFIG_SYS_DDIR_F_VAL, ®s->port[PORTF].ddir);
++ writel(CONFIG_SYS_GPR_F_VAL, ®s->port[PORTF].gpr);
++ writel(CONFIG_SYS_PUEN_F_VAL, ®s->port[PORTF].puen);
++ writel(CONFIG_SYS_GIUS_F_VAL, ®s->port[PORTF].gius);
+}
+
+static int apf27_devices_init(void)
@@ -283,7 +272,7 @@ index 0000000..1f1bd42
+ return -1;
+}
+int
-+board_init (void)
++board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
@@ -294,13 +283,13 @@ index 0000000..1f1bd42
+}
+
+int
-+dram_init (void)
++dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+ if (get_num_ram_bank() > 1) {
+ gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
-+ PHYS_SDRAM_2_SIZE);
++ PHYS_SDRAM_2_SIZE);
+ }
+
+ return 0;
@@ -312,7 +301,8 @@ index 0000000..1f1bd42
+ gd->bd->bi_dram[0].size = gd->ram_size / get_num_ram_bank();
+ if (CONFIG_NR_DRAM_BANKS > 1) {
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-+ gd->bd->bi_dram[1].size = gd->ram_size -gd->bd->bi_dram[0].size;
++ gd->bd->bi_dram[1].size = \
++ gd->ram_size - gd->bd->bi_dram[0].size;
+ }
+}
+
@@ -320,55 +310,40 @@ index 0000000..1f1bd42
+ * Miscellaneous intialization
+ */
+int
-+misc_init_r (void)
++misc_init_r(void)
+{
+ char *s;
-+ u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
++ u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + \
++ CONFIG_SYS_MONITOR_LEN);
+ size_t size = 0;
+ size_t offset = -1;
-+ char *autoload = getenv ("firmware_autoload");
++ char *autoload = getenv("firmware_autoload");
+ u8 pnum;
+ struct mtd_device *dev;
+ struct part_info *part;
+
-+#if defined(CONFIG_FPGA)
-+ /* init and download fpga */
-+ if (( autoload ) && (0 == strcmp(autoload, "1"))) {
-+ if (mtdparts_init() == 0)
-+ if (find_dev_and_part("firmware", &dev, &pnum, &part) == 0) {
-+ size = part->size;
-+ if (nand_read_skip_bad(&nand_info[0], part->offset,
-+ &size, firmware_buffer))
-+ size = 0;
-+ }
-+ }
-+ APF27_init_fpga (firmware_buffer, size);
-+#endif
-+
+ /* detect compatibility issue of environment version */
-+ s = getenv ("env_version");
-+ if (( NULL == s ) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
++ s = getenv("env_version");
++ if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
+ printf("*** Warning - Environment version change suggests: "
+ "run flash_reset_env; reset\n");
+ }
+
+ /* Unlock whole flash but U-Boot */
-+ s = getenv ("env_offset");
++ s = getenv("env_offset");
+ offset = CONFIG_ENV_OFFSET;
-+ if ((s != NULL) && (0 != strcmp(s, "0"))) {
++ if ((s != NULL) && (0 != strcmp(s, "0")))
+ offset = simple_strtoul(s, NULL, 16);
-+ }
+
-+ if (nand_unlock(&nand_info[0], offset, nand_info[0].size - offset)) {
++ if (nand_unlock(&nand_info[0], offset, nand_info[0].size - offset))
+ printf("NAND flash lock/unlocked failed\n");
-+ }
+
+
+ return 0;
+}
+
+void
-+show_boot_progress (int status)
++show_boot_progress(int status)
+{
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+#endif
@@ -381,7 +356,7 @@ index 0000000..1f1bd42
+ return 0;
+}
+
-+int board_eth_init(bd_t * bis)
++int board_eth_init(bd_t *bis)
+{
+#define STR_ENV_ETHADDR "ethaddr"
+ int rc = -ENODEV;
@@ -410,16 +385,41 @@ index 0000000..1f1bd42
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
-+ //dcache_enable();
++ /* dcache_enable(); */
+}
+
+#endif
diff --git a/board/armadeus/apf27/config.mk b/board/armadeus/apf27/config.mk
new file mode 100644
-index 0000000..3354ba0
+index 0000000..9713e69
--- /dev/null
+++ b/board/armadeus/apf27/config.mk
-@@ -0,0 +1,13 @@
+@@ -0,0 +1,38 @@
++#
++# (C) Copyright 2003
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++# (C) Copyright 2012
++# Eric Jarrige <eri...@ar...>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
+#
+# This config file is used for compilation of armadeus sources
+#
@@ -432,330 +432,10 @@ index 0000000..3354ba0
+ifndef TEXT_BASE
+TEXT_BASE = 0xAFF00000
+endif
-+# CONFIG_NAND_U_BOOT = y
-diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
-new file mode 100644
-index 0000000..1d2c168
---- /dev/null
-+++ b/board/armadeus/apf27/fpga.c
-@@ -0,0 +1,269 @@
-+/*
-+ * (C) Copyright 2002-2008
-+ * Eric Jarrige <eri...@ar...>
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+#include <common.h>
-+
-+#if defined(CONFIG_FPGA)
-+
-+#include <asm/arch/imx-regs.h>
-+#include <asm/io.h>
-+#include <command.h>
-+#include <config.h>
-+#include "fpga.h"
-+#include <spartan3.h>
-+
-+#define GPIO_PORT(x) ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT)
-+#define GPIO_SET(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | (1 << (x & GPIO_PIN_MASK)), \
-+ &gpregs->port[GPIO_PORT(x)].dr)
-+//(DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_CLEAR(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) & ~(1 << (x & GPIO_PIN_MASK)), \
-+ &gpregs->port[GPIO_PORT(x)].dr)
-+//(DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
-+#define GPIO_READ(x) ((readl(&gpregs->port[GPIO_PORT(x)].ssr) & (1 << (x & GPIO_PIN_MASK))) \
-+ >> (x & GPIO_PIN_MASK))
-+//((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK)))>> (x & GPIO_PIN_MASK))
-+#ifdef FPGA_DEBUG
-+#define PRINTF(fmt,args...) printf (fmt ,##args)
-+#else
-+#define PRINTF(fmt,args...)
-+#endif
-+
-+/* Note that these are pointers to code that is in Flash. They will be
-+ * relocated at runtime.
-+ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
-+ * Just take care about the file size
-+*/
-+Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
-+ fpga_pre_fn,
-+ fpga_pgm_fn,
-+ fpga_init_fn,
-+ NULL,
-+ fpga_done_fn,
-+ fpga_clk_fn,
-+ fpga_cs_fn,
-+ fpga_wr_fn,
-+ fpga_rdata_fn,
-+ fpga_wdata_fn,
-+ fpga_busy_fn,
-+ fpga_abort_fn,
-+ fpga_post_fn,
-+};
-+
-+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-+ {Xilinx_Spartan3,
-+ slave_parallel,
-+ 1196128l/8,
-+ (void *) &fpga_fns,
-+ 0}
-+};
-+
-+/*
-+ * nitialize GPIO port B before download
-+ */
-+int
-+fpga_pre_fn (int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ // Initialize GPIO pins
-+ GPIO_SET(CONFIG_SYS_FPGA_PWR);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_SUSPEND | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ GPIO_SET(CONFIG_SYS_FPGA_RESET);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ GPIO_SET(CONFIG_SYS_FPGA_PRG);
-+ GPIO_SET(CONFIG_SYS_FPGA_CLK);
-+ GPIO_SET(CONFIG_SYS_FPGA_RW);
-+ GPIO_SET(CONFIG_SYS_FPGA_CS);
-+ GPIO_CLEAR(CONFIG_SYS_FPGA_SUSPEND);
-+// GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
-+ GPIO_CLEAR(CONFIG_SYS_FPGA_PWR);
-+
-+ return cookie;
-+}
-+
-+/*
-+ * Set the FPGA's active-low program line to the specified level
-+ */
-+int
-+fpga_pgm_fn (int assert, int flush, int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA PROGRAM %s", __FUNCTION__, __LINE__,
-+ assert?"high":"low");
-+ GPIO_WRITE( CONFIG_SYS_FPGA_PRG, !assert);
-+ return assert;
-+}
-+
-+/*
-+ * Set the FPGA's active-high clock line to the specified level
-+ */
-+int
-+fpga_clk_fn (int assert_clk, int flush, int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA CLOCK %s", __FUNCTION__, __LINE__,
-+ assert_clk?"high":"low");
-+ GPIO_WRITE( CONFIG_SYS_FPGA_CLK, !assert_clk);
-+ return assert_clk;
-+}
-+
-+/*
-+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
-+ * asserted (low).
-+ */
-+int
-+fpga_init_fn (int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ int value;
-+ PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
-+ value = GPIO_READ(CONFIG_SYS_FPGA_INIT);
-+ //printf("init value read %x",value);
-+#ifdef CONFIG_SYS_FPGA_IS_PROTO
-+ return value;
-+#else
-+ return !value;
-+#endif
-+}
-+
-+/*
-+ * Test the state of the active-high FPGA DONE pin
-+ */
-+int
-+fpga_done_fn (int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
-+ GPIO_READ(CONFIG_SYS_FPGA_DONE)?"high":"low");
-+ return(GPIO_READ(CONFIG_SYS_FPGA_DONE)?FPGA_SUCCESS:FPGA_FAIL);
-+}
-+
-+/*
-+ * Set the FPGA's wr line to the specified level
-+ */
-+int
-+fpga_wr_fn (int assert_write, int flush, int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA RW... %s ", __FUNCTION__, __LINE__,
-+ assert_write?"high":"low");
-+ GPIO_WRITE( CONFIG_SYS_FPGA_RW, !assert_write);
-+ return assert_write;
-+}
-+
-+int
-+fpga_cs_fn (int assert_cs, int flush, int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA CS %s ", __FUNCTION__, __LINE__,
-+ assert_cs?"high":"low");
-+ GPIO_WRITE( CONFIG_SYS_FPGA_CS, !assert_cs);
-+ return assert_cs;
-+}
-+
-+int
-+fpga_rdata_fn ( unsigned char *data, int cookie )
-+{
-+ PRINTF ("%s:%d: FPGA READ DATA %02X ", __FUNCTION__, __LINE__,
-+ *((char*)CONFIG_SYS_FPGA_RDATA));
-+ *data = (unsigned char)((*((unsigned short*)CONFIG_SYS_FPGA_RDATA))&0x00FF);
-+ return *data;
-+}
-+
-+int
-+fpga_wdata_fn ( unsigned char data, int cookie )
-+{
-+ PRINTF ("%s:%d: FPGA WRITE DATA %02X ", __FUNCTION__, __LINE__,
-+ data);
-+ *((unsigned short*)CONFIG_SYS_FPGA_WDATA) = data;
-+ return data;
-+}
-+
-+int
-+fpga_abort_fn ( int cookie )
-+{
-+ return cookie;
-+}
-+
-+
-+int
-+fpga_busy_fn ( int cookie )
-+{
-+ return 1;
-+}
-+
-+int
-+fpga_post_fn (int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA POST ", __FUNCTION__, __LINE__);
-+
-+ imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_PF | GPIO_PUEN);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_PF | GPIO_PUEN);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_PF | GPIO_PUEN);
-+ GPIO_SET(CONFIG_SYS_FPGA_PRG);
-+ GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ return cookie;
-+}
-+
-+/*
-+ * Initialize the fpga. Return 1 on success, 0 on failure.
-+ */
-+int
-+APF27_init_fpga (u_char * buffer, size_t size)
-+{
-+ char *autoload = getenv ("firmware_autoload");
-+
-+ int i,lout=0;
+
-+ fpga_init();
-+
-+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
-+ PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
-+ fpga_add (fpga_xilinx, &fpga[i]);
-+ }
-+
-+ if ((size >= fpga[0].size) && ( autoload ) && (0 == strcmp(autoload, "1"))) {
-+ if (ctrlc()) {
-+ printf("Firmware download stopped!\n");
-+ } else if (FPGA_SUCCESS != fpga_load( 0,(void *)buffer, size )) {
-+ printf("Firmware download failed!\n");
-+ } else {
-+ printf("Firmware successfully programmed\n");
-+ lout = 1;
-+ }
-+ }
-+ return lout;
-+}
-+
-+#endif /* CONFIG_FPGA */
-diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h
-new file mode 100644
-index 0000000..ca569e0
---- /dev/null
-+++ b/board/armadeus/apf27/fpga.h
-@@ -0,0 +1,39 @@
-+/*
-+ * (C) Copyright 2002-2008
-+ * Eric Jarrige <eri...@ar...>
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+extern int APF27_init_fpga (u_char * buffer, size_t size);
-+
-+extern int fpga_pre_fn (int cookie);
-+extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
-+extern int fpga_cs_fn (int assert_cs, int flush, int cookie);
-+extern int fpga_init_fn (int cookie);
-+extern int fpga_done_fn (int cookie);
-+extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
-+extern int fpga_wr_fn (int assert_write, int flush, int cookie);
-+extern int fpga_rdata_fn ( unsigned char *data, int cookie );
-+extern int fpga_wdata_fn ( unsigned char data, int cookie );
-+extern int fpga_abort_fn (int cookie);
-+extern int fpga_post_fn (int cookie);
-+extern int fpga_busy_fn (int cookie);
diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
new file mode 100644
-index 0000000..a6bbbc1
+index 0000000..f5dbbb4
--- /dev/null
+++ b/board/armadeus/apf27/lowlevel_init.S
@@ -0,0 +1,275 @@
@@ -763,7 +443,7 @@ index 0000000..a6bbbc1
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
-+ * (C) Copyright 2008 Eric Jarrige <eri...@ar...>
++ * (C) Copyright 2008-2012 Eric Jarrige <eri...@ar...>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
@@ -784,7 +464,7 @@ index 0000000..a6bbbc1
+
+#include <config.h>
+#include <version.h>
-+#include <asm/macro.h>
++#include <asm/macro.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
@@ -826,7 +506,7 @@ index 0000000..a6bbbc1
+ write32 MPCTL0, CONFIG_SYS_MPCTL0_VAL
+ write32 SPCTL0, CONFIG_SYS_SPCTL0_VAL
+
-+ write32 CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
++ write32 CSCR, CONFIG_SYS_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
+
+ /*
+ * add some delay here
@@ -887,9 +567,9 @@ index 0000000..a6bbbc1
+
+ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
+
-+ ldr r6,=0x7 /* load loop counter */
-+1: str r5,[r4] /* run auto-refresh cycle to array 0 */
-+ subs r6,r6,#1 /* decrease counter value */
++ ldr r6,=0x7 /* load loop counter */
++1: str r5,[r4] /* run auto-refresh cycle to array 0 */
++ subs r6,r6,#1 /* decrease counter value */
+ bne 1b
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
@@ -911,7 +591,7 @@ index 0000000..a6bbbc1
+ /* 2nd sdram */
+ /* write32 ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
+ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
-+ str r1, [r0, #ESDCFG1_ROF]
++ str r1, [r0, #ESDCFG1_ROF]
+
+ /* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
@@ -927,9 +607,9 @@ index 0000000..a6bbbc1
+
+ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
+
-+ ldr r6,=0x7 /* load loop counter */
-+1: str r5,[r4] /* run auto-refresh cycle to array 0 */
-+ subs r6,r6,#1 /* decrease counter value */
++ ldr r6,=0x7 /* load loop counter */
++1: str r5,[r4] /* run auto-refresh cycle to array 0 */
++ subs r6,r6,#1 /* decrease counter value */
+ bne 1b
+
+ /* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
@@ -1046,737 +726,6 @@ index c8bc589..fc8f71c 100644
at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
-diff --git a/nand_spl/board/armadeus/apf27/Makefile b/nand_spl/board/armadeus/apf27/Makefile
-new file mode 100644
-index 0000000..79a250e
---- /dev/null
-+++ b/nand_spl/board/armadeus/apf27/Makefile
-@@ -0,0 +1,77 @@
-+#
-+# (C) Copyright 2007
-+# Stefan Roese, DENX Software Engineering, sr...@de....
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-+
-+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
-+AFLAGS += -DCONFIG_NAND_SPL
-+CFLAGS += -DCONFIG_NAND_SPL
-+
-+SOBJS = start.o
-+COBJS =
-+
-+SRCS := $(addprefix $(src),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-+__OBJS := $(SOBJS) $(COBJS)
-+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
-+
-+nandobj := $(OBJTREE)/nand_spl/
-+
-+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
-+ $(nandobj)System.map
-+
-+all: $(obj).depend $(ALL)
-+
-+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-+
-+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
-+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-+
-+$(nandobj)u-boot-spl: $(OBJS)
-+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-+ -Map $(nandobj)u-boot-spl.map \
-+ -o $(nandobj)u-boot-spl
-+
-+$(nandobj)System.map: $(nandobj)u-boot-spl
-+ @$(NM) $< | \
-+ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
-+ sort > $(nandobj)System.map
-+
-+
-+#########################################################################
-+
-+$(obj)%.o: %.S
-+ $(CC) $(AFLAGS) -c -o $@ $<
-+
-+$(obj)%.o: %.c
-+ $(CC) $(CFLAGS) -c -o $@ $<
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
-diff --git a/nand_spl/board/armadeus/apf27/config.mk b/nand_spl/board/armadeus/apf27/config.mk
-new file mode 100644
-index 0000000..46802e3
---- /dev/null
-+++ b/nand_spl/board/armadeus/apf27/config.mk
-@@ -0,0 +1,43 @@
-+#
-+# (C) Copyright 2007
-+# Stefan Roese, DENX Software Engineering, sr...@de....
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+#
-+# This config file is used for compilation of armadeus apf27 board
-+#
-+
-+#
-+# TEXT_BASE for SPL:
-+#
-+#
-+# This config file is used for compilation of armadeus sources
-+#
-+# You might change location of U-Boot in memory by setting right TEXT_BASE.
-+# This allows for example having one copy located at the end of ram and stored
-+# in flash device and later on while developing use other location to test
-+# the code in RAM device only.
-+#
-+
-+TEXT_BASE = 0xa0000000
-+
-+# PAD_TO used to generate a 2kByte binary needed for the combined image
-+# -> PAD_TO = TEXT_BASE + 0x0800
-+PAD_TO = 0xa0000800
-diff --git a/nand_spl/board/armadeus/apf27/start.S b/nand_spl/board/armadeus/apf27/start.S
-new file mode 100644
-index 0000000..c8f158d
---- /dev/null
-+++ b/nand_spl/board/armadeus/apf27/start.S
-@@ -0,0 +1,550 @@
-+/*
-+ * IMX27 NAND Flash SPL (Secondary Program Loader)
-+ *
-+ * Copyright (c) 2008 Armadeus Project / eja
-+ *
-+ * Based on Freescale NAND SPL
-+ *
-+ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-+ * Copyright (c) 2008 Eric Jarrige <eri...@ar...>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+
-+#include <config.h>
-+#include <version.h>
-+#include <asm/arch/mxc_nand.h>
-+#include <asm/arch/imx-regs.h>
-+#include <generated/asm-offsets.h>
-+
-+/*
-+ * Standard NAND flash commands
-+ */
-+#define NAND_CMD_READ0 0
-+#define NAND_CMD_READ1 1
-+#define NAND_CMD_PAGEPROG 0x10
-+#define NAND_CMD_READOOB 0x50
-+#define NAND_CMD_ERASE1 0x60
-+#define NAND_CMD_STATUS 0x70
-+#define NAND_CMD_STATUS_MULTI 0x71
-+#define NAND_CMD_SEQIN 0x80
-+#define NAND_CMD_READID 0x90
-+#define NAND_CMD_ERASE2 0xd0
-+#define NAND_CMD_RESET 0xff
-+
-+/* Extended commands for large page devices */
-+#define NAND_CMD_READSTART 0x30
-+#define NAND_CMD_CACHEDPROG 0x15
-+
-+/* Status bits */
-+#define NAND_STATUS_FAIL 0x01
-+#define NAND_STATUS_FAIL_N1 0x02
-+#define NAND_STATUS_TRUE_READY 0x20
-+#define NAND_STATUS_READY 0x40
-+#define NAND_STATUS_WP 0x80
-+
-+#define writel(reg, val) \
-+ ldr r0, =reg; \
-+ ldr r1, =val; \
-+ str r1, [r0];
-+
-+ .macro nand_boot
-+
-+#ifdef CONFIG_BOOT_TRACE_REG
-+/*
-+ * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following
-+ * 2 command after SDRAM init
-+ */
-+
-+/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
-+#define BACKUP_TRACE() \
-+ ldr r4, =CONFIG_BOOT_TRACE_REG; \
-+ ldr r3, [r4]; \
-+ str r3, [r4, #0x04];
-+
-+/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
-+#define BOOT_TRACE(val) \
-+ ldr r4, =CONFIG_BOOT_TRACE_REG; \
-+ ldr r3, =val; \
-+ str r3, [r4];
-+#else
-+#define BACKUP_TRACE()
-+#define BOOT_TRACE(val)
-+#endif
-+
-+nand_boot_setup:
-+
-+ /* Copy SPL image from flash to SDRAM first */
-+ BOOT_TRACE(1)
-+ ldr r0, =IMX_NFC_MAIN_AREA0
-+ add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff
-+ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
-+
-+ BOOT_TRACE(2)
-+1: ldmia r0!, {r3-r10}
-+ stmia r1!, {r3-r10}
-+ cmp r0, r2
-+ blo 1b
-+
-+
-+
-+ /* Jump to SDRAM */
-+ BOOT_TRACE(3)
-+ ldr r1, =0xFFF
-+ and r0, pc, r1 /* offset of pc */
-+ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
-+ add r1, r1, #0x10
-+ add pc, r0, r1
-+ nop
-+ nop
-+ nop
-+ nop
-+
-+NAND_Copy_Main:
-+ BOOT_TRACE(4)
-+ /* r0: nfc base. Reloaded after each page copying */
-+ ldr r0, =IMX_NFC_MAIN_AREA0
-+
-+ /* r1: starting flash addr to be copied. Updated constantly */
-+ /* bypass the first preloaded pages */
-+ ldr r1, =(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0)
-+
-+ /* r2: end of 1st RAM buf. Doesn't change */
-+ ldr r2, =IMX_NFC_MAIN_AREA1
-+
-+ /* r12: NFC register base. Doesn't change */
-+ ldr r12, =IMX_NFC_REGS
-+
-+ ldr r11, =CONFIG_SYS_NAND_U_BOOT_DST
-+
-+ /* r13: end of SDRAM address for copying. Doesn't change */
-+ add r13, r11, #CONFIG_SYS_NAND_U_BOOT_SIZE
-+
-+ /* r11: starting SDRAM address for copying. Updated constantly */
-+ add r11, r11, r1
-+
-+ /* unlock internal buffer */
-+ ldr r3, =NFC_CONFIG_UNLOCKED
-+ strh r3, [r12, #NFC_OFFSET_CONFIG]
-+
-+ /* enable ECC and mask interrupts */
-+ ldr r3, =(NFC_CONFIG1_ECC_EN | NFC_CONFIG1_INT_MSK)
-+ strh r3, [r12, #NFC_OFFSET_CONFIG1]
-+
-+Nfc_Read_Page:
-+ BOOT_TRACE(5)
-+ /* send NAND_CMD_READ0 command */
-+ ldr r3, =NAND_CMD_READ0;
-+ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
-+
-+ ldr r3, =NFC_CONFIG2_FCMD
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ /* send NAND address to read. TODO small page support */
-+ BOOT_TRACE(6)
-+ mov r3, r1, lsr #1
-+ bl do_addr_input /* 1st addr cycle */
-+
-+ mov r3, r1, lsr #9
-+ and r3, r3, #0x03
-+ bl do_addr_input /* 2nd addr cycle */
-+
-+ mov r3, r1, lsr #11
-+ bl do_addr_input /* 3rd addr cycle */
-+
-+ mov r3, r1, lsr #19
-+ bl do_addr_input /* 4th addr cycle */
-+
-+ /* Small NAND flashs (== 1Gb) support 5 addr cycles */
-+ mov r3, r1, lsr #27
-+ bl do_addr_input /* 5th addr cycle */
-+
-+ /* send NAND_CMD_READSTART command. TODO small page support */
-+ BOOT_TRACE(7)
-+ mov r3, #NAND_CMD_READSTART;
-+ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
-+ mov r3, #NFC_CONFIG2_FCMD
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ /* read and copy buf 0 */
-+ BOOT_TRACE(8)
-+ mov r3, #0
-+ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+ mov r3, #NFC_CONFIG2_FDO_PAGE
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ bl Test_And_Copy_Buffer
-+
-+ /* read and copy buf 1 */
-+ mov r3, #1
-+ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+ mov r3, #NFC_CONFIG2_FDO_PAGE
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ bl Test_And_Copy_Buffer
-+
-+ /* here we should test if 512B page flash and bypass next buffers */
-+ /* read and copy buf 2. TODO small page support */
-+ mov r3, #2
-+ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+ mov r3, #NFC_CONFIG2_FDO_PAGE
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ bl Test_And_Copy_Buffer
-+
-+ /* read and copy buf 3 */
-+ mov r3, #3
-+ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+ mov r3, #NFC_CONFIG2_FDO_PAGE
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ bl Test_And_Copy_Buffer
-+
-+ /* is the last page ? */
-+ BOOT_TRACE(12)
-+ cmp r11, r13
-+ bge NAND_Copy_Main_done
-+
-+ /* r0: nfc base. Reloaded after each page copying */
-+ ldr r0, =IMX_NFC_MAIN_AREA0
-+ /* r2: end of 1st RAM buf. Doesn't change */
-+ ldr r2, =IMX_NFC_MAIN_AREA1
-+ b Nfc_Read_Page
-+
-+NAND_Copy_Main_done:
-+ BOOT_TRACE(13)
-+ .endm /* nand_boot */
-+
-+ .macro init_aipi
-+ /*
-+ * setup AIPI1 and AIPI2
-+ */
-+ writel(AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL)
-+ writel(AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL)
-+ writel(AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL)
-+ writel(AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL)
-+
-+ /* Change SDRAM signal strengh */
-+ ldr r0, =GPCR
-+ ldr r1, =CONFIG_SYS_GPCR_VAL
-+ ldr r5, [r0]
-+ orr r5, r5, r1
-+ str r5, [r0]
-+
-+ .endm /* init_aipi */
-+
-+ .macro init_clock
-+ ldr r0, =CSCR
-+ /* disable MPLL/SPLL first */
-+ ldr r1, [r0]
-+ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
-+ str r1, [r0]
-+
-+ /*
-+ * pll clock initialization predefined in apf27.h
-+ */
-+ writel(MPCTL0, CONFIG_SYS_MPCTL0_VAL)
-+ writel(SPCTL0, CONFIG_SYS_SPCTL0_VAL)
-+
-+ writel(CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
-+
-+ /*
-+ * add some delay here
-+ */
-+ mov r1, #0x1000
-+ 1: subs r1, r1, #0x1
-+ bne 1b
-+
-+ /* peripheral clock divider */
-+ writel(PCDR0, CONFIG_SYS_PCDR0_VAL)
-+ writel(PCDR1, CONFIG_SYS_PCDR1_VAL)
-+
-+ /* Configure PCCR0 and PCCR1 */
-+ writel(PCCR0, CONFIG_SYS_PCCR0_VAL)
-+ writel(PCCR1, CONFIG_SYS_PCCR1_VAL)
-+
-+ .endm /* init_clock */
-+
-+/*
-+ *************************************************************************
-+ *
-+ * No jump vector table. Use reset vector as direct entry point.
-+ * Do not support any interrupt event within SPL
-+ *
-+ *************************************************************************
-+ */
-+
-+
-+.globl _start
-+_start:
-+
-+/*
-+ *************************************************************************
-+ *
-+ * Startup Code (reset vector)
-+ *
-+ * do important init only if we don't start from memory!
-+ * setup Memory and board specific bits prior to relocation.
-+ * relocate armboot to ram
-+ * setup stack
-+ *
-+ *************************************************************************
-+ */
-+
-+
-+/*
-+ * the actual reset code
-+ */
-+
-+reset:
-+ /*
-+ * set the cpu to SVC32 mode
-+ */
-+ mrs r0,cpsr
-+ bic r0,r0,#0x1f
-+ orr r0,r0,#0xd3
-+ msr cpsr,r0
-+
-+ /*
-+ * invalidate I/D cache/TLB and drain write buffer
-+ */
-+ mov r0, #0
-+ mcr p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
-+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
-+ mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
-+
-+ /*
-+ * disable MMU stuff and caches
-+ */
-+ mrc p15, 0, r0, c1, c0, 0
-+ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
-+ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
-+ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
-+ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
-+ mcr p15, 0, r0, c1, c0, 0
-+
-+init_aipi_start:
-+ init_aipi
-+
-+ /* check if sdram has been setup (running within sdram) */
-+ cmp pc, #0xa0000000 /* start of first sdram memory space */
-+ blo init_clock_start
-+ cmp pc, #0xc0000000 /* end of second sdram memory space */
-+ blo regular_boot
-+
-+ /* running from sdram with full code present -> regular_boot */
-+init_clock_start:
-+ init_clock
-+
-+init_sdram_start:
-+ bl setup_sdram_ddr
-+
-+ /* save state of previous boot (SDRAM is configured)*/
-+ BACKUP_TRACE()
-+
-+ /* nand_boot BOOT_TRACE(1..13) */
-+
-+ nand_boot
-+
-+ BOOT_TRACE(14) /* start regular U-Boot */
-+
-+regular_boot: /* jump to start of next 2kiB block (U-Boot) */
-+ ldr r0, =0xfffff800
-+ and r0, r0, pc
-+ add pc, r0, #0x800
-+
-+do_wait_op_done:
-+ 1:
-+ ldrh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ ands r3, r3, #NFC_CONFIG2_INT
-+ beq 1b
-+ mov r3, #0x0
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ mov pc, lr
-+
-+do_addr_input:
-+ mov r9, lr
-+ and r3, r3, #0xFF
-+ strh r3, [r12, #NFC_OFFSET_FLASH_ADDR]
-+ mov r3, #NFC_CONFIG2_FADD
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+ mov pc, r9
-+
-+Test_And_Copy_Buffer:
-+ /* check for bad block (2 bits error in main or spare are)*/
-+ BOOT_TRACE(9)
-+ ldrh r4, [r12, #NFC_OFFSET_ECC_STATUS_RESULT]
-+ ands r4, r4, #(NFC_ECC_STAT_ERROR2|(NFC_ECC_STAT_ERROR2<<NFC_ECC_STAT_ERM_SHFT))
-+ bne Skip_Bad_Buffer
-+
-+ /* check BI byte of the current spare buffer */
-+ ldr r4, =IMX_NFC_SPARE_AREA0
-+ ldrh r3, [r12, #NFC_OFFSET_BUF_ADDR] /* for the current buffer */
-+ orr r4, r3, lsl #0x04
-+
-+ /* at bi word offset 4. Fixme position change betwwen 8 and 16 bits bus */
-+ ldrh r4, [r4, #0x04]
-+ and r4, r4, #0x0FF00 /* has to be 0xFFxx */
-+ cmp r4, #0x0FF00
-+ bne Skip_Bad_Buffer
-+
-+Copy_Good_Buffer:
-+ /* copying 512 bytes buffer */
-+ BOOT_TRACE(10)
-+1: ldmia r0!, {r3-r10}
-+ stmia r11!, {r3-r10}
-+ cmp r0, r2
-+ blo 1b
-+ b End_Of_Copy
-+
-+Skip_Bad_Buffer:
-+ BOOT_TRACE(11)
-+ /* bad pages do not contain valid data and have to be skip */
-+ add r0, r0, #0x200
-+
-+ /* rewind ram addr to start of buffer */
-+ ldr r3, =(~0x1FF)
-+ and r11, r11, r3
-+
-+End_Of_Copy:
-+ add r2, r2, #0x200
-+ add r1, r1, #0x200
-+
-+ mov pc, lr
-+
-+
-+setup_sdram_ddr:
-+
-+ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-+ ldr r0, =IMX_ESD_BASE
-+ ldr r4, =ESDMISC_SDRAM_RDY
-+2: ldr r1, [r0, #ESDMISC_ROF]
-+ ands r1, r1, r4
-+ bpl 2b
-+
-+ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-+ ldr r0, =IMX_ESD_BASE
-+ ldr r4, =CONFIG_SYS_ESDMISC_VAL
-+ orr r1, r4, #ESDMISC_MDDR_DL_RST
-+ str r1, [r0, #ESDMISC_ROF]
-+
-+ /* Hold for more than 200ns */
-+ ldr r1, =0x10000
-+ 1: subs r1, r1, #0x1
-+ bne 1b
-+
-+ str r4, [r0]
-+
-+ /* writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL) */
-+ ldr r0, =IMX_ESD_BASE
-+ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
-+ str r1, [r0, #ESDCFG0_ROF]
-+
-+ /* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
-+ ldr r0, =IMX_ESD_BASE
-+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
-+ str r1, [r0, #ESDCTL0_ROF]
-+
-+ /* writeb(0xA0001000, any value) */
-+ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+ strb r2, [r1]
-+
-+ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
-+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+ str r1, [r0, #ESDCTL0_ROF]
-+
-+ ldr r4, =PHYS_SDRAM_1 /* ...
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