[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-275-gfc3002d
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-275-gfc3002d
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From: jorasse <jo...@us...> - 2012-04-18 23:44:00
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the project "armadeus".
The branch, master has been updated
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via afad0dd4e4338c71a6ffc095ea3aba3bc25b12ad (commit)
from 21440c21c5195299324e64253b9435501f28f6ab (commit)
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- Log -----------------------------------------------------------------
commit fc3002de7891e356c505d9490cddf6a34c9cfb5b
Merge: afad0dd 21440c2
Author: Eric Jarrige <eri...@ar...>
Date: Thu Apr 19 01:55:18 2012 +0200
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit afad0dd4e4338c71a6ffc095ea3aba3bc25b12ad
Author: Eric Jarrige <eri...@ar...>
Date: Thu Apr 19 01:54:26 2012 +0200
[UBOOT][APF51] Refactor config file + support redundant environment + cleanup
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf51/apf51-u-boot-2011.12.h | 202 +++++++-------------
1 files changed, 70 insertions(+), 132 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
index 929b366..c6f3261 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
@@ -24,8 +24,8 @@
#define __CONFIG_H
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "0.9"
-#define CONFIG_IDENT_STRING " apf51 patch 0.11"
+#define CONFIG_ENV_VERSION "1.0"
+#define CONFIG_IDENT_STRING " apf51 patch 1.0"
#define CONFIG_BOARD_NAME apf51
/*
@@ -78,7 +78,6 @@
*/
#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
-#define CONFIG_SRV_PATH ""
#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root"
/*
@@ -99,7 +98,6 @@
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING /* ping support */
-/*#define CONFIG_CMD_SAVES*/ /* save S record dump */
/*#define CONFIG_CMD_SETEXPR*/ /* setexpr support */
/*#define CONFIG_CMD_UBI*/
/*#define CONFIG_CMD_UBIFS*/
@@ -110,9 +108,9 @@
#define CONFIG_NR_DRAM_POPULATED 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR /* SDRAM bank #1 */
-#define PHYS_SDRAM_SIZE 256
-#define PHYS_SDRAM_1_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
-#define PHYS_SDRAM_2_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
+#define PHYS_SDRAM_SIZE 256
+#define PHYS_SDRAM_1_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
+#define PHYS_SDRAM_2_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 * 1024 * 1024) )
#define CONFIG_SYS_MEMTEST_START 0x90000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x90100000 /* 1st MiB in DRAM */
@@ -120,9 +118,8 @@
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-#define CONFIG_SYS_GBL_DATA_OFFSET \
+#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
@@ -133,22 +130,29 @@
*/
#define CONFIG_SYS_MONITOR_OFFSET 0x00000000 /* offset in NAND */
#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
-#define CONFIG_ENV_RANGE 0x00100000 /* 1MB */
+#define CONFIG_ENV_RANGE 0x00080000 /* 512kB */
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
#define CONFIG_FIRMWARE_OFFSET 0x00200000
-#define CONFIG_FIRMWARE_LEN 0x00100000 /* 1MB */
-#define CONFIG_KERNEL_OFFSET 0x00300000
-#define CONFIG_KERNEL_LEN 0x00800000 /* 8MB (BB ready) */
-#define CONFIG_ROOTFS_OFFSET 0x00B00000
-#define CONFIG_ROOTFS_LEN /* entire flash if not specified */
-
-#define CONFIG_MTDMAP "mxc_nand"
-#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
-#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP ":1M(U-boot)ro," \
- "1M(U-boot_env),1M(firmware)," \
- "8M(kernel)," \
- "-(rootfs)"
+#define CONFIG_KERNEL_OFFSET 0x00400000
+#define CONFIG_ROOTFS_OFFSET 0x00C00000
+
+#define CONFIG_MTDMAP "mxc_nand"
+#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
+#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
+ ":1M(u-boot)ro," \
+ "512K(env)," \
+ "512K(env2)," \
+ "1M(firmware)," \
+ "512K(dtb)," \
+ "512K(splash)," \
+ "8M(kernel)," \
+ "-(rootfs)"
/*
* U-Boot general configurations
@@ -180,17 +184,18 @@
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTFILE "${board_name}-linux.bin"
-#define CONFIG_BOOTARGS \
- CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=ubifs " MTDPARTS_DEFAULT
+#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
+#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
+ MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
-#define CONFIG_CONSOLE "console=ttymxc2,"MK_STR(CONFIG_BAUDRATE)
+#define ACFG_CONSOLE_DEV ttymxc2
#define CONFIG_BOOTCOMMAND "run ubifsboot"
#define CONFIG_SYS_AUTOLOAD "no"
/*
* Default load address for user programs and kernel
*/
-#define CONFIG_LOADADDR 0x90000000
+#define CONFIG_LOADADDR 0x90000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_TFTP_LOADADDR CONFIG_LOADADDR
@@ -199,79 +204,62 @@
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"env_version=" CONFIG_ENV_VERSION "\0" \
- "fileaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
- "filesize=" MK_STR(CONFIG_SYS_MONITOR_LEN) "\0" \
- "console=" CONFIG_CONSOLE "\0" \
+ "consoledev=" MK_STR(ACFG_CONSOLE_DEV) "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,4\0" \
- "uboot_offset=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0" \
- "uboot_len=" MK_STR(CONFIG_SYS_MONITOR_LEN) "\0" \
- "env_offset=" MK_STR(CONFIG_ENV_OFFSET) "\0" \
- "env_len=" MK_STR(CONFIG_ENV_RANGE) "\0" \
- "firmware_offset=" MK_STR(CONFIG_FIRMWARE_OFFSET) "\0" \
- "firmware_len=" MK_STR(CONFIG_FIRMWARE_LEN) "\0" \
- "kernel_offset=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \
- "kernel_len=" MK_STR(CONFIG_KERNEL_LEN) "\0" \
- "rootfs_offset=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0" \
- "rootfs_len=" MK_STR(CONFIG_ROOTFS_LEN) "\0" \
+ "partition=nand0,7\0" \
+ "uboot_addr=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0" \
+ "env_addr=" MK_STR(CONFIG_ENV_OFFSET) "\0" \
+ "firmware_addr=" MK_STR(CONFIG_FIRMWARE_OFFSET) "\0" \
+ "kernel_addr=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \
+ "rootfs_addr=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0" \
"board_name=" MK_STR(CONFIG_BOARD_NAME) "\0" \
- "serverpath=" MK_STR(CONFIG_SRV_PATH) "\0" \
- "ntpserverip=217.147.208.1\0" \
- "mmcroot=/dev/mmcblk0p1\0" \
- "mmcrootfstype=ext2\0" \
"addnfsargs=setenv bootargs ${bootargs} " \
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"addubifsargs=setenv bootargs ${bootargs} " \
"ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
"addmmcargs=setenv bootargs ${bootargs} " \
- "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \
+ "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
"addipargs=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
"${hostname}:eth0:off\0" \
- "nfsboot=setenv bootargs ${console} ${mtdparts};" \
- "run addnfsargs addipargs; setenv autostart yes;" \
- "nboot 90800000 0 ${kernel_offset}\0" \
- "ubifsboot=setenv bootargs ${console} ${mtdparts};" \
- "run addubifsargs addipargs; setenv autostart yes;" \
- "nboot 90800000 0 ${kernel_offset}\0" \
- "mmcboot=setenv bootargs ${console} ${mtdparts};" \
- "run addmmcargs addipargs; setenv autostart yes;" \
- "nboot 90800000 0 ${kernel_offset}\0" \
+ "nfsboot=setenv bootargs console=${consoledev},${baudrate} " \
+ "${mtdparts}; run addnfsargs addipargs; setenv autostart yes;" \
+ "nboot 90800000 0 ${kernel_addr}\0" \
+ "ubifsboot=setenv bootargs console=${consoledev},${baudrate} " \
+ "${mtdparts};run addubifsargs addipargs; setenv autostart yes;"\
+ "nboot 90800000 0 ${kernel_addr}\0" \
+ "mmcboot=setenv bootargs console=${consoledev},${baudrate} " \
+ "${mtdparts}; run addmmcargs addipargs; setenv autostart yes;" \
+ "nboot 90800000 0 ${kernel_addr}\0" \
"firmware_autoload=0\0" \
- "flash_uboot=nand unlock ${uboot_offset} ${uboot_len};" \
- "nand erase ${uboot_offset} ${uboot_len};" \
- "if nand write.trimffs ${fileaddr} ${uboot_offset} ${filesize};" \
- "then nand lock; nand unlock ${env_offset};" \
+ "flash_uboot=nand unlock ${uboot_addr} ;" \
+ "nand erase.part u-boot;" \
+ "if nand write.trimffs ${fileaddr} ${uboot_addr} ${filesize};"\
+ "then nand lock; nand unlock ${env_addr};" \
"echo Flashing of uboot succeed;" \
"else echo Flashing of uboot failed;" \
"fi; \0" \
- "flash_firmware=nand erase ${firmware_offset} ${firmware_len};" \
- "if nand write.trimffs ${fileaddr} ${firmware_offset}" \
+ "flash_firmware=nand erase.part firmware;" \
+ "if nand write.trimffs ${fileaddr} ${firmware_addr}" \
" ${filesize};" \
"then echo Flashing of Firmware succeed;" \
"else echo Flashing of Firmware failed;" \
"fi\0" \
- "fpga_config=tftpboot ${fileaddr} $firmware_name;" \
- "run flash_firmware;" \
- "fpga load 0 ${fileaddr} ${firmware_len};\0" \
- "flash_kernel=nand erase ${kernel_offset} ${kernel_len};" \
- "if nand write.trimffs ${fileaddr} ${kernel_offset} ${filesize};"\
+ "flash_kernel=nand erase.part kernel;" \
+ "if nand write.trimffs ${fileaddr} ${kernel_addr} ${filesize};"\
"then echo Flashing of kernel succeed;" \
"else echo Flashing of kernel failed;" \
"fi\0" \
"flash_rootfs=nand erase.part rootfs;" \
- "if nand write.trimffs ${fileaddr} ${rootfs_offset} ${filesize};"\
+ "if nand write.trimffs ${fileaddr} ${rootfs_addr} ${filesize};"\
"then echo Flashing of rootfs succeed;" \
"else echo Flashing of rootfs failed;" \
"fi\0" \
"flash_reset_env=env default -f; saveenv;" \
"echo Flash environment variables erased!\0" \
- "download_uboot=tftpboot ${loadaddr} " \
- " ${serverpath}${board_name}-u-boot-nand.bin\0" \
- "download_kernel=tftpboot ${loadaddr} " \
- " ${serverpath}${board_name}-linux.bin\0" \
- "download_rootfs=tftpboot ${loadaddr} " \
- " ${serverpath}${board_name}-rootfs.ubi\0" \
+ "download_uboot=tftpboot ${loadaddr} ${board_name}-u-boot-nand.bin\0" \
+ "download_kernel=tftpboot ${loadaddr} ${board_name}-linux.bin\0" \
+ "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ubi\0" \
"update_uboot=run download_uboot flash_uboot\0" \
"update_kernel=run download_kernel flash_kernel\0" \
"update_rootfs=run download_rootfs flash_rootfs\0" \
@@ -283,9 +271,9 @@
* Serial Driver
*/
#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART3_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_MXC_UART_BASE UART3_BASE
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
/*
* GPIO
@@ -312,10 +300,6 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_NAND_QUIET 1
-/* Environment is in NAND */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OVERWRITE /* env is writable now */
-
/*
* Partitions & Filsystems
*/
@@ -417,9 +401,9 @@
/*
* Clocks
*/
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
-#define CONFIG_SYS_MX5_CLK32 32768
-#define CONFIG_SYS_MX5_HCLK 1024*CONFIG_SYS_MX5_CLK32
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_SYS_MX5_CLK32 32768
+#define CONFIG_SYS_MX5_HCLK 1024*CONFIG_SYS_MX5_CLK32
#define CONFIG_MX51_PLL_ERRATA
/* external bus frequencies */
@@ -502,51 +486,6 @@
* ACFG_SDRAM_SINGLE_ACCESS 1= single access; 0 = Burst mode
*
*/
-#if (PHYS_SDRAM_SIZE == 64) /* micron MT46H16M32LF -6 */
-/* micron 64MB */
-#define ACFG_SDRAM_NUM_COL 9 /* 8..11 column address bits */
-#define ACFG_SDRAM_NUM_ROW 13 /* 11..13 row address bits */
-#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.*/
-#define ACFG_SDRAM_XSR_DELAY 138 /* ns Exit self refresh */
-#define ACFG_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
-#define ACFG_SDRAM_W2R_DELAY 1 /* 0=1ck 1=2ck */
-#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk) */
-#define ACFG_SDRAM_TMRD_DELAY 2 /* 1..4 */
-#define ACFG_SDRAM_TWR_DELAY 1 /* DDR: 0=2ck 1=3ck */
-#define ACFG_SDRAM_RAS_DELAY 40 /* ns ACTIVE-to-PRECHARGE*/
-#define ACFG_SDRAM_RRD_DELAY 10 /* ns ACTIVE-to-ACTIVE delay*/
-#define ACFG_SDRAM_RCD_DELAY 15 /* ns Row to Column delay */
-#define ACFG_SDRAM_RC_DELAY 55 /* ns Row cycle delay */
-#define ACFG_SDRAM_RFC_DELAY 110 /* ns (> 10xddr_clk) */
-#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0..4 */
-#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0..3 */
-#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 0..1 */
-#endif
-
-#if (PHYS_SDRAM_SIZE == 128)
-/* micron 128MB */
-#define ACFG_SDRAM_NUM_COL 10 /* 8..11 column address bits */
-#define ACFG_SDRAM_NUM_ROW 13 /* 11..13 row address bits */
-#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.*/
-#define ACFG_SDRAM_XSR_DELAY 138 /* ns Exit self refresh */
-#define ACFG_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
-#define ACFG_SDRAM_W2R_DELAY 1 /* 0=1ck 1=2ck */
-#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk) */
-#define ACFG_SDRAM_TMRD_DELAY 2 /* 1..4 */
-#define ACFG_SDRAM_TWR_DELAY 1 /* DDR: 0=2ck 1=3ck */
-#define ACFG_SDRAM_RAS_DELAY 40 /* ns ACTIVE-to-PRECHARGE */
-#define ACFG_SDRAM_RRD_DELAY 10 /* ns ACTIVE-to-ACTIVE delay */
-#define ACFG_SDRAM_RCD_DELAY 15 /* ns Row to Column delay */
-#define ACFG_SDRAM_RC_DELAY 55 /* ns Row cycle delay */
-#define ACFG_SDRAM_RFC_DELAY 110 /* ns (> 10xddr_clk) */
-#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0..4 */
-#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0..3 */
-#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 0..1 */
-#endif
-
-#if (PHYS_SDRAM_SIZE == 256)
/* micron 256MB */
#define ACFG_SDRAM_NUM_COL 10 /* 8..11 column address bits */
#define ACFG_SDRAM_NUM_ROW 14 /* 11..13 row address bits */
@@ -566,14 +505,13 @@
#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0..3 */
#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 0..1 */
-#endif
/*
* External interface
*/
/* force BCLK free run */
-#define ACFG_WCR_VALUE 0x00000021
-#define ACFG_WIAR_VALUE 0x00000010
+#define ACFG_WCR_VALUE 0x00000021
+#define ACFG_WIAR_VALUE 0x00000010
/* CS1 */
#define ACFG_CS1GCR1_VALUE ACFG_FPGA_GCR1_VALUE
@@ -642,7 +580,7 @@
(((ACFG_SDRAM_PARTIAL_ARRAY_SR&0x7)<<0)\
| ((ACFG_SDRAM_DRIVE_STRENGH&0x7)<<(5)))
-#define ACFG_SDRAM_ESDGPR_REGISTER_VAL 0x20020000
+#define ACFG_SDRAM_ESDGPR_REGISTER_VAL 0x20020000
#define ACFG_SDRAM_ESDCDLY1_REGISTER_VAL 0x00F48000
#define ACFG_SDRAM_ESDCDLY2_REGISTER_VAL 0x00F48000
#define ACFG_SDRAM_ESDCDLY3_REGISTER_VAL 0x00F48000
hooks/post-receive
--
armadeus
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