[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-272-ge47daff
Brought to you by:
sszy
Menu
▾
▴
[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-272-ge47daff
|
From: jorasse <jo...@us...> - 2012-04-18 21:22:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via e47daff1bca2e6e8cd6dd5250be7b9501b9bf1b5 (commit)
from ab8fcf6f1d02b5e285f84aeba0ea350ac108998b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e47daff1bca2e6e8cd6dd5250be7b9501b9bf1b5
Author: Eric Jarrige <eri...@ar...>
Date: Wed Apr 18 23:34:02 2012 +0200
[UBOOT][PPS] Refactore config file + support redundant environment + cleanup
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/pps/pps-u-boot-2011.12.h | 305 +++++++-------------
1 files changed, 109 insertions(+), 196 deletions(-)
diff --git a/buildroot/target/device/armadeus/pps/pps-u-boot-2011.12.h b/buildroot/target/device/armadeus/pps/pps-u-boot-2011.12.h
index ab5baf9..2f97910 100644
--- a/buildroot/target/device/armadeus/pps/pps-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/pps/pps-u-boot-2011.12.h
@@ -24,8 +24,8 @@
#define __CONFIG_H
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "2.3"
-#define CONFIG_IDENT_STRING " pps patch 2.10"
+#define CONFIG_ENV_VERSION "3.0"
+#define CONFIG_IDENT_STRING " pps patch 3.0"
#define CONFIG_BOARD_NAME pps
/*
@@ -68,7 +68,6 @@
#define CONFIG_BOOTP_DNS2
#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
-#define CONFIG_SRV_PATH ""
#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root"
/*
@@ -93,9 +92,7 @@
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_PING /* ping support */
-/*#define CONFIG_CMD_SAVES*/ /* save S record dump */
#define CONFIG_CMD_SETEXPR /* setexpr support */
-/*#define CONFIG_CMD_SNTP */ /* SNTP support */
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
@@ -107,17 +104,13 @@
#define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
-#define PHYS_SDRAM_1 0xA0000000
-#define PHYS_SDRAM_2 0xB0000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
+#define PHYS_SDRAM_1 0xA0000000
+#define PHYS_SDRAM_2 0xB0000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10) )
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
-#define CONFIG_SYS_MEMTEST_END 0xA0300000 /*64MiB -1MiB*/
-
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
-
-/*#define CONFIG_STACKSIZE (256<<10)*//* stack size */
+#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
+ PHYS_SDRAM_1_SIZE - 0x0100000)
@@ -127,25 +120,31 @@
/*
* FLASH organization
*/
-#define CONFIG_SYS_MONITOR_BASE 0xAFF00000
+/*#define CONFIG_SYS_MONITOR_BASE 0xAFF00000*/
#define CONFIG_SYS_MONITOR_OFFSET 0x00000000
-#define CONFIG_SYS_MONITOR_LEN 0x000A0000 /* 640kB ( 5 flash blocks ) */
-#define CONFIG_ENV_OFFSET 0x000A0000 /* NAND offset address for now*/
-#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
-#define CONFIG_ENV_RANGE 0X00060000 /* 384kB ( 3 flash blocks ) */
-#define CONFIG_FIRMWARE_OFFSET 0x00100000
-#define CONFIG_FIRMWARE_LEN 0x00080000 /* 512kB ( 4 flash blocks ) */
-#define CONFIG_KERNEL_OFFSET 0x00180000
-#define CONFIG_KERNEL_LEN 0x00500000 /* 5.0MB */
-#define CONFIG_ROOTFS_OFFSET 0x00680000
-#define CONFIG_ROOTFS_LEN /* entire flash if not specified ~116MB*/
-
-#define CONFIG_MTDMAP "mxc_nand.0"
-#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
-#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP ":640k(U-boot)ro," \
- "384k(U-boot_env),512k(firmware)," \
- "5M(kernel)," \
- "-(rootfs)"
+#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
+#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
+#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
+#define CONFIG_FIRMWARE_OFFSET 0x00200000
+#define CONFIG_KERNEL_OFFSET 0x00300000
+#define CONFIG_ROOTFS_OFFSET 0x00800000
+
+#define CONFIG_MTDMAP "mxc_nand.0"
+#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
+#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
+ ":1M(u-boot)ro," \
+ "512K(env)," \
+ "512K(env2)," \
+ "512k(firmware)," \
+ "512K(dtb)," \
+ "5M(kernel)," \
+ "-(rootfs)"
/*
* U-Boot general configurations
@@ -177,16 +176,17 @@
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
-#define CONFIG_BOOTARGS \
- CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=ubifs " MTDPARTS_DEFAULT
+#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
+ MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
+ " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
-#define CONFIG_CONSOLE "console=ttySMX0,"MK_STR(CONFIG_BAUDRATE)" otg_mode=device"
+#define ACFG_CONSOLE_DEV ttySMX0
#define CONFIG_BOOTCOMMAND "run ubifsboot"
#define CONFIG_SYS_AUTOLOAD "no"
/*
* Default load address for user programs and kernel
*/
-#define CONFIG_LOADADDR 0xA0000000
+#define CONFIG_LOADADDR 0xA0000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_TFTP_LOADADDR CONFIG_LOADADDR
@@ -194,50 +194,44 @@
* Extra Environments
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "env_version=" CONFIG_ENV_VERSION "\0" \
- "fileaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
- "filesize=" MK_STR(0x00080000) "\0" \
- "console=" CONFIG_CONSOLE "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,4\0" \
- "uboot_offset=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0" \
- "uboot_len=" MK_STR(CONFIG_SYS_MONITOR_LEN) "\0" \
- "env_offset=" MK_STR(CONFIG_ENV_OFFSET) "\0" \
- "env_len=" MK_STR(CONFIG_ENV_SIZE) "\0" \
- "firmware_offset=" MK_STR(CONFIG_FIRMWARE_OFFSET) "\0" \
- "firmware_len=" MK_STR(CONFIG_FIRMWARE_LEN) "\0" \
- "kernel_offset=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \
- "kernel_len=" MK_STR(CONFIG_KERNEL_LEN) "\0" \
- "rootfs_offset=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0" \
- "rootfs_len=" MK_STR(CONFIG_ROOTFS_LEN) "\0" \
- "board_name=" MK_STR(CONFIG_BOARD_NAME) "\0" \
- "serverpath=" MK_STR(CONFIG_SRV_PATH) "\0" \
- "ntpserverip=217.147.208.1\0" \
- "mmcroot=/dev/mmcblk0p1\0" \
- "mmcrootfstype=ext2\0" \
+ "env_version=" CONFIG_ENV_VERSION "\0" \
+ "consoledev=" MK_STR(ACFG_CONSOLE_DEV) "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,6\0" \
+ "u-boot_addr=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0" \
+ "env_addr=" MK_STR(CONFIG_ENV_OFFSET) "\0" \
+ "firmware_addr=" MK_STR(CONFIG_FIRMWARE_OFFSET) "\0" \
+ "kernel_addr=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \
+ "rootfs_addr=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0" \
+ "board_name=" MK_STR(CONFIG_BOARD_NAME) "\0" \
"addnfsargs=setenv bootargs ${bootargs} " \
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"addubifsargs=setenv bootargs ${bootargs} " \
"ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
"addmmcargs=setenv bootargs ${bootargs} " \
- "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \
+ "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
"addipargs=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off \0"\
- "nfsboot=setenv bootargs ${console} ${mtdparts};" \
- "run addnfsargs addipargs; setenv autostart yes;" \
- "nboot A0000000 0 ${kernel_offset}\0" \
- "nfsboot2=setenv bootargs ${console} ${mtdparts};" \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+ "${hostname}:eth0:off \0" \
+ "nfsboot=setenv bootargs console=${consoledev},${baudrate} " \
+ "${mtdparts} otg_mode=device; " \
+ "run addnfsargs addipargs; setenv autostart yes;" \
+ "nboot kernel\0" \
+ "nfsboot2=setenv bootargs console=${consoledev},${baudrate} " \
+ "${mtdparts} otg_mode=device; " \
"run addnfsargs addipargs; setenv autostart yes;" \
"setenv kernel_image ${board_name}-linux.bin;" \
"nfs ${loadaddr} " \
"${serverip}:${rootpath}/${kernel_image};" \
"bootm\0" \
- "ubifsboot=setenv bootargs ${console} ${mtdparts};" \
+ "ubifsboot=setenv bootargs console=${consoledev},${baudrate} " \
+ "${mtdparts} otg_mode=device; " \
"run addubifsargs addipargs; setenv autostart yes;" \
- "nboot A0000000 0 ${kernel_offset}\0" \
- "mmcboot=setenv bootargs ${console} ${mtdparts};" \
+ "nboot kernel\0" \
+ "mmcboot=setenv bootargs console=${consoledev},${baudrate} " \
+ "${mtdparts} otg_mode=device; " \
"run addmmcargs addipargs; setenv autostart yes;" \
- "nboot A0000000 0 ${kernel_offset}\0" \
+ "nboot kernel\0" \
"boot_nfs_fallback_flash=if ping ${serverip};" \
"then echo Boot over NFS; run nfsboot;" \
"else echo Boot from the board; run ubifsboot;" \
@@ -246,40 +240,34 @@
"then echo Boot over NFS; run nfsboot2;" \
"else echo Boot from the board; run ubifsboot;" \
"fi\0" \
- "firmware_autoload=0\0" \
- "flash_uboot=nand unlock ${uboot_offset} ${uboot_len};" \
- "nand erase ${uboot_offset} ${uboot_len};" \
- "if nand write.trimffs ${fileaddr} ${uboot_offset} ${filesize};" \
- "then nand lock; nand unlock ${env_offset};" \
- "echo Flashing of uboot succeed;" \
+ "firmware_autoload=0\0" \
+ "flash_uboot=nand unlock ${u-boot_addr} ;" \
+ "nand erase.part u-boot;" \
+ "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
+ "then nand lock; nand unlock ${env_addr};" \
+ "echo Flashing of uboot succeed;" \
"else echo Flashing of uboot failed;" \
"fi; \0" \
- "flash_firmware=nand erase ${firmware_offset} ${firmware_len};"\
- "if nand write.trimffs ${fileaddr} ${firmware_offset} ${filesize} ;"\
- "then echo Flashing of Firmware succeed;" \
- "else echo Flashing of Firmware failed;" \
+ "flash_firmware=nand erase.part firmware;" \
+ "if nand write.trimffs ${fileaddr} ${firmware_addr} ${filesize};"\
+ "then echo Flashing of Firmware succeed;" \
+ "else echo Flashing of Firmware failed;" \
"fi\0" \
- "fpga_config=tftpboot ${fileaddr} $firmware_name;"\
- "run flash_firmware;"\
- "fpga load 0 ${fileaddr} ${firmware_len};\0"\
- "flash_kernel=nand erase ${kernel_offset} ${kernel_len};" \
- "if nand write.trimffs ${fileaddr} ${kernel_offset} ${filesize} ;"\
+ "flash_kernel=nand erase.part kernel;" \
+ "if nand write.trimffs ${fileaddr} ${kernel_addr} ${filesize};"\
"then echo Flashing of kernel succeed;" \
"else echo Flashing of kernel failed;" \
"fi\0" \
"flash_rootfs=nand erase.part rootfs;" \
- "if nand write.trimffs ${fileaddr} ${rootfs_offset} ${filesize};"\
+ "if nand write.trimffs ${fileaddr} ${rootfs_addr} ${filesize};"\
"then echo Flashing of rootfs succeed;" \
"else echo Flashing of rootfs failed;" \
"fi\0" \
"flash_reset_env=env default -f; saveenv;" \
"echo Flash environment variables erased!\0" \
- "download_uboot=tftpboot ${loadaddr} " \
- " ${serverpath}${board_name}-u-boot-nand.bin\0" \
- "download_kernel=tftpboot ${loadaddr} " \
- " ${serverpath}${board_name}-linux.bin\0" \
- "download_rootfs=tftpboot ${loadaddr} " \
- " ${serverpath}${board_name}-rootfs.ubi\0" \
+ "download_uboot=tftpboot ${loadaddr} ${board_name}-u-boot-nand.bin\0" \
+ "download_kernel=tftpboot ${loadaddr} ${board_name}-linux.bin\0" \
+ "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ubi\0" \
"update_uboot=run download_uboot flash_uboot\0" \
"update_kernel=run download_kernel flash_kernel\0" \
"update_rootfs=run download_rootfs flash_rootfs\0" \
@@ -292,10 +280,10 @@
*/
#define CONFIG_MXC_UART
#define CONFIG_SYS_MX27_UART1
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_MXC_UART_BASE UART1_BASE
/*
* GPIO
@@ -323,11 +311,7 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_BOOT_TRACE_REG 0xAFFFFFF8 /* Addr to store traces of SPL boot */
-
-/* Environment is in NAND */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OVERWRITE /* env is writable now */
+#define CONFIG_BOOT_TRACE_REG 0xAFFFFFF8 /* Addr to store traces of SPL boot*/
/*
* Partitions & Filsystems
@@ -344,10 +328,9 @@
#define CONFIG_LZO
/*
- * Ethernet (on SOC mx28 FEC)
+ * Ethernet (on SOC imx FEC)
*/
#define CONFIG_FEC_MXC
-#undef CONFIG_FEC_IMX27_DEBUG
#define CONFIG_NET_MULTI
#define CONFIG_FEC_MXC_PHYADDR 0x1f
@@ -393,21 +376,23 @@
* I2C
*/
-//#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C 1
-//#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-//#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
-//#define CONFIG_I2C_CMD_TREE
-//#define CONFIG_I2C_MULTI_BUS 2
-//#define CONFIG_SYS_I2C_NOPROBES { }
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_I2C_MULTI_BUS 2
+#define CONFIG_SYS_I2C_NOPROBES { }
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x00*/
+#ifdef CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
+#endif /* CONFIG_CMD_EEPROM */
+#endif /* CONFIG_CMD_I2C */
/*
* SPI
@@ -426,8 +411,10 @@
/*
* RTC
*/
+#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_DS1374
#define CONFIG_SYS_RTC_BUS_NUM 0
+#endif /* CONFIG_CMD_DATE */
/*
* Watchdog Config
@@ -440,7 +427,7 @@
/*
* Clocks
*/
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
/*
* PLL
@@ -448,8 +435,8 @@
* 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
* |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
*/
-#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
-#undef CONFIG_MX27_CLK26 /* there is no external 26MHz external clock */
+#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
+#undef CONFIG_MX27_CLK26 /* No external 26MHz external clock */
/* MPU CLOCK source before PLL */
/* CONFIG_SYS_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) */
@@ -471,7 +458,7 @@
#define CONFIG_SYS_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
-/* Serial clock source before PLL (should be named CONFIG_SYS_SYSPLL_CLK_FREQ) */
+/* Serial clock source before PLL (should be named CONFIG_SYS_SYSPLL_CLK_FREQ)*/
#ifndef CONFIG_MX27_CLK26
/*#define CONFIG_SYSPLL_CLK_FREQ (1024*CONFIG_MX27_CLK32)*/
#if (CONFIG_MX27_CLK32 == 32000)
@@ -516,79 +503,10 @@
/*
* SDRAM
*/
-#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 8)
-/* micron 8MB */
-#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
-#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
-#define CONFIG_SYS_SDRAM_NUM_COL 8 /* 8, 9, 10 or 11 column address bits */
-#define CONFIG_SYS_SDRAM_NUM_ROW 11 /* 11, 12 or 13 row address bits */
-#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power down delay */
-#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read cycle delay > 0 */
-#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
-#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register cycle delay 1..4 */
-#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; SDRAM: 0=1ck 1=2ck*/
-#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
-#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
-#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
-#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC refresh to command)*/
-#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 20 /* ns clock cycle time estimated fo CL=1 0=force 3 for lpddr*/
-#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 3=Eighth 4=Sixteenth */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 2=quater 3=Eighth */
-#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
-#endif
-
-#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 16)
-/* micron 16MB */
-#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */
-#define CONFIG_SYS_SDRAM_NUM_COL 8 /* 8, 9, 10 or 11 column address bits */
-#define CONFIG_SYS_SDRAM_NUM_ROW 12 /* 11, 12 or 13 row address bits */
-#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power down delay */
-#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read cycle delay > 0 */
-#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
-#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register cycle delay 1..4 */
-#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; SDRAM: 0=1ck 1=2ck*/
-#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
-#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
-#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
-#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC refresh to command)*/
-#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time estimated fo CL=1 0=force 3 for lpddr*/
-#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 3=Eighth 4=Sixteenth */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 2=quater 3=Eighth */
-#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
-#endif
-
-#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 32)
-/* micron 32MB */
-#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define PHYS_SDRAM_2_SIZE 0x02000000 /* 32 MB */
-#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
-#define CONFIG_SYS_SDRAM_NUM_ROW 12 /* 11, 12 or 13 row address bits */
-#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-#define CONFIG_SYS_SDRAM_EXIT_PWD 25 /* ns exit power down delay */
-#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* write to read cycle delay > 0 */
-#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
-#define CONFIG_SYS_SDRAM_TMRD_DELAY 2 /* Load mode register cycle delay 1..4 */
-#define CONFIG_SYS_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck; SDRAM: 0=1ck 1=2ck*/
-#define CONFIG_SYS_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
-#define CONFIG_SYS_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
-#define CONFIG_SYS_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
-#define CONFIG_SYS_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC refresh to command)*/
-#define CONFIG_SYS_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time estimated fo CL=1 0=force 3 for lpddr*/
-#define CONFIG_SYS_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 3=Eighth 4=Sixteenth */
-#define CONFIG_SYS_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 2=quater 3=Eighth */
-#define CONFIG_SYS_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
-#endif
-
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
/* micron 64MB */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 13 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -610,8 +528,8 @@
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 128)
/* micron 128MB */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -633,8 +551,8 @@
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 256)
/* micron 256MB */
-#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
-#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
+#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -815,12 +733,7 @@
/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
#define CONFIG_SYS_GPCR_VAL 0x0003000F
-/* LPDDR enable. latency hiding behavior enabled */
-//#define CONFIG_SYS_ESDMISC_VAL ESDMISC_MA10_SHARE+ESDMISC_MDDREN
-/*
- * safe value in case of erratic crash during boot
- * (seen with some prototype boards)*/
-#define CONFIG_SYS_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
+#define CONFIG_SYS_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
#if (CONFIG_NR_DRAM_BANKS == 1)
hooks/post-receive
--
armadeus
|
