[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-202-gb7de470
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-202-gb7de470
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From: jorasse <jo...@us...> - 2012-03-27 09:28:06
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The branch, master has been updated
via b7de470530a894ad8b091188d33eb0722b0166b4 (commit)
via 52bd75fb1bfd77baba4e36d1bce374f0cc09e336 (commit)
via 3c352c67fdf22595d7504b0b83a0826d14b9e138 (commit)
via 0fbc8acdd30173e9ee06a446cb92798557933fe0 (commit)
via b74c496a31bf5714fefd21a68ee938f961a49ede (commit)
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- Log -----------------------------------------------------------------
commit b7de470530a894ad8b091188d33eb0722b0166b4
Merge: 52bd75f be1abdd
Author: Eric Jarrige <eri...@ar...>
Date: Tue Mar 27 11:39:06 2012 +0200
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit 52bd75fb1bfd77baba4e36d1bce374f0cc09e336
Author: Eric Jarrige <eri...@ar...>
Date: Tue Mar 27 11:37:15 2012 +0200
[UBOOT] apf9328 does not support board and cpu display infos
commit 3c352c67fdf22595d7504b0b83a0826d14b9e138
Author: Eric Jarrige <eri...@ar...>
Date: Tue Mar 27 10:13:33 2012 +0200
change to fix config_cmd_default.h dependencies
Signed-off-by: Eric Jarrige <eri...@ar...>
commit 0fbc8acdd30173e9ee06a446cb92798557933fe0
Merge: b74c496 1430e6f
Author: Eric Jarrige <eri...@ar...>
Date: Sat Mar 24 12:06:01 2012 +0100
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit b74c496a31bf5714fefd21a68ee938f961a49ede
Author: Eric Jarrige <eri...@ar...>
Date: Sat Mar 24 11:06:36 2012 +0100
[UBOOT] Update config file structure for all APF boards
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf27/apf27-u-boot-2011.12.h | 577 +++++++++----------
.../device/armadeus/apf28/apf28-u-boot-2011.12.h | 352 ++++++-----
.../device/armadeus/apf51/apf51-u-boot-2011.12.h | 622 +++++++++-----------
.../armadeus/apf9328/apf9328-u-boot-2011.12.h | 416 ++++++-------
4 files changed, 936 insertions(+), 1031 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
index 9ac2f98..ce0215c 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
@@ -1,8 +1,8 @@
/*
*
- * Configuration settings for the Armadeus Project apf27 board.
+ * Configuration settings for the Armadeus Project motherboard APF27
*
- * Copyright (c) 2008-2010 Eric Jarrige <eri...@ar...>
+ * Copyright (C) 2008-2012 ej / Armadeus Project <eri...@ar...>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -18,123 +18,186 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
- *
- * 2008/08/19 Initial version based on apf9328 configuration file
- * 2008/10/09 Release 1.0 support u-boot 1.3.4
- * 2008/10/25 Release 1.1 added environment version
- * 2008/11/01 Release 1.2 flash size independant
- * 2008/11/09 Release 1.3 keep uboot partition locked & source clean-up
- * 2010/03/31 U-Boot 2010.03 migration. TODO merge mxc_i2c..
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "2.1"
-#define CONFIG_IDENT_STRING " apf27 patch 2.8"
-
-#define CONFIG_ARM926EJS 1 /* this is an ARM926EJS CPU */
-#define CONFIG_MX27 1 /* in a Freescale i.MX27 Chip */
-#define CONFIG_APF27 1 /* on a Armadeus project APF27 board */
-#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
-#define CONFIG_MACH_TYPE 1698
+#define CONFIG_ENV_VERSION "2.2"
+#define CONFIG_IDENT_STRING " apf27 patch 2.9"
+#define CONFIG_BOARD_NAME apf27
/*
- * Enable the call to misc_init_r() for miscellaneous platform
- * dependent initialization.
+ * SoC configurations
*/
+#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
+#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
+#define CONFIG_MACH_TYPE 1698 /* APF27 */
+/*
+ * Enable the call to miscellaneous platform dependent initialization.
+ */
+#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
#define CONFIG_MISC_INIT_R
/*
+ * Board display option
+ */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * SPL
+ */
+#define CONFIG_NAND_U_BOOT
+/* Copy SPL+U-Boot here */
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR
+/* Size is the partion size */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
+
+/*
* BOOTP options
*/
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
-#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
-/*
- * Select serial console configuration
- */
-#define CONFIG_MXC_UART
-#define CONFIG_SYS_MX27_UART1
-#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.10
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+
+#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
+#define CONFIG_SRV_PATH ""
+#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root"
/*
- * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
- * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
- * functionality or size of u-boot code.
+ * U-Boot Commands
*/
-
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV /* ask for env variable */
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
-#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
-/*#define CONFIG_CMD_DATE */ /* support for RTC, date/time...*/
+/*#define CONFIG_CMD_DATE */ /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
-#define CONFIG_CMD_DIAG /* Diagnostics */
+#define CONFIG_CMD_DNS
/*#define CONFIG_CMD_EEPROM */ /* EEPROM read/write support */
#define CONFIG_CMD_FAT /* FAT support */
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-/*#define CONFIG_CMD_I2C */ /* I2C serial bus support */
+/*#define CONFIG_CMD_I2C */ /* I2C serial bus support */
#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
-#undef CONFIG_CMD_IMLS /* List all found images */
-#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_CMD_MTDPARTS /* MTD partition support */
-#define CONFIG_CMD_MMC /* MMC memory mapped support */
+/*#define CONFIG_CMD_MMC*/ /* MMC memory mapped support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_PING /* ping support */
-#define CONFIG_CMD_SAVES /* save S record dump */
+/*#define CONFIG_CMD_SAVES*/ /* save S record dump */
#define CONFIG_CMD_SETEXPR /* setexpr support */
/*#define CONFIG_CMD_SNTP */ /* SNTP support */
-#define CONFIG_CMD_NFS /* NFS support */
-#define CONFIG_CMD_DNS
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
+
+#define PHYS_SDRAM_1 0xA0000000
+#define PHYS_SDRAM_2 0xB0000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10) )
+#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
+#define CONFIG_SYS_MEMTEST_END 0xA0300000 /*64MiB -1MiB*/
+
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
+
+/*#define CONFIG_STACKSIZE (256<<10)*//* stack size */
+
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
+ + PHYS_SDRAM_1_SIZE - 0x0100000)
+
+#define CONFIG_SYS_TEXT_BASE 0xA1000000
/*
- * Select some advanced features of the commande line parser
+ * FLASH organization
*/
-#define CONFIG_AUTO_COMPLETE 1 /* Enable auto completion of */
- /* commands using TAB */
-#define CONFIG_SYS_HUSH_PARSER 1 /* enable the "hush" shell */
+#define CONFIG_SYS_MONITOR_BASE 0xAFF00000
+#define CONFIG_SYS_MONITOR_OFFSET 0x00000000
+#define CONFIG_SYS_MONITOR_LEN 0x000A0000 /* 640kB ( 5 flash blocks ) */
+#define CONFIG_ENV_OFFSET 0x000A0000 /* NAND offset address for now*/
+#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
+#define CONFIG_ENV_RANGE 0X00060000 /* 384kB ( 3 flash blocks ) */
+#define CONFIG_FIRMWARE_OFFSET 0x00100000
+#define CONFIG_FIRMWARE_LEN 0x00080000 /* 512kB ( 4 flash blocks ) */
+#define CONFIG_KERNEL_OFFSET 0x00180000
+#define CONFIG_KERNEL_LEN 0x00500000 /* 5.0MB */
+#define CONFIG_ROOTFS_OFFSET 0x00680000
+#define CONFIG_ROOTFS_LEN /* entire flash if not specified ~116MB*/
+
+#define CONFIG_MTDMAP "mxc_nand.0"
+#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
+#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP ":640k(U-boot)ro," \
+ "384k(U-boot_env),512k(firmware)," \
+ "5M(kernel)," \
+ "-(rootfs)"
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
+#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 16 /* max command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
-#define CONFIG_CMDLINE_EDITING 1
/*
- * Boot options. Setting delay to -1 stops autostart count down.
+ * Boot Linux
*/
+#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG /* send initrd params */
+/*
+#define CONFIG_REVISION_TAG
+#define CONFIG_OF_LIBFDT
+*/
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK
-
+#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
#define CONFIG_BOOTARGS \
CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=ubifs " MTDPARTS_DEFAULT
#define CONFIG_CONSOLE "console=ttySMX0,"MK_STR(CONFIG_BAUDRATE)
-#define CONFIG_MTDMAP "mxc_nand.0"
-#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
-#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP ":640k(U-boot)ro," \
- "384k(U-boot_env),512k(firmware)," \
- "5M(kernel)," \
- "-(rootfs)"
+#define CONFIG_BOOTCOMMAND "run ubifsboot"
+#define CONFIG_SYS_AUTOLOAD "no"
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_LOADADDR 0xA0000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_TFTP_LOADADDR CONFIG_LOADADDR
+/*
+ * Extra Environments
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
"env_version=" CONFIG_ENV_VERSION "\0" \
"fileaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
@@ -157,7 +220,6 @@
"ntpserverip=217.147.208.1\0" \
"mmcroot=/dev/mmcblk0p1\0" \
"mmcrootfstype=ext2\0" \
- "quiet=1\0" \
"addnfsargs=setenv bootargs ${bootargs} " \
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"addubifsargs=setenv bootargs ${bootargs} " \
@@ -215,8 +277,7 @@
"then echo Flashing of rootfs succeed;" \
"else echo Flashing of rootfs failed;" \
"fi\0" \
- "flash_reset_env=nand unlock ${env_offset} ${env_len};" \
- "nand erase ${env_offset} ${env_len};" \
+ "flash_reset_env=env default -f; saveenv;" \
"echo Flash environment variables erased!\0" \
"download_uboot=tftpboot ${loadaddr} " \
" ${serverpath}${board_name}-u-boot.bin\0" \
@@ -231,71 +292,166 @@
"flash_rootfs download_uboot flash_uboot\0" \
"unlock_regs=mw 10000008 0; mw 10020008 0\0" \
-#define CONFIG_BOOTCOMMAND "run ubifsboot"
-#define CONFIG_SYS_AUTOLOAD "no"
-#define CFG_DIRECT_FLASH_TFTP
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX27_UART1
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_MXC_UART_BASE UART1_BASE
-#undef CONFIG_SHOW_BOOT_PROGRESS
+/*
+ * GPIO
+ */
-#define CONFIG_ETHADDR
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.0.10
-#define CONFIG_BOARD_NAME "apf27"
-#define CONFIG_HOSTNAME "apf27"
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_SRV_PATH ""
-#define CONFIG_ROOTPATH "/tftpboot/apf27-root"
+/*
+ * NOR
+ */
/*
- * General options for u-boot. Modify to save memory foot print
+ * NAND
*/
+#define CONFIG_NAND_MXC
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
-#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
+#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
+#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
-#define CONFIG_SYS_MEMTEST_END 0xA0300000 /*64MiB -1MiB*/
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define IMX27_NAND_16BITS
+#define NAND_MAX_CHIPS 1
+
+/*#define CONFIG_SYS_DIRECT_FLASH_TFTP*/
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_SYS_NAND_QUIET 1
+
+#define CONFIG_BOOT_TRACE_REG 0xAFFFFFF8 /* Addr to store traces of SPL boot */
-#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1 MHz */
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE /* env is writable now */
/*
- * Definitions related to passing arguments to kernel.
+ * Partitions & Filsystems
*/
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
-#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
-#define CONFIG_INITRD_TAG 1 /* send initrd params */
-#undef CONFIG_VFD /* do not send framebuffer setup */
+/*
+ * UBIFS
+ */
+#define CONFIG_RBTREE
+#define CONFIG_LZO
/*
- * Malloc pool need to host env + 512 Kb reserve for other allocations.
+ * Ethernet (on SOC mx28 FEC)
*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10) )
+#define CONFIG_FEC_MXC
+#undef CONFIG_FEC_IMX27_DEBUG
-#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC_PHYADDR 0x1f
+#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_STACKSIZE (256<<10) /* stack size */
+/*
+ * FPGA
+ */
+#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_WAIT 20000 /* 20 ms */
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_CHECK_ERROR
+//#define CONFIG_SYS_FPGA_IS_PROTO /* to be defined with apf27 board prototype*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */
+#define CONFIG_SYS_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */
+#define CONFIG_SYS_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */
+#define CONFIG_SYS_FPGA_RDATA 0xD6000000 /* FPGA data addr */
+#define CONFIG_SYS_FPGA_WDATA 0xD6000000 /* FPGA data addr */
+#define CONFIG_SYS_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
+#define CONFIG_SYS_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */
+#define CONFIG_SYS_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
+#define CONFIG_SYS_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
+#define CONFIG_SYS_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
+#define CONFIG_SYS_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
+/*
+ * Fuses - IIM
+ */
+#ifdef CONFIG_CMD_IMX_FUSE
+#define IIM_MAC_BANK 0
+#define IIM_MAC_ROW 5
+#define IIM0_SCC_KEY 11
+#define IIM1_SUID 1
#endif
/*
-* Clocks configuration
-*/
+ * I2C
+ */
+
+//#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+
+//#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+//#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+//#define CONFIG_I2C_CMD_TREE
+//#define CONFIG_I2C_MULTI_BUS 2
+//#define CONFIG_SYS_I2C_NOPROBES { }
+
+# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x00*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
+
+/*
+ * SPI
+ */
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
+
/*
- * PLL configuration
+ * RTC
+ */
+#define CONFIG_RTC_DS1374
+#define CONFIG_SYS_RTC_BUS_NUM 0
+//#define DEBUG_RTC
+
+/*
+ * Watchdog Config
+ */
+
+/*
+ * USB
+ */
+
+/*
+ * Clocks
+ */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+
+/*
+ * PLL
*
* 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
* |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
*/
-
#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
#undef CONFIG_MX27_CLK26 /* there is no external 26MHz external clock */
@@ -362,15 +518,8 @@
#define CONFIG_USB_FREQ 60 /* 60 MHz */
/*
- * SDRAM definition parameter
+ * SDRAM
*/
-#define PHYS_SDRAM_1 0xA0000000
-#define PHYS_SDRAM_2 0xB0000000
-
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
-
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 8)
/* micron 8MB */
#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
@@ -509,207 +658,10 @@
#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
#endif
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-/* lowlevel_linit copy U-Boot at CONFIG_SYS_INIT_SP_ADDR (here in RAM) */
-/* making u-boot runnable from flash and also RAM that is usefull to boot */
-/* from serial port and from flash with only one version of U-Boot */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xA1000000
-#endif
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
- + PHYS_SDRAM_1_SIZE - 0x0100000)
-
-/*
- * Configuration for no NOR FLASH memory
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#define CONFIG_NAND_MXC
-
-#define CONFIG_MXC_NAND_REGS_BASE (0xD8000000)
-#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-//#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_MTD_NAND_ECC_JFFS2
-
-//#define CONFIG_SYS_DIRECT_FLASH_TFTP 1
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define IMX27_NAND_16BITS 1
-#define NAND_MAX_CHIPS 1
-
-#define CONFIG_BOOT_TRACE_REG 0xAFFFFFF8 /* Addr to store traces of SPL boot */
-//#define NAND_ALLOW_ERASE_ALL
-//#define CONFIG_MTD_NAND_VERIFY_WRITE 1
-//#define CONFIG_SYS_NAND_SELECT_DEVICE 0 /* nand driver supports mutipl. chips */
-//#define CONFIG_SYS_NFC_DEBUG
-//#define CONFIG_MTD_DEBUG
-//#define CONFIG_MTD_DEBUG_VERBOSE 3
-
-/*=====================*/
-
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR /* Copy SPL+U-Boot here */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN /* Size is the partion size */
-
-/*
- * Environment setup. Definitions of monitor location and size with
- * definition of environment setup ends up in 2 possibilities.
- * 1. Embeded environment - in u-boot code is space for environment
- * 2. Environment is read from predefined sector of flash
- * Right now we support 2. possiblity, but expecting no env placed
- * on mentioned address right now. This also needs to provide whole
- * sector for it - for us 256Kb is really waste of memory. U-boot uses
- * default env. and until kernel parameters could be sent to kernel
- * env. has no sense to us.
- */
-
-#define CONFIG_SYS_MONITOR_BASE 0xAFF00000
-#define CONFIG_SYS_MONITOR_OFFSET 0x00000000
-#define CONFIG_SYS_MONITOR_LEN 0x000A0000 /* 640kB ( 5 flash blocks ) */
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_OFFSET 0x000A0000 /* NAND offset address for now*/
-#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
-#define CONFIG_ENV_RANGE 0X00060000 /* 384kB ( 3 flash blocks ) */
-#define CONFIG_ENV_OVERWRITE 1 /* env is writable now */
-#define CONFIG_FIRMWARE_OFFSET 0x00100000
-#define CONFIG_FIRMWARE_LEN 0x00080000 /* 512kB ( 4 flash blocks ) */
-#define CONFIG_KERNEL_OFFSET 0x00180000
-#define CONFIG_KERNEL_LEN 0x00500000 /* 5.0MB */
-#define CONFIG_ROOTFS_OFFSET 0x00680000
-#define CONFIG_ROOTFS_LEN /* entire flash if not specified ~116MB*/
-
-/*
- * Default load address for user programs and kernel
- */
-#define CONFIG_SYS_LOAD_ADDR 0xA0000000
-#define CONFIG_LOADADDR 0xA0000000
-#define CONFIG_SYS_TFTP_LOADADDR 0xA0000000
-
-/*
- * Partitions & Filsystems
- */
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_ISO_PARTITION
-#define CONFIG_SUPPORT_VFAT
-
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * JFFS2
- */
-#define CONFIG_JFFS2_NAND 1
-#define CONFIG_JFFS2_CMDLINE 1
-
-/*
- * This is setting for JFFS2 support in u-boot.
- * NOTE: Enable CONFIG_SYS_CMD_JFFS2 for JFFS2 support.
- */
-#define CONFIG_SYS_JFFS_CUSTOM_PART
-
/*
- * UBIFS
+ * External interface
*/
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
/*
- * Hardware drivers
- */
-
-/* FEC IMX27 ethernet chipset */
-#define CONFIG_FEC_MXC
-#undef CONFIG_FEC_IMX27_DEBUG
-
-#define CONFIG_NET_MULTI
-#define CONFIG_FEC_MXC_PHYADDR 0x1f
-#define CONFIG_MII 1 /* MII PHY management */
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
-//#define FPGA_DEBUG
-#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
-#define CONFIG_SYS_FPGA_WAIT 20000 /* 20 ms */
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_CHECK_CTRLC
-#define CONFIG_SYS_FPGA_CHECK_ERROR
-//#define CONFIG_SYS_FPGA_IS_PROTO /* to be defined with apf27 board prototype*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */
-#define CONFIG_SYS_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */
-#define CONFIG_SYS_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */
-#define CONFIG_SYS_FPGA_RDATA 0xD6000000 /* FPGA data addr */
-#define CONFIG_SYS_FPGA_WDATA 0xD6000000 /* FPGA data addr */
-#define CONFIG_SYS_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
-#define CONFIG_SYS_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */
-#define CONFIG_SYS_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
-#define CONFIG_SYS_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
-#define CONFIG_SYS_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
-#define CONFIG_SYS_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
-
-/*
- * I2C bus
- */
-
-//#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-
-//#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-//#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-//#define CONFIG_I2C_CMD_TREE
-//#define CONFIG_I2C_MULTI_BUS 2
-//#define CONFIG_SYS_I2C_NOPROBES { }
-
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x00*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
-
-/*
- * RTC
- */
-#define CONFIG_RTC_DS1374
-#define CONFIG_SYS_RTC_BUS_NUM 0
-//#define DEBUG_RTC
-
-/*
- * SD/MMC
- */
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
-#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
-
-/**
- * IIM fuse Config
- */
-
-#ifdef CONFIG_CMD_IMX_FUSE
-#define IIM_MAC_BANK 0
-#define IIM_MAC_ROW 5
-#define IIM0_SCC_KEY 11
-#define IIM1_SUID 1
-#endif /*CONFIG_CMD_IMX_FUSE */
-
-/*
- * External interfaces module
- *
* CSCRxU_VAL:
* 31| x | x | x x |x x x x| x x | x | x |x x x x|16
* |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL |
@@ -868,7 +820,7 @@
#define CONFIG_SYS_GPCR_VAL 0x0003000F
/* LPDDR enable. latency hiding behavior enabled */
-//#define CONFIG_SYS_ESDMISC_VAL ESDMISC_MA10_SHARE+ESDMISC_MDDREN
+//#define CONFIG_SYS_ESDMISC_VAL ESDMISC_MA10_SHARE+ESDMISC_MDDREN
/*
* safe value in case of erratic crash during boot
* (seen with some prototype boards)*/
@@ -890,9 +842,6 @@
#define CONFIG_SYS_PCCR0_VAL 0x05070400
#define CONFIG_SYS_PCCR1_VAL 0xA14A0408
-/* CONFIG_SKIP_LOWLEVEL_INIT bypass lowlevel init in bootstrap mode */
-#undef CONFIG_SKIP_LOWLEVEL_INIT
-
/*
* From here, there should not be any user configuration.
* All Equations are automatic
diff --git a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h
index a18a099..20060f6 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h
@@ -1,9 +1,7 @@
/*
- * Configuration settings for the Armadeus Project apf28 board.
+ * Configuration settings for the Armadeus Project motherboard APF28.
*
- * Copyright (C) 2011-2012 Eric Jarrige, Armadeus Project
- * Copyright (C) 2011 Marek Vasut <mar...@gm...>
- * on behalf of DENX Software Engineering GmbH
+ * Copyright (C) 2011-2012 ej / Armadeus Project <eri...@ar...>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -20,34 +18,39 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef __APF28_H__
-#define __APF28_H__
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
#include <asm/arch/regs-base.h>
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "0.5"
+#define CONFIG_ENV_VERSION "0.6"
#define CONFIG_IDENT_STRING " apf28 patch 0.7"
+#define CONFIG_BOARD_NAME apf28
/*
* SoC configurations
*/
-#define CONFIG_MX28 /* i.MX28 SoC */
-#define CONFIG_MXS_GPIO /* GPIO control */
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_MX28 /* i.MX28 SoC */
+#define CONFIG_MACH_TYPE 3845 /* APF9328 */
/*
- * Define APF28 machine type by hand until it lands in mach-types
+ * Enable the call to miscellaneous platform dependent initialization.
*/
-#define CONFIG_MACH_TYPE 3845
-
-#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_ARCH_MISC_INIT
/*
+ * Board display option
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+/*
* SPL
*/
#define CONFIG_SPL
@@ -65,38 +68,39 @@
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOARD_NAME apf28
-#define CONFIG_HOSTNAME "apf28"
+#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
#define CONFIG_SRV_PATH ""
-#define CONFIG_ROOTPATH "/tftpboot/apf28-root"
+#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root"
/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_ASKENV /* ask for env variable */
+#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DNS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NET
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_USB
-
-#define CONFIG_CMD_ASKENV /* ask for env variable */
-#define CONFIG_CMD_BSP /* Board Specific functions */
-#define CONFIG_CMD_NAND_LOCK_UNLOCK
-#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
/*
* Memory configurations
@@ -104,12 +108,12 @@
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MiB RAM */
-#define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+/*#define CONFIG_STACKSIZE 0x00010000*//* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00002000
@@ -118,11 +122,7 @@
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/*
- * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
- * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
- * binary. In case there was more of this mess, 0x100 bytes are skipped.
- */
+
#define CONFIG_SYS_TEXT_BASE 0x44000000
/*
@@ -144,66 +144,6 @@
#define CONFIG_ROOTFS_OFFSET 0x00C00000
#define CONFIG_ROOTFS_LEN /* entire flash if not specified */
-/*
- * U-Boot general configurations
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "BIOS> "
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
- /* Print buffer size */
-#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* Boot argument buffer size */
-#define CONFIG_AUTO_COMPLETE /* Command auto complete */
-#define CONFIG_CMDLINE_EDITING /* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-/*
- * Serial Driver
- */
-#define CONFIG_PL011_SERIAL
-#define CONFIG_PL011_CLOCK 24000000
-#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
-#define CONFIG_CONS_INDEX 0
-#define CONFIG_BAUDRATE 115200 /* Default baud rate */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-
-/*
- * MMC Driver
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXS_MMC
-#endif
-
-/*
- * NAND
- */
-#ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_MXS
-#define CONFIG_APBH_DMA
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x60000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define NAND_MAX_CHIPS 1
-
-/* Environment is in NAND */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTDMAP "gpmi-nfc-main"
#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
#define MTDPARTS_DEFAULT \
@@ -213,77 +153,34 @@
"512K(redundant-environment)," \
"8M(kernel)," \
"-(rootfs)"
-#endif
-
-/*
- * Ethernet on SOC (FEC)
- */
-#ifdef CONFIG_CMD_NET
-#define CONFIG_NET_MULTI
-#define CONFIG_ETHPRIME "FEC0"
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_MULTI
-#define CONFIG_MII
-#define CONFIG_DISCOVER_PHY
-#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_M28_FEC_MAC_IN_OCOTP
-#define CONFIG_NETCONSOLE 1
-#endif
-#define ACFG_OUI 0x001EAC
/*
- * I2C
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MXS
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 400000
-#endif
-
-/*
- * RTC
- */
-#ifdef CONFIG_CMD_DATE
-/* Use the internal RTC in the MXS chip */
-#define CONFIG_RTC_INTERNAL
-#define CONFIG_RTC_MXS
-#endif
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MXS
-#define CONFIG_EHCI_MXS_PORT 1
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_STORAGE
-#endif
-
-/*
- * SPI
- */
-#ifdef CONFIG_CMD_SPI
-#define CONFIG_HARD_SPI
-#define CONFIG_MXS_SPI
-#define CONFIG_SPI_HALF_DUPLEX
-#define CONFIG_DEFAULT_SPI_BUS 2
-#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
-#endif
-
-/*
- * OCOTP
+ * U-Boot general configurations
*/
-
-/*#define CONFIG_IMX_OCOTP*/
-#define IMX_OCOTP_BASE MXS_OCOTP_BASE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "BIOS> "
+#define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
/*
* Boot Linux
*/
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG /* send initrd params */
+/*
+#define CONFIG_REVISION_TAG
+#define CONFIG_OF_LIBFDT
+*/
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
@@ -293,14 +190,18 @@
#define CONFIG_CONSOLE "console=ttyAM0,"MK_STR(CONFIG_BAUDRATE)
#define CONFIG_BOOTCOMMAND "run ubifsboot"
#define CONFIG_SYS_AUTOLOAD "no"
-#define CONFIG_LOADADDR 0x40000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_LOADADDR 0x40000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_TFTP_LOADADDR CONFIG_LOADADDR
/*
* Extra Environments
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
- "env_version=" CONFIG_ENV_VERSION "\0" \
+ "env_version=" CONFIG_ENV_VERSION "\0" \
"console=" CONFIG_CONSOLE "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"partition=nand0,4\0" \
@@ -369,5 +270,136 @@
"update_all=run download_kernel flash_kernel download_rootfs " \
"flash_rootfs download_uboot flash_uboot\0"
+/*
+ * Serial Driver
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK 24000000
+#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_BAUDRATE 115200 /* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * GPIO
+ */
+#define CONFIG_MXS_GPIO
+
+/*
+ * NOR
+ */
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXS
+#define CONFIG_APBH_DMA
+#define CONFIG_SYS_NAND_BASE 0x60000000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define NAND_MAX_CHIPS 1
+
+/*#define CONFIG_SYS_DIRECT_FLASH_TFTP*/
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define CONFIG_SYS_NAND_QUIET 1
+
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Partitions & Filsystems
+ */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * UBIFS
+ */
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/*
+ * Ethernet (on SOC mx28 FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_MULTI
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE RMII
+#define CONFIG_M28_FEC_MAC_IN_OCOTP
+#define CONFIG_NETCONSOLE 1
+#endif
+#define ACFG_OUI 0x001EAC
+
+/*
+ * Fuses - OCOTP
+ */
+/*#define CONFIG_IMX_OCOTP*/
+#define IMX_OCOTP_BASE MXS_OCOTP_BASE
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 400000
+#endif
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_HARD_SPI
+#define CONFIG_MXS_SPI
+#define CONFIG_SPI_HALF_DUPLEX
+#define CONFIG_DEFAULT_SPI_BUS 2
+#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
+#endif
+
+/*
+ * SD/MMC
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXS_MMC
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+/* Use the internal RTC in the MXS chip */
+#define CONFIG_RTC_INTERNAL
+#define CONFIG_RTC_MXS
+#endif
+
+/*
+ * Watchdog Config
+ */
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MXS
+#define CONFIG_EHCI_MXS_PORT 1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * Clocks
+ */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
-#endif /* __APF28_H__ */
+#endif /* __CONFIG_H */
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
index 3930e2d..2f5f8d8 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
@@ -1,8 +1,8 @@
/*
*
- * Configuration settings for the Armadeus Project apf51 board.
+ * Configuration settings for the Armadeus Project motherboard APF51
*
- * (C) Copyright 2010-2012 Eric Jarrige, Armadeus Project
+ * Copyright (C) 2010-2012 ej / Armadeus Project <eri...@ar...>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -18,53 +18,136 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
- *
- * 2010/03/31 Initial version based on apf27 configuration file
- * 2011/05/02 patch V0.5 updates NAND OOB to be mx51 linux kernel compliant
- * (at least for the first 11 spare bytes..)
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "0.7"
-#define CONFIG_IDENT_STRING " apf51 patch 0.9"
+#define CONFIG_ENV_VERSION "0.8"
+#define CONFIG_IDENT_STRING " apf51 patch 0.10"
+#define CONFIG_BOARD_NAME apf51
/*
- * High Level Configuration Options
- * (easy to change)
+ * SoC configurations
*/
-
#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU */
#define CONFIG_MX51 /* in a Freescale i.MX51 Chip */
-#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
#define CONFIG_MACH_TYPE 2795 /* APF51 */
+/*
+ * Enable the call to miscellaneous platform dependent initialization.
+ */
+#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * Board display option
+ */
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_SYS_TEXT_BASE 0x97000000
+/*
+ * SPL
+ */
+#ifndef CONFIG_DOWNLOAD_BY_DEBUGGER
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+#endif
+
+#define CONFIG_NAND_U_BOOT
+/* APF Copy SPL+U-Boot here */
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR
+/* APF Size is the partion size */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
/*
- * Select serial console configuration
+ * BOOTP options
*/
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE UART3_BASE
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+/*
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+*/
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.10
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+
+#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
+#define CONFIG_SRV_PATH ""
+#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root"
/*
- * Boot options. Setting delay to -1 stops autostart count down.
+ * U-Boot Commands
*/
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_ZERO_BOOTDELAY_CHECK
+#include <config_cmd_default.h>
-#define CONFIG_BOOTARGS \
- CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=ubifs " MTDPARTS_DEFAULT
+#define CONFIG_CMD_ASKENV /* ask for env variable */
+#define CONFIG_CMD_BSP /* Board Specific functions */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_DHCP /* DHCP Support */
+/*#define CONFIG_CMD_DNS*/
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_IIM /* imx iim fuse */
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING /* ping support */
+/*#define CONFIG_CMD_SAVES*/ /* save S record dump */
+/*#define CONFIG_CMD_SETEXPR*/ /* setexpr support */
+/*#define CONFIG_CMD_UBI*/
+/*#define CONFIG_CMD_UBIFS*/
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_NR_DRAM_POPULATED 1
+#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR /* SDRAM bank #1 */
+#define PHYS_SDRAM_SIZE 256
+#define PHYS_SDRAM_1_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
+#define PHYS_SDRAM_2_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 * 1024 * 1024) )
+#define CONFIG_SYS_MEMTEST_START 0x90000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x90100000 /* 1st MiB in DRAM */
+
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_TEXT_BASE 0x97000000
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_MONITOR_OFFSET 0x00000000 /* offset in NAND */
+#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MB */
+#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
+#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
+#define CONFIG_ENV_RANGE 0x00100000 /* 1MB */
+#define CONFIG_FIRMWARE_OFFSET 0x00200000
+#define CONFIG_FIRMWARE_LEN 0x00100000 /* 1MB */
+#define CONFIG_KERNEL_OFFSET 0x00300000
+#define CONFIG_KERNEL_LEN 0x00800000 /* 8MB (BB ready) */
+#define CONFIG_ROOTFS_OFFSET 0x00B00000
+#define CONFIG_ROOTFS_LEN /* entire flash if not specified */
-#define CONFIG_CONSOLE "console=ttymxc2,"MK_STR(CONFIG_BAUDRATE)
#define CONFIG_MTDMAP "mxc_nand"
#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP ":1M(U-boot)ro," \
@@ -72,6 +155,53 @@
"8M(kernel)," \
"-(rootfs)"
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
+#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 16 /* max command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG /* send initrd params */
+/*
+#define CONFIG_REVISION_TAG
+#define CONFIG_OF_LIBFDT
+*/
+
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_BOOTFILE "${board_name}-linux.bin"
+#define CONFIG_BOOTARGS \
+ CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=ubifs " MTDPARTS_DEFAULT
+
+#define CONFIG_CONSOLE "console=ttymxc2,"MK_STR(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run ubifsboot"
+#define CONFIG_SYS_AUTOLOAD "no"
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_LOADADDR 0x90000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_TFTP_LOADADDR CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
#define CONFIG_EXTRA_ENV_SETTINGS \
"env_version=" CONFIG_ENV_VERSION "\0" \
"fileaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
@@ -94,7 +224,6 @@
"ntpserverip=217.147.208.1\0" \
"mmcroot=/dev/mmcblk0p1\0" \
"mmcrootfstype=ext2\0" \
- "quiet=1\0" \
"addnfsargs=setenv bootargs ${bootargs} " \
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"addubifsargs=setenv bootargs ${bootargs} " \
@@ -140,8 +269,7 @@
"then echo Flashing of rootfs succeed;" \
"else echo Flashing of rootfs failed;" \
"fi\0" \
- "flash_reset_env=nand unlock ${env_offset} ${env_len};" \
- "nand erase ${env_offset} ${env_len};" \
+ "flash_reset_env=env default -f; saveenv;" \
"echo Flash environment variables erased!\0" \
"download_uboot=tftpboot ${loadaddr} " \
" ${serverpath}${board_name}-u-boot.bin\0" \
@@ -154,260 +282,65 @@
"update_rootfs=run download_rootfs flash_rootfs\0" \
"update_all=run download_kernel flash_kernel download_rootfs " \
"flash_rootfs download_uboot flash_uboot\0" \
- "unlock_regs=mw 10000008 0; mw 10020008 0;TODO\0"
-
-#define CONFIG_BOOTCOMMAND "run ubifsboot"
-
-#define CONFIG_SYS_AUTOLOAD "no"
+ "unlock_regs=echo unlock_reg not needed anymore\0"
/*
- * BOOTP options
+ * Serial Driver
*/
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-*/
-
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_IPADDR 192.168.0.10
-#define CONFIG_BOARD_NAME "apf51"
-#define CONFIG_HOSTNAME "apf51"
-#define CONFIG_GATEWAYIP 192.168.0.1
-#define CONFIG_SERVERIP 192.168.0.2
-#define CONFIG_SRV_PATH ""
-#define CONFIG_ROOTPATH "/tftpboot/apf51-root"
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV /* ask for env variable */
-#define CONFIG_CMD_BSP /* Board Specific functions */
-#define CONFIG_CMD_CACHE /* icache, dcache */
-#define CONFIG_CMD_DHCP /* DHCP Support */
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_IIM /* imx iim fuse */
-#undef CONFIG_CMD_IMLS /* List all found images */
-#define CONFIG_CMD_MTDPARTS /* MTD partition support */
-#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_NAND_LOCK_UNLOCK
-#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING /* ping support */
-
-/*
- * Select some advanced features of the commande line parser
- */
-
-#define CONFIG_BOOT_PARAMS_ADDR 0x90000100
-
-/**
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
-#define CONFIG_AUTO_COMPLETE /* Enable auto completion of */
- /* commands using TAB */
-
-#define CONFIG_SYS_CBSIZE 1024 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* boot args buf size */
-
-#define CONFIG_SYS_MEMTEST_START 0x90000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x90100000 /* 1st MiB in DRAM */
-
-/*
- * Default load address for user programs and kernel
- */
-#define CONFIG_SYS_LOAD_ADDR 0x90000000
-#define CONFIG_LOADADDR 0x90000000
-
-#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1 ms */
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/*
- * Malloc pool need to host env. + 2 MB reserve for other allocations.
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 * 1024 * 1024) )
-
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE (128<<10) /* stack size */
-#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
-#endif
-
-/*
- * CPU Flash boot constants
- */
-#ifndef CONFIG_DOWNLOAD_BY_DEBUGGER
-#define CONFIG_FLASH_HEADER
-#define CONFIG_FLASH_HEADER_OFFSET 0x400
-#define CONFIG_FLASH_HEADER_BARKER 0xB1
-#endif
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART3_BASE
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_BAUDRATE 115200
/*
- * Enable the call to miscellaneous platform dependent initialization.
+ * GPIO
*/
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
/*
- * Definitions related to passing arguments to kernel.
- */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-/*
-#define CONFIG_REVISION_TAG
-#define CONFIG_OF_LIBFDT
-*/
-/*
- * SDRAM Configs
+ * NOR
*/
-#define CONFIG_NR_DRAM_BANKS 2
-#define CONFIG_NR_DRAM_POPULATED 1
-#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR /* SDRAM bank #1 */
-#define PHYS_SDRAM_SIZE 256
-#define PHYS_SDRAM_1_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
-#define PHYS_SDRAM_2_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
/*
- * FLASH organization
- */
-#define CONFIG_SYS_MONITOR_OFFSET 0x00000000 /* offset in NAND */
-#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
-#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
-#define CONFIG_ENV_RANGE 0x00100000 /* 1MB */
-#define CONFIG_ENV_OVERWRITE /* env is writable now */
-#define CONFIG_FIRMWARE_OFFSET 0x00200000
-#define CONFIG_FIRMWARE_LEN 0x00100000 /* 1MB */
-#define CONFIG_KERNEL_OFFSET 0x00300000
-#define CONFIG_KERNEL_LEN 0x00800000 /* 8MB (BB ready) */
-#define CONFIG_ROOTFS_OFFSET 0x00B00000
-#define CONFIG_ROOTFS_LEN /* entire flash if not specified */
-
-/*
- * Configuration for no NOR FLASH memory
- */
-#define CONFIG_SYS_NO_FLASH
-
-/*=====================*/
-/* Flash & Environment */
-/*=====================*/
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-
-/*-----------------------------------------------------------------------
- * NAND FLASH driver setup
+ * NAND
*/
#define CONFIG_NAND_MXC_V2
#define CONFIG_MXC_NAND_REGS_BASE 0xCFFF0000
#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
#define CONFIG_SYS_MAX_NAND_DEVICE 1
+
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
-/*#define CONFIG_MTD_NAND_VERIFY_WRITE*/
+#define NAND_MAX_CHIPS 1
/*#define CONFIG_SYS_DIRECT_FLASH_TFTP*/
#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define NAND_MAX_CHIPS 1
-
-/*=====================*/
+#define CONFIG_SYS_NAND_QUIET 1
-#define CONFIG_NAND_U_BOOT
-/* Copy SPL+U-Boot here */
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR
-/* Size is the partion size */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
-/*
-#define CONFIG_NAND_ENV_DST
-#define CONFIG_ENV_OFFSET_REDUND
-*/
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OVERWRITE /* env is writable now */
/*
* Partitions & Filsystems
*/
-#undef CONFIG_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
-
-/**
- * I2C Configs
- */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MXC 1
-#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_MX51_PORT2
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0xfe
-
-/**
- * RTC PMIC TODO TODO TODO TODO
- */
-
/*
- * SD/MMC Configs
- */
-
-/**
- * SPI Configs
- */
-
-/**
- * Watchdog Config
- */
-
-#define CONFIG_HW_WATCHDOG
-
-/**
- * IIM fuse Config
- */
-
-#define CONFIG_IMX_IIM
-#define CONFIG_IIM_MAC_BANK 1
-#define CONFIG_IIM_MAC_ROW 9
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+*/
-/**
- * GPIO: Support for MXC GPIO
+/*
+ * UBIFS
*/
+/*
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+*/
-#define CONFIG_MXC_GPIO
-
-/**
- * Ethernet: Support for internal Fast Ethernet Controller
+/*
+ * Ethernet (on SOC mx51 FEC)
*/
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
@@ -421,7 +354,6 @@
* FPGA
*/
#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
-/*#define FPGA_DEBUG*/
#define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
@@ -449,11 +381,50 @@
#define ACFG_FPGA_WCR2_VALUE 0x00000000
/*
-* Clocks configuration
-*/
+ * Fuses - IIM
+ */
+
+#define CONFIG_IMX_IIM
+#define CONFIG_IIM_MAC_BANK 1
+#define CONFIG_IIM_MAC_ROW 9
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_MX51_PORT2
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+/*
+ * SPI
+ */
+
+/*
+ * SD/MMC
+ */
+
+/*
+ * RTC
+ */
+
+/*
+ * Watchdog Config
+ */
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * USB
+ */
-#define CONFIG_SYS_MX5_CLK32 32768
-#define CONFIG_SYS_MX5_HCLK 1024*CONFIG_SYS_MX5_CLK32
+/*
+ * Clocks
+ */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
+#define CONFIG_SYS_MX5_CLK32 32768
+#define CONFIG_SYS_MX5_HCLK 1024*CONFIG_SYS_MX5_CLK32
#define CONFIG_MX51_PLL_ERRATA
/* external bus frequencies */
@@ -484,10 +455,6 @@
//#define APF_LPSR_CLK 0 /* MHz */
#define APF_PGC_CLK 66 /* MHz 66.5 MHz */
-/**
- * iMX51 PLL constants
- */
-
/* PLL parameters assuming 32.768kHz *1024 input clock with doubler ON */
/* MFI PDF */
#define DP_OP_864 ((11 << 4) + ((2 - 1) << 0))
@@ -514,83 +481,12 @@
#define DP_MFD_216 (262144 - 1)
#define DP_MFN_216 12223
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-
#define CONFIG_SYS_DDR_CLKSEL 0
/*
- * Hardware drivers
+ * SDRAM
*/
-
-/*-----------------------------------------------------------------------
- * WEIM - EIM
- */
- /* force BCLK free run */
-#define ACFG_WCR_VALUE 0x00000021
-#define ACFG_WIAR_VALUE 0x00000010
-
-/* CS1 */
-#define ACFG_CS1GCR1_VALUE ACFG_FPGA_GCR1_VALUE
-#define ACFG_CS1GCR2_VALUE ACFG_FPGA_GCR2_VALUE
-
-#define ACFG_CS1RCR1_VALUE ACFG_FPGA_RCR1_VALUE
-#define ACFG_CS1RCR2_VALUE ACFG_FPGA_RCR2_VALUE
-
-#define ACFG_CS1WCR1_VALUE ACFG_FPGA_WCR1_VALUE
-#define ACFG_CS1WCR2_VALUE ACFG_FPGA_WCR2_VALUE
-
-/* CS2 */
-#define ACFG_CS2GCR1_VALUE 0x00010080
-#define ACFG_CS2GCR2_VALUE 0x00000000
-
-#define ACFG_CS2RCR1_VALUE 0x00000000
-#define ACFG_CS2RCR2_VALUE 0x00000000
-
-#define ACFG_CS2WCR1_VALUE 0x00000000
-#define ACFG_CS2WCR2_VALUE 0x00000000
-
-/* CS3 */
-#define ACFG_CS3GCR1_VALUE 0x00010080
-#define ACFG_CS3GCR2_VALUE 0x00000000
-
-#define ACFG_CS3RCR1_VALUE 0x00000000
-#define ACFG_CS3RCR2_VALUE 0x00000000
-
-#define ACFG_CS3WCR1_VALUE 0x00000000
-#define ACFG_CS3WCR2_VALUE 0x00000000
-
-/* CS4 */
-#define ACFG_CS4GCR1_VALUE 0x00010080
-#define ACFG_CS4GCR2_VALUE 0x00000000
-
-#define ACFG_CS4RCR1_VALUE 0x00000000
-#define ACFG_CS4RCR2_VALUE 0x00000000
-
-#define ACFG_CS4WCR1_VALUE 0x00000000
-#define ACFG_CS4WCR2_VALUE 0x00000000
-
-/* CS5 */
-#define ACFG_CS5GCR1_VALUE 0x00010080
-#define ACFG_CS5GCR2_VALUE 0x00000000
-
-#define ACFG_CS5RCR1_VALUE 0x00000000
-#define ACFG_CS5RCR2_VALUE 0x00000000
-
-#define ACFG_CS5WCR1_VALUE 0x00000000
-#define ACFG_CS5WCR2_VALUE 0x00000000
-
-#include <asm/arch/imx-regs.h>
-
/*
- * From here, there should not be any user configuration.
- * All Equations are automatic
- */
-
-/**
- * SDRAM controler configs
- *
* ACFG_SDRAM_NUM_COL 8, 9, 10 or 11 column address bits
* ACFG_SDRAM_NUM_ROW 11, 12 or 13 row address bits
* ACFG_SDRAM_REFRESH 0=OFF 1=2048 2=4096 3=8192.. refresh
@@ -611,7 +507,6 @@
* ACFG_SDRAM_SINGLE_ACCESS 1= single access; 0 = Burst mode
*
*/
-
#if (PHYS_SDRAM_SIZE == 64) /* micron MT46H16M32LF -6 */
/* micron 64MB */
#define ACFG_SDRAM_NUM_COL 9 /* 8..11 column address bits */
@@ -678,6 +573,69 @@
#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 0..1 */
#endif
+/*
+ * External interface
+ */
+ /* force BCLK free run */
+#define ACFG_WCR_VALUE 0x00000021
+#define ACFG_WIAR_VALUE 0x00000010
+
+/* CS1 */
+#define ACFG_CS1GCR1_VALUE ACFG_FPGA_GCR1_VALUE
+#define ACFG_CS1GCR2_VALUE ACFG_FPGA_GCR2_VALUE
+
+#define ACFG_CS1RCR1_VALUE ACFG_FPGA_RCR1_VALUE
+#define ACFG_CS1RCR2_VALUE ACFG_FPGA_RCR2_VALUE
+
+#define ACFG_CS1WCR1_VALUE ACFG_FPGA_WCR1_VALUE
+#define ACFG_CS1WCR2_VALUE ACFG_FPGA_WCR2_VALUE
+
+/* CS2 */
+#define ACFG_CS2GCR1_VALUE 0x00010080
+#define ACFG_CS2GCR2_VALUE 0x00000000
+
+#define ACFG_CS2RCR1_VALUE 0x00000000
+#define ACFG_CS2RCR2_VALUE 0x00000000
+
+#define ACFG_CS2WCR1_VALUE 0x00000000
+#define ACFG_CS2WCR2_VALUE 0x00000000
+
+/* CS3 */
+#define ACFG_CS3GCR1_VALUE 0x00010080
+#define ACFG_CS3GCR2_VALUE 0x00000000
+
+#define ACFG_CS3RCR1_VALUE 0x00000000
+#define ACFG_CS3RCR2_VALUE 0x00000000
+
+#define ACFG_CS3WCR1_VALUE 0x00000000
+#define ACFG_CS3WCR2_VALUE 0x00000000
+
+/* CS4 */
+#define ACFG_CS4GCR1_VALUE 0x00010080
+#define ACFG_CS4GCR2_VALUE 0x00000000
+
+#define ACFG_CS4RCR1_VALUE 0x00000000
+#define ACFG_CS4RCR2_VALUE 0x000...
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