[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-178-g2adca38
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-178-g2adca38
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From: jorasse <jo...@us...> - 2012-03-20 13:04:59
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 2adca3896e79a4ffe437f2a04a8162e51ea87045 (commit)
from ea1a9356432018629f5f43b6932f963403335446 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2adca3896e79a4ffe437f2a04a8162e51ea87045
Author: Eric Jarrige <eri...@ar...>
Date: Tue Mar 20 14:15:31 2012 +0100
[UBOOT] apf27: board refactoring and fix nand issue with UBoot 2011.12
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf27/apf27-u-boot-2011.12.h | 76 +++++++----------
...-Add-support-for-the-armadeus-apf27-board.patch | 93 +++++++++++++-------
patches/u-boot/2011.12/310-apf27-nand-spl.patch | 16 ++--
3 files changed, 99 insertions(+), 86 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
index 148e345..a74d14a 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
@@ -31,8 +31,8 @@
#define __CONFIG_H
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "2.0"
-#define CONFIG_IDENT_STRING " apf27 patch 2.7"
+#define CONFIG_ENV_VERSION "2.1"
+#define CONFIG_IDENT_STRING " apf27 patch 2.8"
#define CONFIG_ARM926EJS 1 /* this is an ARM926EJS CPU */
#define CONFIG_MX27 1 /* in a Freescale i.MX27 Chip */
@@ -88,13 +88,13 @@
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
//#define CONFIG_CMD_I2C /* I2C serial bus support */
#undef CONFIG_CMD_IMLS /* List all found images */
-#define CONFIG_CMD_IMMAP /* IMMR dump support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_CMD_MTDPARTS /* MTD partition support */
#define CONFIG_CMD_MMC /* MMC memory mapped support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_CMD_PING /* ping support */
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SETEXPR /* setexpr support */
@@ -120,11 +120,11 @@
/*
* Boot options. Setting delay to -1 stops autostart count down.
*/
-#define CONFIG_BOOTDELAY 20
+#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTARGS \
- CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=jffs2 " MTDPARTS_DEFAULT
+ CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=ubifs " MTDPARTS_DEFAULT
#define CONFIG_CONSOLE "console=ttySMX0,"MK_STR(CONFIG_BAUDRATE)
#define CONFIG_MTDMAP "mxc_nand.0"
@@ -159,8 +159,6 @@
"quiet=1\0" \
"addnfsargs=setenv bootargs ${bootargs} " \
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
- "addjffsargs=setenv bootargs ${bootargs} " \
- "root=/dev/mtdblock4 rootfstype=jffs2\0" \
"addubifsargs=setenv bootargs ${bootargs} " \
"ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
"addmmcargs=setenv bootargs ${bootargs} " \
@@ -169,26 +167,23 @@
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off \0"\
"nfsboot=setenv bootargs ${console} ${mtdparts};" \
"run addnfsargs addipargs; setenv autostart yes;" \
- "nboot.jffs2 A0000000 0 ${kernel_offset}\0" \
- "jffsboot=setenv bootargs ${console} ${mtdparts};" \
- "run addjffsargs addipargs; setenv autostart yes;" \
- "nboot.jffs2 A0000000 0 ${kernel_offset}\0" \
+ "nboot A0000000 0 ${kernel_offset}\0" \
"ubifsboot=setenv bootargs ${console} ${mtdparts};" \
"run addubifsargs addipargs; setenv autostart yes;" \
- "nboot.jffs2 A0000000 0 ${kernel_offset}\0" \
+ "nboot A0000000 0 ${kernel_offset}\0" \
"mmcboot=setenv bootargs ${console} ${mtdparts};" \
"run addmmcargs addipargs; setenv autostart yes;" \
- "nboot.jffs2 A0000000 0 ${kernel_offset}\0" \
+ "nboot A0000000 0 ${kernel_offset}\0" \
"firmware_autoload=0\0" \
"flash_uboot=nand unlock ${uboot_offset} ${uboot_len};" \
"nand erase ${uboot_offset} ${uboot_len};" \
- "if nand write.jffs2 ${fileaddr} ${uboot_offset} ${filesize};" \
+ "if nand write.trimffs ${fileaddr} ${uboot_offset} ${filesize};" \
"then nand lock; nand unlock ${env_offset};" \
"echo Flashing of uboot succeed;" \
"else echo Flashing of uboot failed;" \
"fi; \0" \
"flash_firmware=nand erase ${firmware_offset} ${firmware_len};"\
- "if nand write.jffs2 ${fileaddr} ${firmware_offset} ${filesize} ;"\
+ "if nand write.trimffs ${fileaddr} ${firmware_offset} ${filesize} ;"\
"then echo Flashing of Firmware succeed;" \
"else echo Flashing of Firmware failed;" \
"fi\0" \
@@ -196,12 +191,12 @@
"run flash_firmware;"\
"fpga load 0 ${fileaddr} ${firmware_len};\0"\
"flash_kernel=nand erase ${kernel_offset} ${kernel_len};" \
- "if nand write.jffs2 ${fileaddr} ${kernel_offset} ${filesize} ;"\
+ "if nand write.trimffs ${fileaddr} ${kernel_offset} ${filesize} ;"\
"then echo Flashing of kernel succeed;" \
"else echo Flashing of kernel failed;" \
"fi\0" \
- "flash_rootfs=nand erase clean ${rootfs_offset} ${rootfs_len};" \
- "if nand write.jffs2 ${fileaddr} ${rootfs_offset} ${filesize};"\
+ "flash_rootfs=nand erase.part rootfs;" \
+ "if nand write.trimffs ${fileaddr} ${rootfs_offset} ${filesize};"\
"then echo Flashing of rootfs succeed;" \
"else echo Flashing of rootfs failed;" \
"fi\0" \
@@ -225,7 +220,7 @@
#define CFG_AUTOLOAD "no"
#define CFG_DIRECT_FLASH_TFTP
-#define CONFIG_MACH_TYPE MACH_TYPE_APF27
+#define CONFIG_MACH_TYPE 1698
#define CONFIG_BOOT_PARAMS_ADDR 0xa0000100
#undef CONFIG_SHOW_BOOT_PROGRESS
@@ -357,16 +352,17 @@
/*
* SDRAM definition parameter
*/
+#define PHYS_SDRAM_1 0xA0000000
+#define PHYS_SDRAM_2 0xB0000000
+
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 8)
/* micron 8MB */
-#define CONFIG_SYS_SDRAM_1_BASE 0xA0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
-#define CONFIG_SYS_SDRAM_2_BASE 0xB0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
+#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
+#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 8 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 11 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -388,10 +384,8 @@
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 16)
/* micron 16MB */
-#define CONFIG_SYS_SDRAM_1_BASE 0xA0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-#define CONFIG_SYS_SDRAM_2_BASE 0xB0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */
+#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
+#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 8 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 12 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -413,10 +407,8 @@
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 32)
/* micron 32MB */
-#define CONFIG_SYS_SDRAM_1_BASE 0xA0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-#define CONFIG_SYS_SDRAM_2_BASE 0xB0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_2_SIZE 0x02000000 /* 32 MB */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+#define PHYS_SDRAM_2_SIZE 0x02000000 /* 32 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 12 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -438,10 +430,8 @@
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
/* micron 64MB */
-#define CONFIG_SYS_SDRAM_1_BASE 0xA0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define CONFIG_SYS_SDRAM_2_BASE 0xB0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 13 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -463,10 +453,8 @@
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 128)
/* micron 128MB */
-#define CONFIG_SYS_SDRAM_1_BASE 0xA0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define CONFIG_SYS_SDRAM_2_BASE 0xB0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -488,10 +476,8 @@
#if (CONFIG_SYS_SDRAM_MBYTE_SYZE == 256)
/* micron 256MB */
-#define CONFIG_SYS_SDRAM_1_BASE 0xA0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
-#define CONFIG_SYS_SDRAM_2_BASE 0xB0000000 /* SDRAM bank #1 32bits */
-#define CONFIG_SYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
+#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
+#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
#define CONFIG_SYS_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
@@ -511,7 +497,7 @@
#define CONFIG_SYS_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
#endif
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_1_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* lowlevel_linit copy U-Boot at CONFIG_SYS_INIT_SP_ADDR (here in RAM) */
/* making u-boot runnable from flash and also RAM that is usefull to boot */
@@ -521,7 +507,7 @@
#endif
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
- + CONFIG_SYS_SDRAM_1_SIZE - 0x0100000)
+ + PHYS_SDRAM_1_SIZE - 0x0100000)
/*
* Configuration for no NOR FLASH memory
diff --git a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
index 577b8d1..ba99f40 100644
--- a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -79,7 +79,7 @@ new file mode 100644
index 0000000..e08b7a2
--- /dev/null
+++ b/board/armadeus/apf27/apf27.c
-@@ -0,0 +1,200 @@
+@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige <jo...@us...>
@@ -106,6 +106,7 @@ index 0000000..e08b7a2
+#include "fpga.h"
+#include <nand.h>
+#include <asm/arch/imx-regs.h>
++#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
@@ -176,12 +177,7 @@ index 0000000..e08b7a2
+int
+board_init (void)
+{
-+
-+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
-+
-+ /* On apf27 U-Boot is always in the relocatated stated */
-+ gd->flags |= GD_FLG_RELOC;
++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ apf27_devices_init();
+
@@ -192,27 +188,22 @@ index 0000000..e08b7a2
+dram_init (void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
-+ gd->ram_size = 0;
-+#if ( CONFIG_NR_DRAM_BANKS > 0 )
-+ gd->ram_size += get_ram_size((void *)CONFIG_SYS_SDRAM_1_BASE,
-+ CONFIG_SYS_SDRAM_1_SIZE);
-+#endif
++ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
++ PHYS_SDRAM_1_SIZE);
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
-+ gd->ram_size += get_ram_size((void *)CONFIG_SYS_SDRAM_2_BASE,
-+ CONFIG_SYS_SDRAM_2_SIZE);
++ gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
++ PHYS_SDRAM_2_SIZE);
+#endif
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
-+#if ( CONFIG_NR_DRAM_BANKS > 0 )
-+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_1_BASE;
-+ gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_1_SIZE;
-+#endif
++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++ gd->bd->bi_dram[0].size = gd->ram_size / CONFIG_NR_DRAM_BANKS;
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
-+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_2_BASE;
-+ gd->bd->bi_dram[1].size = CONFIG_SYS_SDRAM_2_SIZE;
++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
++ gd->bd->bi_dram[1].size = gd->ram_size -gd->bd->bi_dram[0].size;
+#endif
+}
+
@@ -280,6 +271,40 @@ index 0000000..e08b7a2
+ printf("Armadeus APF27\n");
+ return 0;
+}
++
++int board_eth_init(bd_t * bis)
++{
++#define STR_ENV_ETHADDR "ethaddr"
++ int rc = -ENODEV;
++
++#if defined(CONFIG_FEC_MXC)
++ struct eth_device *dev;
++ uchar eth_addr[6];
++
++ rc = fecmxc_initialize(bis);
++
++ if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
++ dev = eth_get_dev_by_index(0);
++ if (dev) {
++ eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
++ } else {
++ printf("FEC APF27: Couldn't get eth device\n");
++ rc = -1;
++ }
++ }
++#endif
++
++ return rc;
++}
++
++#ifndef CONFIG_SYS_DCACHE_OFF
++void enable_caches(void)
++{
++ /* Enable D-cache. I-cache is already enabled in start.S */
++ //dcache_enable();
++}
++
++#endif
diff --git a/board/armadeus/apf27/config.mk b/board/armadeus/apf27/config.mk
new file mode 100644
index 0000000..3354ba0
@@ -513,14 +538,14 @@ index 0000000..4d72d8c
+ str r1, [r0]
+
+ /* writeb(0xA0001000, any value) */
-+ ldr r1, =CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
+ ldrb r2, [r1]
+
+ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
+ str r1, [r0]
+
-+ ldr r4, =CONFIG_SYS_SDRAM_1_BASE /* CSD0 base address */
++ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
+
+ ldr r6,=0x7 /* load loop counter */
+1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
@@ -532,11 +557,11 @@ index 0000000..4d72d8c
+ str r1, [r0]
+
+ /* set standard mode register */
-+ ldr r4, = CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
+ ldrb r2, [r4]
+
+ /* set extended mode register */
-+ ldr r4, =CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++ ldr r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r5, [r4]
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
@@ -553,14 +578,14 @@ index 0000000..4d72d8c
+ str r1, [r0]
+
+ /* writeb(0xB0001000, any value) */
-+ ldr r1, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
+ ldrb r2, [r1]
+
+ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
+ str r1, [r0]
+
-+ ldr r4, =CONFIG_SYS_SDRAM_2_BASE /* CSD1 base address */
++ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
+
+ ldr r6,=0x7 /* load loop counter */
+1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
@@ -572,11 +597,11 @@ index 0000000..4d72d8c
+ str r1, [r0]
+
+ /* set standard mode register */
-+ ldr r4, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
+ ldrb r2, [r4]
+
+ /* set extended mode register */
-+ ldr r4, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r2, [r4]
+
+ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
@@ -749,7 +774,7 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ u-boot-2010.03/board/armadeus/apf27/fpga.c 2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,267 @@
+@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2002-2008
+ * Eric Jarrige <eri...@ar...>
@@ -1006,12 +1031,14 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
+ }
+
+ if ((size >= fpga[0].size) && ( autoload ) && (0 == strcmp(autoload, "1"))) {
-+ if (FPGA_SUCCESS != fpga_load( 0, (void *)buffer, size )) {
-+ lout = 1;
++ if (ctrlc()) {
++ printf("Firmware download stopped!\n");
++ } else if (FPGA_SUCCESS != fpga_load( 0,(void *)buffer, size )) {
+ printf("Firmware download failed!\n");
++ } else {
++ printf("Firmware successfully programmed\n");
++ lout = 1;
+ }
-+ else
-+ printf("Firmware successfully programmed\n");
+ }
+ return lout;
+}
diff --git a/patches/u-boot/2011.12/310-apf27-nand-spl.patch b/patches/u-boot/2011.12/310-apf27-nand-spl.patch
index db09282..daa8554 100644
--- a/patches/u-boot/2011.12/310-apf27-nand-spl.patch
+++ b/patches/u-boot/2011.12/310-apf27-nand-spl.patch
@@ -604,14 +604,14 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+ str r1, [r0]
+
+ /* writeb(0xA0001000, any value) */
-+ ldr r1, =CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
+ ldrb r2, [r1]
+
+ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
+ str r1, [r0]
+
-+ ldr r4, =CONFIG_SYS_SDRAM_1_BASE /* CSD0 base address */
++ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
+
+ ldr r6,=0x7 /* load loop counter */
+1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
@@ -623,11 +623,11 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+ str r1, [r0]
+
+ /* set standard mode register */
-+ ldr r4, = CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
+ ldrb r2, [r4]
+
+ /* set extended mode register */
-+ ldr r4, =CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++ ldr r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r5, [r4]
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
@@ -644,14 +644,14 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+ str r1, [r0]
+
+ /* writeb(0xB0001000, any value) */
-+ ldr r1, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
+ ldrb r2, [r1]
+
+ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
+ str r1, [r0]
+
-+ ldr r4, =CONFIG_SYS_SDRAM_2_BASE /* CSD1 base address */
++ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
+
+ ldr r6,=0x7 /* load loop counter */
+1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
@@ -663,11 +663,11 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+ str r1, [r0]
+
+ /* set standard mode register */
-+ ldr r4, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
+ ldrb r2, [r4]
+
+ /* set extended mode register */
-+ ldr r4, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
+ ldrb r2, [r4]
+
+ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
hooks/post-receive
--
armadeus
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