[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-156-gd9ebdaf

[Julien B a. A. <ar...@us...>]

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- Log -----------------------------------------------------------------
commit d9ebdafc9f402ec241f085573fb52837833185dc
Author: Julien Boibessot <jul...@ar...>
Date:   Mon Mar 19 16:47:47 2012 +0100

    [DEBUG] Add i.MX51/53 CSI registers to imxregs

-----------------------------------------------------------------------

Summary of changes:
 target/linux/debug/imxregs/imx51regs.h |   35 ++++++++++++++++++++++++++++++-
 1 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/target/linux/debug/imxregs/imx51regs.h b/target/linux/debug/imxregs/imx51regs.h
index 4c4f9f8..b658853 100644
--- a/target/linux/debug/imxregs/imx51regs.h
+++ b/target/linux/debug/imxregs/imx51regs.h
@@ -1,7 +1,7 @@
 /*
- * imx51regs.h - i.MX51 registers definition
+ * imx5xregs.h - i.MX5x registers definition
  *
- * Copyright (C) 2010 armadeus systems
+ * Copyright (C) 2010-2012 armadeus systems
  * Derivated from pxaregs (c) Copyright 2002 by M&N Logistik-Loesungen Online GmbH
  * Author: Julien Boibessot
  *
@@ -23,10 +23,41 @@
 
 #include "definitions.h"
 
+#ifdef IMX51
 #define IMX_TYPE "i.MX51"
+#define CSI0_BASE(x)	(0x5e030000 + x)
+#define CSI1_BASE(x)	(0x5e038000 + x)
+#else
+#define IMX_TYPE "i.MX53"
+#define CSI0_BASE(x)	(0x1e030000 + x)
+#define CSI1_BASE(x)	(0x1e038000 + x)
+#endif
 
 static struct reg_info regs[] =
 {
+/* IPU */
+{ "CSI0_SENS_CONF",	CSI0_BASE(0x00), 0, 0xffffffff, 'x', "CSI0 Sensor Configuration Register" },
+{ "CSI0_SENS_FRM_SIZE",	CSI0_BASE(0x04), 0, 0xffffffff, 'x', "CSI0 Sensor Frame Size Register" },
+{ "CSI0_ACT_FRM_SIZE",	CSI0_BASE(0x08), 0, 0xffffffff, 'x', "CSI0 Actual Frame Size Register" },
+{ "CSI0_OUT_FRM_CTRL",	CSI0_BASE(0x0c), 0, 0xffffffff, 'x', "CSI0 Output Control Register" },
+{ "CSI0_TST_CTRL",	CSI0_BASE(0x10), 0, 0xffffffff, 'x', "CSI0 Test Control Register" },
+{ "CSI0_CCIR_CODE_1",	CSI0_BASE(0x14), 0, 0xffffffff, 'x', "CSI0 CCIR Code Register 1" },
+{ "CSI0_CCIR_CODE_2",	CSI0_BASE(0x18), 0, 0xffffffff, 'x', "CSI0 CCIR Code Register 2" },
+{ "CSI0_CCIR_CODE_3",	CSI0_BASE(0x1c), 0, 0xffffffff, 'x', "CSI0 CCIR Code Register 3" },
+{ "CSI0_DI",		CSI0_BASE(0x20), 0, 0xffffffff, 'x', "CSI0 Data Identifier Register" },
+{ "CSI0_SKIP",		CSI0_BASE(0x24), 0, 0xffffffff, 'x', "CSI0 Skip Register" },
+{ "CSI0_CPD_CTRL",	CSI0_BASE(0x28), 0, 0xffffffff, 'x', "CSI0 Compander Control Register" },
+{ "CSI1_SENS_CONF",	CSI1_BASE(0x00), 0, 0xffffffff, 'x', "CSI1 Sensor Configuration Register" },
+{ "CSI1_SENS_FRM_SIZE",	CSI1_BASE(0x04), 0, 0xffffffff, 'x', "CSI1 Sensor Frame Size Register" },
+{ "CSI1_ACT_FRM_SIZE",	CSI1_BASE(0x08), 0, 0xffffffff, 'x', "CSI1 Actual Frame Size Register" },
+{ "CSI1_OUT_FRM_CTRL",	CSI1_BASE(0x0c), 0, 0xffffffff, 'x', "CSI1 Output Control Register" },
+{ "CSI1_TST_CTRL",	CSI1_BASE(0x10), 0, 0xffffffff, 'x', "CSI1 Test Control Register" },
+{ "CSI1_CCIR_CODE_1",	CSI1_BASE(0x14), 0, 0xffffffff, 'x', "CSI1 CCIR Code Register 1" },
+{ "CSI1_CCIR_CODE_2",	CSI1_BASE(0x18), 0, 0xffffffff, 'x', "CSI1 CCIR Code Register 2" },
+{ "CSI1_CCIR_CODE_3",	CSI1_BASE(0x1c), 0, 0xffffffff, 'x', "CSI1 CCIR Code Register 3" },
+{ "CSI1_DI",		CSI1_BASE(0x20), 0, 0xffffffff, 'x', "CSI1 Data Identifier Register" },
+{ "CSI1_SKIP",		CSI1_BASE(0x24), 0, 0xffffffff, 'x', "CSI1 Skip Register" },
+{ "CSI1_CPD_CTRL",	CSI1_BASE(0x28), 0, 0xffffffff, 'x', "CSI1 Compander Control Register" },
 /* CCM */
 { "CCR",	0x73fd4000, 0, 0xffffffff, 'x', "CCM Control Register" },
 { "CCDR",	0x73fd4004, 0, 0xffffffff, 'x', "CCM Control Divider Register" },


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