[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-98-g8fc7106

[Julien B a. A. <ar...@us...>]

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- Log -----------------------------------------------------------------
commit 8fc7106882947fd07a7ae90089e34db13aa452d8
Author: Julien Boibessot <jul...@ar...>
Date:   Mon Mar 5 18:58:12 2012 +0100

    [LINUX] 3.0: removes perturbating 401 patch (no more needed)

-----------------------------------------------------------------------

Summary of changes:
 .../linux/3.0/401-armadeus-fix_clock_tree.patch    |   49 --------------------
 1 files changed, 0 insertions(+), 49 deletions(-)
 delete mode 100644 patches/linux/3.0/401-armadeus-fix_clock_tree.patch

diff --git a/patches/linux/3.0/401-armadeus-fix_clock_tree.patch b/patches/linux/3.0/401-armadeus-fix_clock_tree.patch
deleted file mode 100644
index e62f830..0000000
--- a/patches/linux/3.0/401-armadeus-fix_clock_tree.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-Change default GTP clock source for the APF51 to 32k one. Indeed current U-Boot
-setup 32k as main clock for GPT1 and Linux should take that into account.
-
-Patch has to be reworked to dynamically do that switch.
-
-Signed-off-by: Nicolas Colombain <nic...@ar...>
-
-Index: linux-3.0.10/arch/arm/mach-mx5/clock-mx51-mx53.c
-===================================================================
---- linux-3.0.10.orig/arch/arm/mach-mx5/clock-mx51-mx53.c	2011-11-21 23:37:44.000000000 +0100
-+++ linux-3.0.10/arch/arm/mach-mx5/clock-mx51-mx53.c	2011-11-30 18:52:53.000000000 +0100
-@@ -1536,7 +1536,7 @@
- 	clk_set_rate(&esdhc2_clk, 166250000);
- 
- 	/* System timer */
--	mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-+	mxc_timer_init(&gpt_32k_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
- 		MX51_MXC_INT_GPT);
- 	return 0;
- }
-Index: linux-3.0.10/arch/arm/plat-mxc/time.c
-===================================================================
---- linux-3.0.10.orig/arch/arm/plat-mxc/time.c	2011-11-21 23:37:44.000000000 +0100
-+++ linux-3.0.10/arch/arm/plat-mxc/time.c	2011-11-30 17:18:02.000000000 +0100
-@@ -57,6 +57,7 @@
- /* MX31, MX35, MX25, MX5 */
- #define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
- #define V2_TCTL_CLK_IPG		(1 << 6)
-+#define V2_TCTL_CLK_IPG_32k	(1 << 8)
- #define V2_TCTL_FRR		(1 << 9)
- #define V2_IR			0x0c
- #define V2_TSTAT		0x08
-@@ -281,6 +282,7 @@
- 	clockevent_mxc.min_delta_ns =
- 			clockevent_delta2ns(0xff, &clockevent_mxc);
- 
-+	printk("___ %s %dkHz mult=%d\n", __func__, c, clockevent_mxc.mult);
- 	clockevent_mxc.cpumask = cpumask_of(0);
- 
- 	clockevents_register_device(&clockevent_mxc);
-@@ -304,7 +306,7 @@
- 	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
- 
- 	if (timer_is_v2())
--		tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
-+		tctl_val = V2_TCTL_CLK_IPG_32k | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
- 	else
- 		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
- 


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