[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-80-gac21fda

[Julien B a. A. <ar...@us...>]

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- Log -----------------------------------------------------------------
commit ac21fda86ba6d1c0d9ff1576420f4d27dd2c7ada
Author: Julien Boibessot <jul...@ar...>
Date:   Mon Feb 27 17:14:31 2012 +0100

    [DEBUG] Add i.MX51 GPIO Bank 1 registers to imxregs

commit 731e84dc8356e792b37a8a3c8839c030c76914bc
Author: Julien Boibessot <jul...@ar...>
Date:   Mon Feb 27 17:08:28 2012 +0100

    [DEMOS] Add square wave generator for preempt-rt tests (APF51)

-----------------------------------------------------------------------

Summary of changes:
 target/demos/real_time/pulse/preempt-rt/swave.c |  106 +++++++++++++++++++++++
 target/linux/debug/imxregs/imx51regs.h          |    9 ++
 2 files changed, 115 insertions(+), 0 deletions(-)
 create mode 100644 target/demos/real_time/pulse/preempt-rt/swave.c

diff --git a/target/demos/real_time/pulse/preempt-rt/swave.c b/target/demos/real_time/pulse/preempt-rt/swave.c
new file mode 100644
index 0000000..b9d3cbb
--- /dev/null
+++ b/target/demos/real_time/pulse/preempt-rt/swave.c
@@ -0,0 +1,106 @@
+/* 
+ * Generates a square wave on platform dependant GPIO.
+ * taken from: https://rt.wiki.kernel.org/articles/s/q/u/Squarewave-example.html
+ *
+ * compile using  "arm-linux-gcc -o swave swave.c -lrt -Wall"
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <time.h>
+#include <sched.h>
+#include <fcntl.h>
+#include <sys/mman.h>	/* mmap */
+
+#define NSEC_PER_SEC    1000000000
+#define MAP_SIZE 4096
+#define MAP_MASK ( MAP_SIZE - 1 )
+#define u32	unsigned int
+
+/* Platform specific stuff (here for APF51) */
+#define GPIO_PIN	2
+#define GPIO_DR_ADDR	0x73f84000
+#define GPIO_DR_MASK	(~(1 << GPIO_PIN))
+
+/* using clock_nanosleep of librt */
+extern int clock_nanosleep(clockid_t __clock_id, int __flags,
+				__const struct timespec *__req,
+				struct timespec *__rem);
+
+/* the struct timespec consists of nanoseconds and seconds. if the
+ * nanoseconds are getting bigger than 1000000000 (= 1 second) the
+ * variable containing seconds has to be incremented and the
+ * nanoseconds decremented by 1000000000.
+ */
+static inline void tsnorm(struct timespec *ts)
+{
+	while (ts->tv_nsec >= NSEC_PER_SEC) {
+		ts->tv_nsec -= NSEC_PER_SEC;
+		ts->tv_sec++;
+	}
+}
+
+void out()
+{
+	static unsigned char state=0;
+	static int fd = -1;
+	static void *map, *regaddr;
+	u32 addr = GPIO_DR_ADDR;
+
+	if (fd == -1) {
+		fd = open("/dev/mem", O_RDWR | O_SYNC);
+		if (fd < 0) {
+			perror("open(\"/dev/mem\")");
+			exit(1);
+		}
+		map = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED,
+				fd, addr & ~MAP_MASK);
+		if (map == (void *)-1) {
+			perror("mmap()");
+			exit(1);
+		}
+		regaddr = map + (addr & MAP_MASK);
+	}
+
+	state = state ? 0 : 1;
+	*(u32 *) regaddr = (*(u32 *) regaddr & GPIO_DR_MASK) | (state << GPIO_PIN);
+}
+
+int main(int argc, char** argv)
+{
+	struct timespec t;
+	struct sched_param param;
+
+	/* default interval = 100000000ns = 100ms */
+	int interval = 100000000;
+
+	if(argc >= 2 && atoi(argv[1]) > 0) {
+		printf("using realtime, priority: %d\n",atoi(argv[1]));
+		param.sched_priority = atoi(argv[1]);
+		/* enable realtime fifo scheduling */
+		if (sched_setscheduler(0, SCHED_FIFO, &param) == -1) {
+			perror("sched_setscheduler failed");
+			exit(-1);
+		}
+	}
+	if (argc >= 3)
+		interval = atoi(argv[2]);
+
+	/* get current time */
+	clock_gettime(0, &t);
+	/* start after one second */
+	t.tv_sec++;
+	while(1) {
+		/* wait until next shot */
+		clock_nanosleep(0, TIMER_ABSTIME, &t, NULL);
+		/* do the stuff */
+		out();
+		/* calculate next shot */
+		t.tv_nsec += interval;
+		tsnorm(&t);
+	}
+
+	return 0;
+}
+
diff --git a/target/linux/debug/imxregs/imx51regs.h b/target/linux/debug/imxregs/imx51regs.h
index cc6b0b5..4c4f9f8 100644
--- a/target/linux/debug/imxregs/imx51regs.h
+++ b/target/linux/debug/imxregs/imx51regs.h
@@ -61,6 +61,15 @@ static struct reg_info regs[] =
 { "CCGR5",	0x73fd407c, 0, 0xffffffff, 'x', "CCM Clock Gating Register 5" },
 { "CCGR6",	0x73fd4080, 0, 0xffffffff, 'x', "CCM Clock Gating Register 6" },
 { "CMEOR",	0x73fd4084, 0, 0xffffffff, 'x', "CCM Module Enable Override Register" },
+/* GPIO */
+{ "GPIO1_DR",   0x73f84000, 0, 0xffffffff, 'x', "GPIO Bank1 Data Register" },
+{ "GPIO1_DIR",	0x73f84004, 0, 0xffffffff, 'x', "GPIO Bank1 Direction Register" },
+{ "GPIO1_PSR",	0x73f84008, 0, 0xffffffff, 'x', "GPIO Bank1 Pad Status Register" },
+{ "GPIO1_ICR1",	0x73f8400c, 0, 0xffffffff, 'x', "GPIO Bank1 Interrupt Configuration Register 1" },
+{ "GPIO1_ICR2",	0x73f84010, 0, 0xffffffff, 'x', "GPIO Bank1 Interrupt Configuration Register 2" },
+{ "GPIO1_IMR",	0x73f84014, 0, 0xffffffff, 'x', "GPIO Bank1 Interrupt Mask Register" },
+{ "GPIO1_ISR",	0x73f84018, 0, 0xffffffff, 'x', "GPIO Bank1 Interrupt Status Register" },
+{ "GPIO1_EDGE",	0x73f8401c, 0, 0xffffffff, 'x', "GPIO Bank1 Edge Detect Register" },
 /* GPT */
 { "GPTCR_1",	0x73fa0000, 0, 0xffffffff, 'x', "GPT1 Control Register" },
 { "GPTPR_1",	0x73fa0004, 0, 0xffffffff, 'x', "GPT1 Prescaler Register" },


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