[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-71-g75ee35d
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-71-g75ee35d
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From: jorasse <jo...@us...> - 2012-02-20 23:59:03
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The branch, master has been updated
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via f294bdc5ec46d4afd9d130f8ba98a4e24b511257 (commit)
via 2194eaa6f9f0b60d5d7d9f0f58d36020ec2f4fbd (commit)
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- Log -----------------------------------------------------------------
commit 75ee35dec2f10b85e786c0062251df515f24d91d
Merge: f294bdc 9deef89
Author: Eric Jarrige <eri...@ar...>
Date: Tue Feb 21 00:58:38 2012 +0100
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit f294bdc5ec46d4afd9d130f8ba98a4e24b511257
Author: Eric Jarrige <eri...@ar...>
Date: Tue Feb 21 00:58:17 2012 +0100
[UBOOT] apf51: add config option for uboot 2011.12 to force number of RAM on rev 0 boards - rev 1 support auto detection of number of RAM and UBoot autorelocation at the end of RAM
commit 2194eaa6f9f0b60d5d7d9f0f58d36020ec2f4fbd
Author: Eric Jarrige <eri...@ar...>
Date: Tue Feb 21 00:16:40 2012 +0100
[UBOOT] apf51: support UBoot 2011.12 relocation to the end of the 2nd flash
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf51/apf51-u-boot-2011.12.h | 886 ++++++++++++++++++++
...ariable-to-check-number-of-ram-at-runtime.patch | 23 +
patches/u-boot/2011.12/401-apf51.patch | 53 +-
patches/u-boot/2011.12/409-apf51-nand-spl.patch | 4 +-
4 files changed, 947 insertions(+), 19 deletions(-)
create mode 100644 buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
create mode 100644 patches/buildroot/2011.05/173-u-boot-add-variable-to-check-number-of-ram-at-runtime.patch
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
new file mode 100644
index 0000000..1f64949
--- /dev/null
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
@@ -0,0 +1,886 @@
+/*
+ *
+ * Configuration settings for the Armadeus Project apf51 board.
+ *
+ * (C) Copyright 2010-2012 Eric Jarrige, Armadeus Project
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * 2010/03/31 Initial version based on apf27 configuration file
+ * 2011/05/02 patch V0.5 updates NAND OOB to be mx51 linux kernel compliant
+ * (at least for the first 11 spare bytes..)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_VERSION "0.6"
+#define CONFIG_IDENT_STRING " apf51 patch 0.8"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU */
+#define CONFIG_MX51 /* in a Freescale i.MX51 Chip */
+#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
+#define CONFIG_MACH_TYPE 2795 /* APF51 */
+
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_SYS_TEXT_BASE 0x97000000
+
+/*
+ * Select serial console configuration
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART3_BASE
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Boot options. Setting delay to -1 stops autostart count down.
+ */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTARGS \
+ CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=jffs2 " MTDPARTS_DEFAULT
+
+#define CONFIG_CONSOLE "console=ttymxc2,"MK_STR(CONFIG_BAUDRATE)
+#define CONFIG_MTDMAP "mxc_nand"
+#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
+#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP ":1M(U-boot)ro," \
+ "1M(U-boot_env),1M(firmware)," \
+ "8M(kernel)," \
+ "-(rootfs)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "env_version=" CONFIG_ENV_VERSION "\0" \
+ "fileaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "filesize=" MK_STR(CONFIG_SYS_MONITOR_LEN) "\0" \
+ "console=" CONFIG_CONSOLE "\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "partition=nand0,4\0" \
+ "uboot_offset=" MK_STR(CONFIG_SYS_MONITOR_OFFSET) "\0" \
+ "uboot_len=" MK_STR(CONFIG_SYS_MONITOR_LEN) "\0" \
+ "env_offset=" MK_STR(CONFIG_ENV_OFFSET) "\0" \
+ "env_len=" MK_STR(CONFIG_ENV_RANGE) "\0" \
+ "firmware_offset=" MK_STR(CONFIG_FIRMWARE_OFFSET) "\0" \
+ "firmware_len=" MK_STR(CONFIG_FIRMWARE_LEN) "\0" \
+ "kernel_offset=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \
+ "kernel_len=" MK_STR(CONFIG_KERNEL_LEN) "\0" \
+ "rootfs_offset=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0" \
+ "rootfs_len=" MK_STR(CONFIG_ROOTFS_LEN) "\0" \
+ "board_name=" MK_STR(CONFIG_BOARD_NAME) "\0" \
+ "serverpath=" MK_STR(CONFIG_SRV_PATH) "\0" \
+ "ntpserverip=217.147.208.1\0" \
+ "mmcroot=/dev/mmcblk0p1\0" \
+ "mmcrootfstype=ext2\0" \
+ "quiet=1\0" \
+ "addnfsargs=setenv bootargs ${bootargs} " \
+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
+ "addjffsargs=setenv bootargs ${bootargs} " \
+ "root=/dev/mtdblock4 rootfstype=jffs2\0" \
+ "addubifsargs=setenv bootargs ${bootargs} " \
+ "ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
+ "addmmcargs=setenv bootargs ${bootargs} " \
+ "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \
+ "addipargs=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
+ "${hostname}:eth0:off\0" \
+ "nfsboot=setenv bootargs ${console} ${mtdparts};" \
+ "run addnfsargs addipargs; setenv autostart yes;" \
+ "nboot.jffs2 90800000 0 ${kernel_offset}\0" \
+ "jffsboot=setenv bootargs ${console} ${mtdparts};" \
+ "run addjffsargs addipargs; setenv autostart yes;" \
+ "nboot.jffs2 90800000 0 ${kernel_offset}\0" \
+ "ubifsboot=setenv bootargs ${console} ${mtdparts};" \
+ "run addubifsargs addipargs; setenv autostart yes;" \
+ "nboot.jffs2 90800000 0 ${kernel_offset}\0" \
+ "mmcboot=setenv bootargs ${console} ${mtdparts};" \
+ "run addmmcargs addipargs; setenv autostart yes;" \
+ "nboot.jffs2 90800000 0 ${kernel_offset}\0" \
+ "firmware_autoload=0\0" \
+ "flash_uboot=nand unlock ${uboot_offset} ${uboot_len};" \
+ "nand erase ${uboot_offset} ${uboot_len};" \
+ "if nand write.jffs2 ${fileaddr} ${uboot_offset} ${filesize};" \
+ "then nand lock; nand unlock ${env_offset};" \
+ "echo Flashing of uboot succeed;" \
+ "else echo Flashing of uboot failed;" \
+ "fi; \0" \
+ "flash_firmware=nand erase ${firmware_offset} ${firmware_len};" \
+ "if nand write.jffs2 ${fileaddr} ${firmware_offset}" \
+ " ${filesize};" \
+ "then echo Flashing of Firmware succeed;" \
+ "else echo Flashing of Firmware failed;" \
+ "fi\0" \
+ "fpga_config=tftpboot ${fileaddr} $firmware_name;" \
+ "run flash_firmware;" \
+ "fpga load 0 ${fileaddr} ${firmware_len};\0" \
+ "flash_kernel=nand erase ${kernel_offset} ${kernel_len};" \
+ "if nand write.jffs2 ${fileaddr} ${kernel_offset} ${filesize};"\
+ "then echo Flashing of kernel succeed;" \
+ "else echo Flashing of kernel failed;" \
+ "fi\0" \
+ "flash_rootfs=nand erase.part rootfs;" \
+ "if nand write.jffs2 ${fileaddr} ${rootfs_offset} ${filesize};"\
+ "then echo Flashing of rootfs succeed;" \
+ "else echo Flashing of rootfs failed;" \
+ "fi\0" \
+ "flash_reset_env=nand unlock ${env_offset} ${env_len};" \
+ "nand erase ${env_offset} ${env_len};" \
+ "echo Flash environment variables erased!\0" \
+ "download_uboot=tftpboot ${loadaddr} " \
+ " ${serverpath}${board_name}-u-boot.bin\0" \
+ "download_kernel=tftpboot ${loadaddr} " \
+ " ${serverpath}${board_name}-linux.bin\0" \
+ "download_rootfs=tftpboot ${loadaddr} " \
+ " ${serverpath}${board_name}-rootfs.ubi\0" \
+ "update_uboot=run download_uboot flash_uboot\0" \
+ "update_kernel=run download_kernel flash_kernel\0" \
+ "update_rootfs=run download_rootfs flash_rootfs\0" \
+ "update_all=run download_kernel flash_kernel download_rootfs " \
+ "flash_rootfs download_uboot flash_uboot\0" \
+ "unlock_regs=mw 10000008 0; mw 10020008 0;TODO\0"
+
+#define CONFIG_BOOTCOMMAND "run ubifsboot"
+
+#define CONFIG_SYS_AUTOLOAD "no"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+*/
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.10
+#define CONFIG_BOARD_NAME "apf51"
+#define CONFIG_HOSTNAME "apf51"
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.2
+#define CONFIG_SRV_PATH ""
+#define CONFIG_ROOTPATH "/tftpboot/apf51-root"
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV /* ask for env variable */
+#define CONFIG_CMD_BSP /* Board Specific functions */
+#define CONFIG_CMD_CACHE /* icache, dcache */
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_IIM /* imx iim fuse */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING /* ping support */
+
+/*
+ * Select some advanced features of the commande line parser
+ */
+
+#define CONFIG_BOOT_PARAMS_ADDR 0x90000100
+
+/**
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
+#define CONFIG_AUTO_COMPLETE /* Enable auto completion of */
+ /* commands using TAB */
+
+#define CONFIG_SYS_CBSIZE 1024 /* console I/O buffer */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* print buffer size */
+#define CONFIG_SYS_MAXARGS 16 /* max command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* boot args buf size */
+
+#define CONFIG_SYS_MEMTEST_START 0x90000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x90100000 /* 1st MiB in DRAM */
+
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x90000000
+#define CONFIG_LOADADDR 0x90000000
+
+#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1 ms */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * Malloc pool need to host env. + 2 MB reserve for other allocations.
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 * 1024 * 1024) )
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE (128<<10) /* stack size */
+#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
+#endif
+
+/*
+ * CPU Flash boot constants
+ */
+#ifndef CONFIG_DOWNLOAD_BY_DEBUGGER
+#define CONFIG_FLASH_HEADER
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+#endif
+
+/*
+ * Enable the call to miscellaneous platform dependent initialization.
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+/*
+#define CONFIG_REVISION_TAG
+#define CONFIG_OF_LIBFDT
+*/
+/*
+ * SDRAM Configs
+ */
+#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_NR_DRAM_POPULATED 1
+#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR /* SDRAM bank #1 */
+#define PHYS_SDRAM_SIZE 256
+#define PHYS_SDRAM_1_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
+#define PHYS_SDRAM_2_SIZE (PHYS_SDRAM_SIZE) * 1024 * 1024
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_MONITOR_OFFSET 0x00000000 /* offset in NAND */
+#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
+#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
+#define CONFIG_ENV_RANGE 0x00100000 /* 1MB */
+#define CONFIG_ENV_OVERWRITE /* env is writable now */
+#define CONFIG_FIRMWARE_OFFSET 0x00200000
+#define CONFIG_FIRMWARE_LEN 0x00100000 /* 1MB */
+#define CONFIG_KERNEL_OFFSET 0x00300000
+#define CONFIG_KERNEL_LEN 0x00800000 /* 8MB (BB ready) */
+#define CONFIG_ROOTFS_OFFSET 0x00B00000
+#define CONFIG_ROOTFS_LEN /* entire flash if not specified */
+
+/*
+ * Configuration for no NOR FLASH memory
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC_V2
+#define CONFIG_MXC_NAND_REGS_BASE 0xCFFF0000
+#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+/*#define CONFIG_MTD_NAND_VERIFY_WRITE*/
+
+/*#define CONFIG_SYS_DIRECT_FLASH_TFTP*/
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+#define NAND_MAX_CHIPS 1
+
+/*=====================*/
+
+#define CONFIG_NAND_U_BOOT
+/* Copy SPL+U-Boot here */
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_LOAD_ADDR
+/* Size is the partion size */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
+/*
+#define CONFIG_NAND_ENV_DST
+#define CONFIG_ENV_OFFSET_REDUND
+*/
+
+/*
+ * Partitions & Filsystems
+ */
+#undef CONFIG_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/**
+ * I2C Configs
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MXC 1
+#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
+#define CONFIG_SYS_I2C_MX51_PORT2
+#define CONFIG_SYS_I2C_SPEED 400000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+
+/**
+ * RTC PMIC TODO TODO TODO TODO
+ */
+
+/*
+ * SD/MMC Configs
+ */
+
+/**
+ * SPI Configs
+ */
+
+/**
+ * Watchdog Config
+ */
+
+#define CONFIG_HW_WATCHDOG
+
+/**
+ * IIM fuse Config
+ */
+
+#define CONFIG_IMX_IIM
+#define CONFIG_IIM_MAC_BANK 1
+#define CONFIG_IIM_MAC_ROW 9
+
+/**
+ * GPIO: Support for MXC GPIO
+ */
+
+#define CONFIG_MXC_GPIO
+
+/**
+ * Ethernet: Support for internal Fast Ethernet Controller
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_SYS_PHY_RESET_GPIO IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11)
+
+#define CONFIG_FEC_MXC_PHYADDR 0x02
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+/*-----------------------------------------------------------------------
+ * FPGA
+ */
+#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
+/*#define FPGA_DEBUG*/
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_WAIT 20000 /* 20 ms */
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_CHECK_ERROR
+
+/* FPGA program pin configuration */
+#define ACFG_FPGA_PWR MX51_PIN_DI1_D0_CS
+#define ACFG_FPGA_PRG MX51_PIN_CSI2_D12
+#define ACFG_FPGA_RDATA CS1_BASE_ADDR
+#define ACFG_FPGA_WDATA CS1_BASE_ADDR
+#define ACFG_FPGA_INIT MX51_PIN_CSI2_D18
+#define ACFG_FPGA_DONE MX51_PIN_CSI2_D13
+#define ACFG_FPGA_SUSPEND MX51_PIN_DISPB2_SER_DIO
+
+#define ACFG_FPGA_GCR1_VALUE 0x019100bf
+#define ACFG_FPGA_GCR2_VALUE 0x00000000
+
+#define ACFG_FPGA_RCR1_VALUE 0x04000010
+#define ACFG_FPGA_RCR2_VALUE 0x00000000
+
+#define ACFG_FPGA_WCR1_VALUE 0x04000008
+#define ACFG_FPGA_WCR2_VALUE 0x00000000
+
+/*
+* Clocks configuration
+*/
+
+#define CONFIG_SYS_MX5_CLK32 32768
+#define CONFIG_SYS_MX5_HCLK 1024*CONFIG_SYS_MX5_CLK32
+#define CONFIG_MX51_PLL_ERRATA
+
+/* external bus frequencies */
+#define APF_DDR_CLK 200 /* MHZ DDR frequency from PLL1 */
+#define APF_ARM_CLK 800 /* MHZ CPU frequency from PLL1 */
+#define APF_AXIA_CLK 166 /* MHZ AXI A frequency from PLL2 */
+#define APF_AXIB_CLK 110 /* 110.8 133 MHZ AXI B frequency from PLL2 */
+#define APF_EMI_CLK 95 /* MHZ AHB frequency from PLL2 */
+#define APF_AHB_CLK 133 /* MHZ AHB frequency from PLL2 */
+#define APF_IPG_CLK 66 /* 66.5 MHZ IPG frequency from PLL2 */
+#define APF_PERCLK 55 /* 55.4 MHZ PERCLK frequency */
+#define APF_NFC_CLK 23 /* MHZ NFC Clock from EMI clk */
+#define APF_USB_CLK 54 /* external USB serial bus frequency PLL3 */
+#define APF_ESDHC_CLK 54 /* MHz ESDHC controller frequency / PLL3 */
+#define APF_UART_CLK 66 /* 66.5 MHz UART frequency from PLL2 */
+
+//#define APF_SSI_CLK 54 /* MHz SSI controller frequency */
+//#define APF_TVE_CLK 216 /* MHz TVE controller frequency */
+//#define APF_DI_CLK 0 /* MHz DISPLAY controller frequency*/
+//#define APF_VPU_CLK 0 /* MHz VPU controller frequency*/
+//#define APF_SPDIF_CLK 10 /* MHz SPDIF controller frequency 10.3 MHz*/
+//#define APF_SIM_CLK 54 /* MHz SIM controller frequency */
+//#define APF_FIRI_CLK 54 /* MHz FIRI controller frequency */
+//#define APF_HSI2C_CLK 54 /* MHz HS I2C controller frequency */
+//#define APF_CSI_CLK 54 /* MHz HS CSI controller frequency */
+//#define APF_ECSPI_CLK 54 /* MHz HECSPI controller frequency */
+//#define APF_WRCK_CLK 13 /* MHz WRCK 13.3 MHz */
+//#define APF_LPSR_CLK 0 /* MHz */
+#define APF_PGC_CLK 66 /* MHz 66.5 MHz */
+
+/**
+ * iMX51 PLL constants
+ */
+
+/* PLL parameters assuming 32.768kHz *1024 input clock with doubler ON */
+/* MFI PDF */
+#define DP_OP_864 ((11 << 4) + ((2 - 1) << 0))
+#define DP_MFD_864 (65536 - 1)
+#define DP_MFN_864 122854
+#define DP_MFN_800_DIT 60354
+
+#define DP_OP_850 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_850 (1048576 - 1)
+#define DP_MFN_850 349169
+
+#define ACFG_PLL1_CLK 800 /* MHz */
+#define DP_OP_800 ((11 << 4) + ((2 - 1) << 0))
+#define DP_MFD_800 (65536 - 1)
+#define DP_MFN_800 60354
+
+#define ACFG_PLL2_CLK 665 /* MHz */
+#define DP_OP_665 ((14 << 4) + ((3 - 1) << 0))
+#define DP_MFD_665 (2097152 - 1)
+#define DP_MFN_665 1811747
+
+#define ACFG_PLL3_CLK 216 /* MHz */
+#define DP_OP_216 ((8 << 4) + ((5 - 1) << 0))
+#define DP_MFD_216 (262144 - 1)
+#define DP_MFN_216 12223
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_SYS_DDR_CLKSEL 0
+
+/*
+ * Hardware drivers
+ */
+
+/*-----------------------------------------------------------------------
+ * WEIM - EIM
+ */
+ /* force BCLK free run */
+#define ACFG_WCR_VALUE 0x00000021
+#define ACFG_WIAR_VALUE 0x00000010
+
+/* CS1 */
+#define ACFG_CS1GCR1_VALUE ACFG_FPGA_GCR1_VALUE
+#define ACFG_CS1GCR2_VALUE ACFG_FPGA_GCR2_VALUE
+
+#define ACFG_CS1RCR1_VALUE ACFG_FPGA_RCR1_VALUE
+#define ACFG_CS1RCR2_VALUE ACFG_FPGA_RCR2_VALUE
+
+#define ACFG_CS1WCR1_VALUE ACFG_FPGA_WCR1_VALUE
+#define ACFG_CS1WCR2_VALUE ACFG_FPGA_WCR2_VALUE
+
+/* CS2 */
+#define ACFG_CS2GCR1_VALUE 0x00010080
+#define ACFG_CS2GCR2_VALUE 0x00000000
+
+#define ACFG_CS2RCR1_VALUE 0x00000000
+#define ACFG_CS2RCR2_VALUE 0x00000000
+
+#define ACFG_CS2WCR1_VALUE 0x00000000
+#define ACFG_CS2WCR2_VALUE 0x00000000
+
+/* CS3 */
+#define ACFG_CS3GCR1_VALUE 0x00010080
+#define ACFG_CS3GCR2_VALUE 0x00000000
+
+#define ACFG_CS3RCR1_VALUE 0x00000000
+#define ACFG_CS3RCR2_VALUE 0x00000000
+
+#define ACFG_CS3WCR1_VALUE 0x00000000
+#define ACFG_CS3WCR2_VALUE 0x00000000
+
+/* CS4 */
+#define ACFG_CS4GCR1_VALUE 0x00010080
+#define ACFG_CS4GCR2_VALUE 0x00000000
+
+#define ACFG_CS4RCR1_VALUE 0x00000000
+#define ACFG_CS4RCR2_VALUE 0x00000000
+
+#define ACFG_CS4WCR1_VALUE 0x00000000
+#define ACFG_CS4WCR2_VALUE 0x00000000
+
+/* CS5 */
+#define ACFG_CS5GCR1_VALUE 0x00010080
+#define ACFG_CS5GCR2_VALUE 0x00000000
+
+#define ACFG_CS5RCR1_VALUE 0x00000000
+#define ACFG_CS5RCR2_VALUE 0x00000000
+
+#define ACFG_CS5WCR1_VALUE 0x00000000
+#define ACFG_CS5WCR2_VALUE 0x00000000
+
+#include <asm/arch/imx-regs.h>
+
+/*
+ * From here, there should not be any user configuration.
+ * All Equations are automatic
+ */
+
+/**
+ * SDRAM controler configs
+ *
+ * ACFG_SDRAM_NUM_COL 8, 9, 10 or 11 column address bits
+ * ACFG_SDRAM_NUM_ROW 11, 12 or 13 row address bits
+ * ACFG_SDRAM_REFRESH 0=OFF 1=2048 2=4096 3=8192.. refresh
+ * ACFG_SDRAM_XSR_DELAY ns Exit self refresh to any command (>= 25 ddr_clk)
+ * ACFG_SDRAM_EXIT_PWD ns exit power down delay
+ * ACFG_SDRAM_W2R_DELAY WRITE to READ Command Delay 0=1ck 1=2ck
+ * ACFG_SDRAM_ROW_PRECHARGE_DELAY ns (>2 x ddr_clk)
+ * ACFG_SDRAM_TMRD_DELAY Load mode register cycle delay 1..4
+ * ACFG_SDRAM_TWR_DELAY DDR: 0=2ck 1=3ck
+ * ACFG_SDRAM_RAS_DELAY ns ACTIVE-to-PRECHARGE delay
+ * ACFG_SDRAM_RRD_DELAY ns ACTIVE-to-ACTIVE delay
+ * ACFG_SDRAM_RCD_DELAY ns Row to Column delay
+ * ACFG_SDRAM_RC_DELAY ns Row cycle delay (tRFC refresh to command)
+ * ACFG_SDRAM_RFC_DELAY ns (> 10xddr_clk) auto refresh to any command
+ * ACFG_SDRAM_PARTIAL_ARRAY_SR 0=full 1=half 2=quater 3=Eighth 4=Sixteenth
+ * ACFG_SDRAM_DRIVE_STRENGH 0=Full-strength 1=half 2=quater 3=Eighth
+ * ACFG_SDRAM_BURST_LENGTH 2^N BYTES (N=0..3)
+ * ACFG_SDRAM_SINGLE_ACCESS 1= single access; 0 = Burst mode
+ *
+ */
+
+#if (PHYS_SDRAM_SIZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
+#define ACFG_SDRAM_NUM_COL 9 /* 8..11 column address bits */
+#define ACFG_SDRAM_NUM_ROW 13 /* 11..13 row address bits */
+#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.*/
+#define ACFG_SDRAM_XSR_DELAY 138 /* ns Exit self refresh */
+#define ACFG_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
+#define ACFG_SDRAM_W2R_DELAY 1 /* 0=1ck 1=2ck */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk) */
+#define ACFG_SDRAM_TMRD_DELAY 2 /* 1..4 */
+#define ACFG_SDRAM_TWR_DELAY 1 /* DDR: 0=2ck 1=3ck */
+#define ACFG_SDRAM_RAS_DELAY 40 /* ns ACTIVE-to-PRECHARGE*/
+#define ACFG_SDRAM_RRD_DELAY 10 /* ns ACTIVE-to-ACTIVE delay*/
+#define ACFG_SDRAM_RCD_DELAY 15 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY 55 /* ns Row cycle delay */
+#define ACFG_SDRAM_RFC_DELAY 110 /* ns (> 10xddr_clk) */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0..4 */
+#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0..3 */
+#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 0..1 */
+#endif
+
+#if (PHYS_SDRAM_SIZE == 128)
+/* micron 128MB */
+#define ACFG_SDRAM_NUM_COL 10 /* 8..11 column address bits */
+#define ACFG_SDRAM_NUM_ROW 13 /* 11..13 row address bits */
+#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.*/
+#define ACFG_SDRAM_XSR_DELAY 138 /* ns Exit self refresh */
+#define ACFG_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
+#define ACFG_SDRAM_W2R_DELAY 1 /* 0=1ck 1=2ck */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk) */
+#define ACFG_SDRAM_TMRD_DELAY 2 /* 1..4 */
+#define ACFG_SDRAM_TWR_DELAY 1 /* DDR: 0=2ck 1=3ck */
+#define ACFG_SDRAM_RAS_DELAY 40 /* ns ACTIVE-to-PRECHARGE */
+#define ACFG_SDRAM_RRD_DELAY 10 /* ns ACTIVE-to-ACTIVE delay */
+#define ACFG_SDRAM_RCD_DELAY 15 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY 55 /* ns Row cycle delay */
+#define ACFG_SDRAM_RFC_DELAY 110 /* ns (> 10xddr_clk) */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0..4 */
+#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0..3 */
+#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 0..1 */
+#endif
+
+#if (PHYS_SDRAM_SIZE == 256)
+/* micron 256MB */
+#define ACFG_SDRAM_NUM_COL 10 /* 8..11 column address bits */
+#define ACFG_SDRAM_NUM_ROW 14 /* 11..13 row address bits */
+#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.*/
+#define ACFG_SDRAM_XSR_DELAY 125 /* ns Exit self refresh */
+#define ACFG_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
+#define ACFG_SDRAM_W2R_DELAY 1 /* 0=1ck 1=2ck */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk) */
+#define ACFG_SDRAM_TMRD_DELAY 2 /* 1..4 */
+#define ACFG_SDRAM_TWR_DELAY 1 /* DDR: 0=2ck 1=3ck */
+#define ACFG_SDRAM_RAS_DELAY 40 /* ns ACTIVE-to-PRECHARGE */
+#define ACFG_SDRAM_RRD_DELAY 10 /* ns ACTIVE-to-ACTIVE delay */
+#define ACFG_SDRAM_RCD_DELAY 15 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY 55 /* ns Row cycle delay */
+#define ACFG_SDRAM_RFC_DELAY 72 /* ns (> 10xddr_clk) */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0..4 */
+#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0..3 */
+#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 0..1 */
+#endif
+
+/* Issue Mode register Command to SDRAM*/
+#define ACFG_DRR_MR_VAL ( 0x0\
+ | (((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\
+ | ((3)<<(4)) \
+ | (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(3)))
+
+/* Issue Extended Mode register Command to SDRAM*/
+#define ACFG_DRR_EMR_VAL\
+ (((ACFG_SDRAM_PARTIAL_ARRAY_SR&0x7)<<0)\
+ | ((ACFG_SDRAM_DRIVE_STRENGH&0x7)<<(5)))
+
+#define ACFG_SDRAM_ESDGPR_REGISTER_VAL 0x20020000
+#define ACFG_SDRAM_ESDCDLY1_REGISTER_VAL 0x00F48000
+#define ACFG_SDRAM_ESDCDLY2_REGISTER_VAL 0x00F48000
+#define ACFG_SDRAM_ESDCDLY3_REGISTER_VAL 0x00F48000
+#define ACFG_SDRAM_ESDCDLY4_REGISTER_VAL 0x00F48000
+#define ACFG_SDRAM_ESDCDLY5_REGISTER_VAL 0x00F48000
+
+/* SDRAM IO Muxing */
+#define ACFG_IOMUX_PAD_DRAM_RAS PAD_CTL_DRV_HIGH+PAD_CTL_SRE_FAST /* default */
+#define ACFG_IOMUX_PAD_DRAM_CAS PAD_CTL_DRV_HIGH+PAD_CTL_SRE_FAST /* default */
+#define ACFG_IOMUX_PAD_DRAM_SDWE \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_FAST /* imx default */
+#define ACFG_IOMUX_PAD_DRAM_SDCKE0 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_FAST /* imx default */
+#define ACFG_IOMUX_PAD_DRAM_SDCKE1 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_FAST /* imx default */
+#define ACFG_IOMUX_PAD_DRAM_SDCLK \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_MAX+PAD_CTL_SRE_FAST
+#define ACFG_IOMUX_PAD_DRAM_SDQS0 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_SDQS1 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_SDQS2 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_SDQS3 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PD \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_CS0 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_FAST /* imx default */
+#define ACFG_IOMUX_PAD_DRAM_CS1 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH /* imx default */
+#define ACFG_IOMUX_PAD_DRAM_DQM0 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_DQM1 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_DQM2 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_PAD_DRAM_DQM3 \
+ PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+ +PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
+
+#define ACFG_IOMUX_PAD_EIM_SDBA2 \
+ PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+ +PAD_CTL_100K_PU
+#define ACFG_IOMUX_PAD_EIM_SDODT1 \
+ PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+ +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST
+#define ACFG_IOMUX_PAD_EIM_SDODT0 \
+ PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+ +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST
+
+#define ACFG_IOMUX_GRP_DDRPKS PAD_CTL_PUE_PULL /* imx default */
+#define ACFG_IOMUX_GRP_DRAM_B4 PAD_CTL_DRV_HIGH /* imx default */
+#define ACFG_IOMUX_GRP_INDDR PAD_CTL_DDR_INPUT_CMOS /* imx default */
+#define ACFG_IOMUX_GRP_PKEDDR PAD_CTL_PKE_ENABLE /* imx default */
+#define ACFG_IOMUX_GRP_DDR_A0 PAD_CTL_DRV_HIGH /* imx default */
+#define ACFG_IOMUX_GRP_DDR_A1 PAD_CTL_DRV_MEDIUM /* imx default */
+#define ACFG_IOMUX_GRP_DDRAPUS PAD_CTL_100K_PU /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR0 PAD_CTL_HYS_NONE /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR1 PAD_CTL_HYS_NONE /* imx default */
+#define ACFG_IOMUX_GRP_HYSDDR2 PAD_CTL_HYS_NONE /* imx default */
+#define ACFG_IOMUX_GRP_HVDDR PAD_CTL_DRV_VOT_LOW
+#define ACFG_IOMUX_GRP_HYSDDR3 PAD_CTL_HYS_NONE /* imx default */
+#define ACFG_IOMUX_GRP_DDR_SR_B0 PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_GRP_DDRAPKS PAD_CTL_PUE_PULL /* imx default */
+
+#define ACFG_IOMUX_GRP_DDR_SR_B1 PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_GRP_DDRPUS PAD_CTL_100K_PU /* imx default */
+#define ACFG_IOMUX_GRP_DDR_SR_B2 PAD_CTL_SRE_SLOW
+#define ACFG_IOMUX_GRP_PKEADDR PAD_CTL_PKE_ENABLE /* imx default */
+#define ACFG_IOMUX_GRP_DDR_SR_B4 PAD_CTL_SRE_SLOW
+
+#define ACFG_IOMUX_GRP_INMODE1 PAD_CTL_DDR_INPUT_CMOS /* imx default */
+#define ACFG_IOMUX_GRP_DRAM_B0 PAD_CTL_DRV_HIGH /* imx default */
+#define ACFG_IOMUX_GRP_DRAM_B1 PAD_CTL_DRV_HIGH /* imx default */
+
+#define ACFG_IOMUX_GRP_DDR_SR_A0 PAD_CTL_SRE_FAST/* imx default */
+
+#define ACFG_IOMUX_GRP_DRAM_B2 PAD_CTL_DRV_HIGH /* imx default */
+
+#define ACFG_IOMUX_GRP_DDR_SR_A1 PAD_CTL_SRE_FAST/* imx default */
+/* end of SDRAM IO Muxing */
+
+/* CCM Configuration */
+
+#define CONFIG_SYS_PLL_DP_CTL 0x00001332 /* use fpm_clk */
+#define CONFIG_SYS_CLKCTL_CCMR 0x00001FFF
+#define CONFIG_SYS_CLKCTL_CSR 0x0000003E
+#define CONFIG_SYS_CLKCTL_CCSR 0x00000200
+
+#define CCBDR_MASK 0x40000000
+
+#define CONFIG_SYS_CLKTL_CBCDR\
+ (CCBDR_MASK \
+ |((((ACFG_PLL1_CLK/APF_DDR_CLK)-1)&0x07)<<27) \
+ |((((ACFG_PLL2_CLK/APF_EMI_CLK)-1)&0x07)<<22) \
+ |((((ACFG_PLL2_CLK/APF_AXIB_CLK)-1)&0x07)<<19) \
+ |((((ACFG_PLL2_CLK/APF_AXIA_CLK)-1)&0x07)<<16) \
+ |((((APF_EMI_CLK/APF_NFC_CLK)-1)&0x07)<<13) \
+ |((((ACFG_PLL2_CLK/APF_AHB_CLK)-1)&0x07)<<10) \
+ |((((APF_AHB_CLK/APF_IPG_CLK)-1)&0x03)<<8) \
+ |(((((ACFG_PLL2_CLK/APF_PERCLK)/8))&0x03)<<6) \
+ |(((((ACFG_PLL2_CLK/APF_PERCLK) \
+ /((ACFG_PLL2_CLK/APF_PERCLK)/8+1))-1)&0x07)<<0)\
+ )
+
+#define CONFIG_SYS_CLKTL_CBCMR 0x000020C0
+
+#define CONFIG_SYS_CLKTL_CBCMR1 0xA5A2A020
+
+#define CONFIG_SYS_CLKTL_CSCDR1\
+ ( 0x0 \
+ |((((ACFG_PLL3_CLK/APF_ESDHC_CLK)/8)&0x07)<<19) \
+ |(((((ACFG_PLL3_CLK/APF_ESDHC_CLK) \
+ /((ACFG_PLL3_CLK/APF_ESDHC_CLK)/8+1))-1)&0x07)<<22) \
+ |((((ACFG_PLL3_CLK/APF_ESDHC_CLK)/8)&0x07)<<11) \
+ |((((APF_IPG_CLK/APF_PGC_CLK)-1)&0x07)<<14) \
+ |(((((ACFG_PLL3_CLK/APF_ESDHC_CLK) \
+ /((ACFG_PLL3_CLK/APF_ESDHC_CLK)/8+1))-1)&0x07)<<16) \
+ |((((ACFG_PLL3_CLK/APF_USB_CLK)/4)&0x07)<<6) \
+ |(((((ACFG_PLL3_CLK/APF_USB_CLK) \
+ /((ACFG_PLL3_CLK/APF_USB_CLK)/4+1))-1)&0x03)<<8) \
+ |((((ACFG_PLL2_CLK/APF_UART_CLK)/8)&0x07)<<0) \
+ |(((((ACFG_PLL2_CLK/APF_UART_CLK) \
+ /((ACFG_PLL2_CLK/APF_UART_CLK)/8+1))-1)&0x07)<<3) \
+ )
+
+/* clock cycle time with x2 for a 0.5ns accuracy */
+#define CONFIG_SYS_2XDDRCLK_LGTH (2000/APF_DDR_CLK) /* ns */
+
+#define ACFG_SDRAM_ESDMISC_REGISTER_VAL 0x000a5680
+
+#if ((2*ACFG_SDRAM_RC_DELAY)>(16*CONFIG_SYS_2XDDRCLK_LGTH))
+#define REG_FIELD_RC_VAL 0
+#else
+#define REG_FIELD_RC_VAL \
+ (((2*ACFG_SDRAM_RC_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1) \
+ /CONFIG_SYS_2XDDRCLK_LGTH)-1)
+#endif
+
+#if ((2*ACFG_SDRAM_RFC_DELAY)>(25*CONFIG_SYS_2XDDRCLK_LGTH))
+#define REG_FIELD_RFC_VAL \
+ (((2*ACFG_SDRAM_RFC_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1) \
+ /CONFIG_SYS_2XDDRCLK_LGTH/2)-10)
+#define REG_FIELD_ESDCTL_PAT 0x80820000
+#else
+#define REG_FIELD_RFC_VAL \
+ (((2*ACFG_SDRAM_RFC_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1) \
+ /CONFIG_SYS_2XDDRCLK_LGTH)-10)
+#define REG_FIELD_ESDCTL_PAT 0x80020000
+#endif
+
+/* ESDCTLx Configuration Registers: 32bits */
+#define ACFG_SDRAM_ESDCTL_REGISTER_VAL (REG_FIELD_ESDCTL_PAT\
+ | (((ACFG_SDRAM_REFRESH)&0x0F)<<28)\
+ | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\
+ | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20))
+
+#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x00000000\
+ | ((REG_FIELD_RFC_VAL&0x0F)<<28)\
+ | (((((2*ACFG_SDRAM_XSR_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1)\
+ /CONFIG_SYS_2XDDRCLK_LGTH)-25)&0x0F)<<24)\
+ | (((((2*ACFG_SDRAM_EXIT_PWD+CONFIG_SYS_2XDDRCLK_LGTH-1)\
+ /CONFIG_SYS_2XDDRCLK_LGTH)-1)&0x7)<<20)\
+ | ((ACFG_SDRAM_W2R_DELAY)<<20)\
+ | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1)\
+ /CONFIG_SYS_2XDDRCLK_LGTH)-2)&0x3)<<18)\
+ | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\
+ | (((((2*ACFG_SDRAM_RAS_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1)\
+ /CONFIG_SYS_2XDDRCLK_LGTH)-1)&0x0F)<<12)\
+ | (((((2*ACFG_SDRAM_RRD_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1)\
+ /CONFIG_SYS_2XDDRCLK_LGTH)-1)&0x3)<<10)\
+ | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<7)\
+ | (((((2*ACFG_SDRAM_RCD_DELAY+CONFIG_SYS_2XDDRCLK_LGTH-1)\
+ /CONFIG_SYS_2XDDRCLK_LGTH)-1)&0x7)<<4)\
+ | (((REG_FIELD_RC_VAL)&0x0F)<<0))
+
+#endif /* __CONFIG_H */
diff --git a/patches/buildroot/2011.05/173-u-boot-add-variable-to-check-number-of-ram-at-runtime.patch b/patches/buildroot/2011.05/173-u-boot-add-variable-to-check-number-of-ram-at-runtime.patch
new file mode 100644
index 0000000..27f2165
--- /dev/null
+++ b/patches/buildroot/2011.05/173-u-boot-add-variable-to-check-number-of-ram-at-runtime.patch
@@ -0,0 +1,23 @@
+U-Boot: Add config option to check number of RAM at runtime.
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+
+Index: buildroot/boot/u-boot/u-boot.mk
+===================================================================
+--- buildroot/boot/u-boot/u-boot.mk 2011-08-08 12:14:25.000000000 +0200
++++ buildroot/boot/u-boot/u-boot.mk 2012-02-21 00:36:06.969559196 +0100
+@@ -156,11 +156,12 @@ ifneq ($(BR2_TARGET_ARMADEUS_SDRAM_SIZE)
+ $(SED) "s,^#define CONFIG_SYS_SDRAM_MBYTE_SYZE.*,#define CONFIG_SYS_SDRAM_MBYTE_SYZE $(BR2_TARGET_ARMADEUS_SDRAM_SIZE),g;"\
+ $(U_BOOT_INC_CONF_FILE)
+ endif
+-ifneq ($(BR2_TARGET_ARMADEUS_NR_SDRAM),)
++ifneq ($(strip $(BR2_TARGET_ARMADEUS_NR_SDRAM)),"1")
+ $(SED) "s,^#define CONFIG_NR_DRAM_BANKS.*,#define CONFIG_NR_DRAM_BANKS $(BR2_TARGET_ARMADEUS_NR_SDRAM),g;"\
+ $(U_BOOT_INC_CONF_FILE)
+ $(SED) "s,^#define CONFIG_SYS_NR_DRAM_BANKS.*,#define CONFIG_SYS_NR_DRAM_BANKS $(BR2_TARGET_ARMADEUS_NR_SDRAM),g;"\
+ $(U_BOOT_INC_CONF_FILE)
++ $(call insert_define, CONFIG_NR_DRAM_POPULATED, $(BR2_TARGET_ARMADEUS_NR_SDRAM))
+ endif
+ touch $@
+
diff --git a/patches/u-boot/2011.12/401-apf51.patch b/patches/u-boot/2011.12/401-apf51.patch
index cd68739..9818093 100644
--- a/patches/u-boot/2011.12/401-apf51.patch
+++ b/patches/u-boot/2011.12/401-apf51.patch
@@ -2,7 +2,7 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ u-boot-custom/board/armadeus/apf51/apf51.c 2012-01-12 17:19:58.434303119 +0100
-@@ -0,0 +1,1221 @@
+@@ -0,0 +1,1242 @@
+/*
+ * (C) Copyright 2010-2012 Eric Jarrige, Armadeus Project
+ *
@@ -72,27 +72,48 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
+ return amount_loaded;
+}
+
-+int dram_init(void)
++u32 get_board_rev(void)
+{
-+ u32 size1, size2 = 0;
+
-+ size1 = get_ram_size((void *)CSD0_BASE_ADDR, PHYS_SDRAM_1_SIZE);
-+#if ( CONFIG_NR_DRAM_BANKS > 1 )
-+ size2 = get_ram_size((void *)CSD1_BASE_ADDR, PHYS_SDRAM_2_SIZE);
-+#endif
++ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
++
++ return readl(&iim->bank[1].fuse_regs[0x0f]) & 0x1f;
++}
++
++int get_num_ram_bank(void)
++{
++ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
++ int nr_dram_banks = 1;
++
++ if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
++ nr_dram_banks += readl(&iim->bank[1].fuse_regs[0x10]) & 0x01;
++ else
++ nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
++
++ return nr_dram_banks;
++}
++
++int dram_init(void)
++{
++
++ gd->ram_size = get_ram_size((void *)CSD0_BASE_ADDR, PHYS_SDRAM_1_SIZE);
++ if (get_num_ram_bank() > 1) {
++ gd->ram_size +=
++ get_ram_size((void *)CSD1_BASE_ADDR, PHYS_SDRAM_2_SIZE);
++ }
+
-+ gd->ram_size = size1 + size2;
+ return 0;
+}
+
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CSD0_BASE_ADDR;
-+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-+#if ( CONFIG_NR_DRAM_BANKS > 1 )
-+ gd->bd->bi_dram[1].start = CSD1_BASE_ADDR;
-+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
-+#endif
++ gd->bd->bi_dram[0].size = gd->ram_size / get_num_ram_bank();
++ if (CONFIG_NR_DRAM_BANKS > 1) {
++ gd->bd->bi_dram[1].start = CSD1_BASE_ADDR;
++ gd->bd->bi_dram[1].size = gd->ram_size -gd->bd->bi_dram[0].size;
++ }
++
+}
+
+void setup_usb(void)
@@ -989,7 +1010,7 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
+
+int checkboard(void)
+{
-+ printf("Board: Armadeus APF51\n");
++ printf("Board: Armadeus APF51 revision %d\n", get_board_rev());
+ return 0;
+}
+
@@ -1183,7 +1204,7 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
+ ACFG_SDRAM_ESDCTL_REGISTER_VAL);
+ printf(dcd_item, i++, 4, &esdctl->esdcfg0,
+ ACFG_SDRAM_ESDCFG_REGISTER_VAL);
-+#if (CONFIG_NR_DRAM_BANKS > 1)
++
+ printf(dcd_item, i++, 4, &esdctl->esdctl1,
+ (ACFG_SDRAM_ESDCTL_REGISTER_VAL & 0x8FFFFFFF));
+ printf(dcd_item, i++, 4, &esdctl->esdscr, DRR_PRECHARGE_CMD(1, 0));
@@ -1198,7 +1219,7 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
+ ACFG_SDRAM_ESDCTL_REGISTER_VAL);
+ printf(dcd_item, i++, 4, &esdctl->esdcfg1,
+ ACFG_SDRAM_ESDCFG_REGISTER_VAL);
-+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
++
+ printf(dcd_item, i++, 4, &esdctl->esdmisc,
+ ACFG_SDRAM_ESDMISC_REGISTER_VAL);
+ printf(dcd_item, i++, 4, &esdctl->esdscr, 0x00000000);
diff --git a/patches/u-boot/2011.12/409-apf51-nand-spl.patch b/patches/u-boot/2011.12/409-apf51-nand-spl.patch
index e9235bb..fdbae9f 100644
--- a/patches/u-boot/2011.12/409-apf51-nand-spl.patch
+++ b/patches/u-boot/2011.12/409-apf51-nand-spl.patch
@@ -50,7 +50,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/flash_header.S
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ u-boot-2010.03/nand_spl/board/armadeus/apf51/flash_header.S 2011-01-05 18:11:55.000000000 +0100
-@@ -0,0 +1,210 @@
+@@ -0,0 +1,208 @@
+/*
+ *
+ * Copyright (c) 2010-2012 Eric Jarrige, Armadeus Project
@@ -223,7 +223,6 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/flash_header.S
+ ACFG_SDRAM_ESDCFG_REGISTER_VAL)
+
+/* Init DDR on CS1 */
-+#if (CONFIG_NR_DRAM_BANKS > 1)
+MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, \
+ (ACFG_SDRAM_ESDCTL_REGISTER_VAL&0x8FFFFFFF))
+MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, DRR_PRECHARGE_CMD(1, 0))
@@ -238,7 +237,6 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/flash_header.S
+ ACFG_SDRAM_ESDCTL_REGISTER_VAL)
+MXC_DCD_ITEM(62, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, \
+ ACFG_SDRAM_ESDCFG_REGISTER_VAL)
-+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
+
+MXC_DCD_ITEM(63, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, \
+ ACFG_SDRAM_ESDMISC_REGISTER_VAL)
hooks/post-receive
--
armadeus
|
