[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-68-g9deef89
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-68-g9deef89
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From: jorasse <jo...@us...> - 2012-02-20 21:50:40
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 9deef899fd3d76d87802e264989f1709cacf1308 (commit)
from bcaff153460985f4a2c1eb6b40ef60658326d2e2 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9deef899fd3d76d87802e264989f1709cacf1308
Author: Eric Jarrige <eri...@ar...>
Date: Mon Feb 20 22:50:07 2012 +0100
[UBOOT] apf27: add fpga patch to release 2011.12
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf27/apf27-u-boot-2011.12.h | 30 +-
...-Add-support-for-the-armadeus-apf27-board.patch | 318 +++++++++++++++++++-
.../2011.12/303-Remove-useless-code-in-apf27.patch | 76 -----
...6-Debug-nand-this-patch-should-be-removed.patch | 79 -----
4 files changed, 331 insertions(+), 172 deletions(-)
delete mode 100644 patches/u-boot/2011.12/303-Remove-useless-code-in-apf27.patch
delete mode 100644 patches/u-boot/2011.12/306-Debug-nand-this-patch-should-be-removed.patch
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
index 33f83e8..148e345 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
@@ -80,16 +80,14 @@
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
-// #define CONFIG_CMD_DATE /* support for RTC, date/time...*/
+//#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_DIAG /* Diagnostics */
//#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
-#define CONFIG_CMD_ELF /* bootelf, bootvx */
#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
//#define CONFIG_CMD_I2C /* I2C serial bus support */
-#undef CONFIG_CMD_IMLS /* List all found images */
+#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_CMD_IMMAP /* IMMR dump support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MII /* MII support */
@@ -224,7 +222,8 @@
"unlock_regs=mw 10000008 0; mw 10020008 0\0" \
#define CONFIG_BOOTCOMMAND "run ubifsboot"
-#define CONFIG_SYS_AUTOLOAD "no"
+#define CFG_AUTOLOAD "no"
+#define CFG_DIRECT_FLASH_TFTP
#define CONFIG_MACH_TYPE MACH_TYPE_APF27
#define CONFIG_BOOT_PARAMS_ADDR 0xa0000100
@@ -267,7 +266,7 @@
#undef CONFIG_VFD /* do not send framebuffer setup */
/*
- * Malloc pool need to host env + 128 Kb reserve for other allocations.
+ * Malloc pool need to host env + 512 Kb reserve for other allocations.
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10) )
@@ -358,7 +357,7 @@
/*
* SDRAM definition parameter
*/
-#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
@@ -640,12 +639,11 @@
/*-----------------------------------------------------------------------
* FPGA stuff
*/
-// #define CONFIG_FPGA CONFIG_SYS_SPARTAN3
+#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
//#define FPGA_DEBUG
-#define CONFIG_FPGA_COUNT 2
+#define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_SPARTAN6
#define CONFIG_SYS_FPGA_WAIT 20000 /* 20 ms */
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
@@ -669,14 +667,14 @@
* I2C bus
*/
-// #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+//#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-// #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-// #define CONFIG_SYS_I2C_SLAVE 0x7F
+//#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+//#define CONFIG_SYS_I2C_SLAVE 0x7F
-// #define CONFIG_I2C_CMD_TREE
-// #define CONFIG_I2C_MULTI_BUS 2
-// #define CONFIG_SYS_I2C_NOPROBES { }
+//#define CONFIG_I2C_CMD_TREE
+//#define CONFIG_I2C_MULTI_BUS 2
+//#define CONFIG_SYS_I2C_NOPROBES { }
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
diff --git a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
index 45dd049..577b8d1 100644
--- a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -51,7 +51,7 @@ index 0000000..2a0f7d8
+
+LIB = $(obj)lib$(BOARD).o
+
-+COBJS := apf27.o
++COBJS := apf27.o fpga.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
@@ -745,4 +745,320 @@ index 66c27a4..f68c3a7 100644
at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
1.7.4.4
+Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/board/armadeus/apf27/fpga.c 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,267 @@
++/*
++ * (C) Copyright 2002-2008
++ * Eric Jarrige <eri...@ar...>
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++
++#if defined(CONFIG_FPGA)
++
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include <command.h>
++#include <config.h>
++#include "fpga.h"
++#include <spartan3.h>
++
++#define GPIO_PORT(x) ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT)
++#define GPIO_SET(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | (1 << (x & GPIO_PIN_MASK)), \
++ &gpregs->port[GPIO_PORT(x)].dr)
++//(DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
++#define GPIO_CLEAR(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) & ~(1 << (x & GPIO_PIN_MASK)), \
++ &gpregs->port[GPIO_PORT(x)].dr)
++//(DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
++#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
++#define GPIO_READ(x) ((readl(&gpregs->port[GPIO_PORT(x)].ssr) & (1 << (x & GPIO_PIN_MASK))) \
++ >> (x & GPIO_PIN_MASK))
++//((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK)))>> (x & GPIO_PIN_MASK))
++#ifdef FPGA_DEBUG
++#define PRINTF(fmt,args...) printf (fmt ,##args)
++#else
++#define PRINTF(fmt,args...)
++#endif
++
++/* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
++ fpga_pre_fn,
++ fpga_pgm_fn,
++ fpga_init_fn,
++ NULL,
++ fpga_done_fn,
++ fpga_clk_fn,
++ fpga_cs_fn,
++ fpga_wr_fn,
++ fpga_rdata_fn,
++ fpga_wdata_fn,
++ fpga_busy_fn,
++ fpga_abort_fn,
++ fpga_post_fn,
++};
++
++Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++ {Xilinx_Spartan3,
++ slave_parallel,
++ 1196128l/8,
++ (void *) &fpga_fns,
++ 0}
++};
++
++/*
++ * nitialize GPIO port B before download
++ */
++int
++fpga_pre_fn (int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ // Initialize GPIO pins
++ GPIO_SET(CONFIG_SYS_FPGA_PWR);
++ imx_gpio_mode (CONFIG_SYS_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_SUSPEND | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ GPIO_SET(CONFIG_SYS_FPGA_RESET);
++ imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ GPIO_SET(CONFIG_SYS_FPGA_PRG);
++ GPIO_SET(CONFIG_SYS_FPGA_CLK);
++ GPIO_SET(CONFIG_SYS_FPGA_RW);
++ GPIO_SET(CONFIG_SYS_FPGA_CS);
++ GPIO_CLEAR(CONFIG_SYS_FPGA_SUSPEND);
++// GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
++ GPIO_CLEAR(CONFIG_SYS_FPGA_PWR);
++
++ return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int
++fpga_pgm_fn (int assert, int flush, int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA PROGRAM %s", __FUNCTION__, __LINE__,
++ assert?"high":"low");
++ GPIO_WRITE( CONFIG_SYS_FPGA_PRG, !assert);
++ return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int
++fpga_clk_fn (int assert_clk, int flush, int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA CLOCK %s", __FUNCTION__, __LINE__,
++ assert_clk?"high":"low");
++ GPIO_WRITE( CONFIG_SYS_FPGA_CLK, !assert_clk);
++ return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
++ * asserted (low).
++ */
++int
++fpga_init_fn (int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ int value;
++ PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
++ value = GPIO_READ(CONFIG_SYS_FPGA_INIT);
++ //printf("init value read %x",value);
++#ifdef CONFIG_SYS_FPGA_IS_PROTO
++ return value;
++#else
++ return !value;
++#endif
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int
++fpga_done_fn (int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
++ GPIO_READ(CONFIG_SYS_FPGA_DONE)?"high":"low");
++ return(GPIO_READ(CONFIG_SYS_FPGA_DONE)?FPGA_SUCCESS:FPGA_FAIL);
++}
++
++/*
++ * Set the FPGA's wr line to the specified level
++ */
++int
++fpga_wr_fn (int assert_write, int flush, int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA RW... %s ", __FUNCTION__, __LINE__,
++ assert_write?"high":"low");
++ GPIO_WRITE( CONFIG_SYS_FPGA_RW, !assert_write);
++ return assert_write;
++}
++
++int
++fpga_cs_fn (int assert_cs, int flush, int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA CS %s ", __FUNCTION__, __LINE__,
++ assert_cs?"high":"low");
++ GPIO_WRITE( CONFIG_SYS_FPGA_CS, !assert_cs);
++ return assert_cs;
++}
++
++int
++fpga_rdata_fn ( unsigned char *data, int cookie )
++{
++ PRINTF ("%s:%d: FPGA READ DATA %02X ", __FUNCTION__, __LINE__,
++ *((char*)CONFIG_SYS_FPGA_RDATA));
++ *data = (unsigned char)((*((unsigned short*)CONFIG_SYS_FPGA_RDATA))&0x00FF);
++ return *data;
++}
++
++int
++fpga_wdata_fn ( unsigned char data, int cookie )
++{
++ PRINTF ("%s:%d: FPGA WRITE DATA %02X ", __FUNCTION__, __LINE__,
++ data);
++ *((unsigned short*)CONFIG_SYS_FPGA_WDATA) = data;
++ return data;
++}
++
++int
++fpga_abort_fn ( int cookie )
++{
++ return cookie;
++}
++
++
++int
++fpga_busy_fn ( int cookie )
++{
++ return 1;
++}
++
++int
++fpga_post_fn (int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA POST ", __FUNCTION__, __LINE__);
++
++ imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_PF | GPIO_PUEN);
++ imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_PF | GPIO_PUEN);
++ imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_PF | GPIO_PUEN);
++ GPIO_SET(CONFIG_SYS_FPGA_PRG);
++ GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
++ imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ return cookie;
++}
++
++/*
++ * Initialize the fpga. Return 1 on success, 0 on failure.
++ */
++int
++APF27_init_fpga (u_char * buffer, size_t size)
++{
++ char *autoload = getenv ("firmware_autoload");
++
++ int i,lout=0;
++
++ fpga_init();
++
++ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++ PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
++ fpga_add (fpga_xilinx, &fpga[i]);
++ }
++
++ if ((size >= fpga[0].size) && ( autoload ) && (0 == strcmp(autoload, "1"))) {
++ if (FPGA_SUCCESS != fpga_load( 0, (void *)buffer, size )) {
++ lout = 1;
++ printf("Firmware download failed!\n");
++ }
++ else
++ printf("Firmware successfully programmed\n");
++ }
++ return lout;
++}
++
++#endif /* CONFIG_FPGA */
+Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/board/armadeus/apf27/fpga.h 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,39 @@
++/*
++ * (C) Copyright 2002-2008
++ * Eric Jarrige <eri...@ar...>
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++extern int APF27_init_fpga (u_char * buffer, size_t size);
++
++extern int fpga_pre_fn (int cookie);
++extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
++extern int fpga_cs_fn (int assert_cs, int flush, int cookie);
++extern int fpga_init_fn (int cookie);
++extern int fpga_done_fn (int cookie);
++extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn (int assert_write, int flush, int cookie);
++extern int fpga_rdata_fn ( unsigned char *data, int cookie );
++extern int fpga_wdata_fn ( unsigned char data, int cookie );
++extern int fpga_abort_fn (int cookie);
++extern int fpga_post_fn (int cookie);
++extern int fpga_busy_fn (int cookie);
diff --git a/patches/u-boot/2011.12/303-Remove-useless-code-in-apf27.patch b/patches/u-boot/2011.12/303-Remove-useless-code-in-apf27.patch
deleted file mode 100644
index d9ed98d..0000000
--- a/patches/u-boot/2011.12/303-Remove-useless-code-in-apf27.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From 7d5eba120d72f2ea5e3a946fd2c87b021759f21b Mon Sep 17 00:00:00 2001
-From: Philippe Reynes <tr...@ya...>
-Date: Tue, 4 Oct 2011 19:30:15 +0200
-Subject: [PATCH 3/6] Remove useless code in apf27
-
----
- board/armadeus/apf27/apf27.c | 45 ------------------------------------------
- 1 files changed, 0 insertions(+), 45 deletions(-)
-
-diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
-index e08b7a2..d4f2082 100644
---- a/board/armadeus/apf27/apf27.c
-+++ b/board/armadeus/apf27/apf27.c
-@@ -27,31 +27,6 @@
-
- DECLARE_GLOBAL_DATA_PTR;
-
--static int read_firmware (size_t offset, size_t end, u_char * buf)
--{
-- size_t amount_loaded = 0;
-- size_t blocksize;
--
-- u_char *char_ptr;
--
-- blocksize = nand_info[0].erasesize;
--
-- while (offset < end) {
-- if (nand_block_isbad(&nand_info[0], offset)) {
-- offset += blocksize;
-- } else {
-- char_ptr = &buf[amount_loaded];
-- if (nand_read(&nand_info[0], offset, &blocksize, char_ptr))
-- return 1;
-- offset += blocksize;
-- amount_loaded += blocksize;
-- }
-- }
--
-- return amount_loaded;
--}
--
--
- static int apf27_devices_init(void)
- {
- int i;
-@@ -141,27 +116,7 @@ int
- misc_init_r (void)
- {
- char *s;
-- u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
-- size_t end = 0;
-- size_t size = 0;
- size_t offset = -1;
-- char *autoload = getenv ("firmware_autoload");
--
--#if defined(CONFIG_FPGA)
-- /* init and download fpga */
-- if (( autoload ) && (0 == strcmp(autoload, "1"))) {
-- if ((s = getenv("firmware_offset")) != NULL) {
-- offset = simple_strtoul(s, NULL, 16);
-- }
-- if ((s = getenv("firmware_len")) != NULL) {
-- end = offset + simple_strtoul(s, NULL, 16);
-- }
-- if ((-1 != offset) && (offset != end)) {
-- size = read_firmware (offset, end, firmware_buffer);
-- }
-- }
-- APF27_init_fpga (firmware_buffer, size);
--#endif
-
- /* detect compatibility issue of environment version */
- s = getenv ("env_version");
---
-1.7.4.4
-
diff --git a/patches/u-boot/2011.12/306-Debug-nand-this-patch-should-be-removed.patch b/patches/u-boot/2011.12/306-Debug-nand-this-patch-should-be-removed.patch
deleted file mode 100644
index 2ba4946..0000000
--- a/patches/u-boot/2011.12/306-Debug-nand-this-patch-should-be-removed.patch
+++ /dev/null
@@ -1,79 +0,0 @@
-From 8aa4ee39d003d442cc9f01ea487dcce190274cfc Mon Sep 17 00:00:00 2001
-From: Philippe Reynes <tr...@ya...>
-Date: Wed, 25 Jan 2012 20:36:42 +0100
-Subject: [PATCH 6/6] Debug nand, this patch should be removed
-
----
- drivers/mtd/nand/mxc_nand.c | 22 +++++++++++++++++++++-
- drivers/mtd/nand/nand_base.c | 2 ++
- 2 files changed, 31 insertions(+), 9 deletions(-)
-
-diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
-index 35e89a0..929e228 100644
---- a/drivers/mtd/nand/mxc_nand.c
-+++ b/drivers/mtd/nand/mxc_nand.c
-@@ -193,7 +193,8 @@ static struct mxc_nand_host mxc_host;
- static struct mxc_nand_host *host = &mxc_host;
-
- /* Define delays in microsec for NAND device operations */
--#define TROP_US_DELAY 2000
-+#define TROP_US_DELAY 10000
-+
- /* Macros to get byte and bit positions of ECC */
- #define COLPOS(x) ((x) >> 3)
- #define BITPOS(x) ((x) & 0xf)
-@@ -326,6 +327,21 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
- {
- MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
-
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: bufsize = 0x%04x\n", __func__, readw(&host->regs->nfc_buf_size));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_buf_addr = 0x%04x\n", __func__, readw(&host->regs->nfc_buf_addr));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_flash_addr = 0x%04x\n", __func__, readw(&host->regs->nfc_flash_addr));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_flash_cmd = 0x%04x\n", __func__, readw(&host->regs->nfc_flash_cmd));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_config = 0x%04x\n", __func__, readw(&host->regs->nfc_config));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_ecc_status_result = 0x%04x\n", __func__, readw(&host->regs->nfc_ecc_status_result));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_rsltmain_area = 0x%04x\n", __func__, readw(&host->regs->nfc_rsltmain_area));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_rsltspare_area = 0x%04x\n", __func__, readw(&host->regs->nfc_rsltspare_area));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_wrprot = 0x%04x\n", __func__, readw(&host->regs->nfc_wrprot));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_unlockstart_blkaddr = 0x%04x\n", __func__, readw(&host->regs->nfc_unlockstart_blkaddr));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_unlockend_blkaddr = 0x%04x\n", __func__, readw(&host->regs->nfc_unlockend_blkaddr));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_nf_wrprst = 0x%04x\n", __func__, readw(&host->regs->nfc_nf_wrprst));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: config1 = 0x%04x\n", __func__, readw(&host->regs->nfc_config1));
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: config2 = 0x%04x\n", __func__, readw(&host->regs->nfc_config2));
-+
- writew(cmd, &host->regs->nfc_flash_cmd);
- writew(NFC_CMD, &host->regs->nfc_config2);
-
-@@ -1308,6 +1324,8 @@ int board_nand_init(struct nand_chip *this)
- uint16_t tmp;
- int err = 0;
-
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s(this = %p)\n", __func__, this);
-+
- /* structures must be linked */
- mtd = &host->mtd;
- mtd->priv = this;
-@@ -1391,6 +1409,8 @@ int board_nand_init(struct nand_chip *this)
- if (is_16bit_nand())
- this->options |= NAND_BUSWIDTH_16;
-
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: this->options = %x\n", __func__, this->options);
-+
- #ifdef CONFIG_SYS_NAND_LARGEPAGE
- host->pagesize_2k = 1;
- this->ecc.layout = &nand_hw_eccoob2k;
-diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
-index 27f6c77..6107b8b 100644
---- a/drivers/mtd/nand/nand_base.c
-+++ b/drivers/mtd/nand/nand_base.c
-@@ -2578,6 +2578,8 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
- tmp_manf = chip->read_byte(mtd);
- tmp_id = chip->read_byte(mtd);
-
-+ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: manf = %02x, id = %02x\n", __func__, tmp_manf, tmp_id);
-+
- if (tmp_manf != *maf_id || tmp_id != *dev_id) {
- printk(KERN_INFO "%s: second ID read did not match "
- "%02x,%02x against %02x,%02x\n", __func__,
-1.7.4.4
-
hooks/post-receive
--
armadeus
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