[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-51-g0b7f2f2
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-51-g0b7f2f2
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From: jorasse <jo...@us...> - 2012-02-13 21:54:51
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- Log -----------------------------------------------------------------
commit 0b7f2f2d61d28989b6ada5d2c7da5f4c5f221925
Author: Eric Jarrige <eri...@ar...>
Date: Mon Feb 13 22:54:10 2012 +0100
[UBOOT] apf27: import mx27 NAND SPL from U-Boot 2010.03
commit dce448662a155fe7a716a9b8da93b17326b5264d
Author: Philippe Reynes <tr...@ya...>
Date: Mon Feb 13 22:51:21 2012 +0100
[UBOOT] apf27:[PATCH 6/6] Debug nand, this patch should be removed
commit 69f54d1f9df08c8ae7148367f5a976773f4a28b9
Author: Philippe Reynes <tr...@ya...>
Date: Mon Feb 13 22:50:33 2012 +0100
[UBOOT] apf27:[PATCH 5/6] Define uart1 for the console
commit 7ef82f0f19b3c2304a0e1a1f300a29d7ebe3356c
Author: Philippe Reynes <tr...@ya...>
Date: Mon Feb 13 22:49:54 2012 +0100
[UBOOT] apf27:[PATCH 4/6] Add type for apf27
commit d6eee0236270b6c5a889cd6cf442f81465003784
Author: Philippe Reynes <tr...@ya...>
Date: Mon Feb 13 22:49:23 2012 +0100
[UBOOT] apf27:[PATCH 3/6] Remove useless code in apf27
commit 6dd0e4e1c5abfc334a78f0981d9ac6a85ce34e9d
Author: Philippe Reynes <tr...@ya...>
Date: Mon Feb 13 22:48:02 2012 +0100
[UBOOT] apf27:[PATCH 2/6] Add support for the armadeus apf27 board
commit 760e53ea5896de8c08ac5769f1a94ed66d04c34b
Author: Philippe Reynes <tr...@ya...>
Date: Mon Feb 13 22:31:52 2012 +0100
[UBOOT] apf27:[PATCH 1/6] Add GPIO Module and I/O Multiplexer constant for mx27
-----------------------------------------------------------------------
Summary of changes:
...dule-and-I-O-Multiplexer-constant-for-mx2.patch | 238 +++++++
...-Add-support-for-the-armadeus-apf27-board.patch | 726 ++++++++++++++++++++
.../2011.12/303-Remove-useless-code-in-apf27.patch | 76 ++
.../u-boot/2011.12/304-Add-type-for-apf27.patch | 24 +
.../2011.12/305-Define-uart1-for-the-console.patch | 24 +
...6-Debug-nand-this-patch-should-be-removed.patch | 150 ++++
patches/u-boot/2011.12/310-apf27-nand-spl.patch | 721 +++++++++++++++++++
7 files changed, 1959 insertions(+), 0 deletions(-)
create mode 100644 patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
create mode 100644 patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
create mode 100644 patches/u-boot/2011.12/303-Remove-useless-code-in-apf27.patch
create mode 100644 patches/u-boot/2011.12/304-Add-type-for-apf27.patch
create mode 100644 patches/u-boot/2011.12/305-Define-uart1-for-the-console.patch
create mode 100644 patches/u-boot/2011.12/306-Debug-nand-this-patch-should-be-removed.patch
create mode 100644 patches/u-boot/2011.12/310-apf27-nand-spl.patch
diff --git a/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch b/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
new file mode 100644
index 0000000..c60fcba
--- /dev/null
+++ b/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
@@ -0,0 +1,238 @@
+From c454b2c2ed3a4be1a0809c0f0fa49f46559e1fa6 Mon Sep 17 00:00:00 2001
+From: Philippe Reynes <tr...@ya...>
+Date: Sun, 25 Sep 2011 11:22:00 +0200
+Subject: [PATCH 1/6] Add GPIO Module and I/O Multiplexer constant for mx27
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ arch/arm/include/asm/arch-mx27/imx-regs.h | 216 +++++++++++++++++++++++++++++
+ 1 files changed, 216 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
+index ced5b2a..f1c0ce7 100644
+--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
+@@ -522,4 +522,220 @@ struct fuse_bank0_regs {
+ #define IIM_ERR_SNSE (1 << 2)
+ #define IIM_ERR_PARITYE (1 << 1)
+
++/* IIM Control Registers */
++#define IIM_BANK_AREA IMX_IIM_BASE + 0x800
++#define IIM_BANK_REG(x,y) (IIM_BANK_AREA + 0x400 * x + (y<<2))
++
++# ifdef __ASSEMBLY__
++# define __REG(x) (x)
++# define __REG16(x) (x)
++# define __REG2(x,y) ((x)+(y))
++
++/*
++ * GPIO Module and I/O Multiplexer
++ */
++#define PORTA 0
++#define PORTB 1
++#define PORTC 2
++#define PORTD 3
++#define PORTE 4
++#define PORTF 5
++
++#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00)
++#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04)
++#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00)
++#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04)
++
++/* System Control */
++#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14)
++#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18)
++#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C)
++#define DSCR1 __REG(IMX_SYSTEM_CTL_BASE + 0x20)
++#define DSCR2 __REG(IMX_SYSTEM_CTL_BASE + 0x24)
++#define DSCR3 __REG(IMX_SYSTEM_CTL_BASE + 0x28)
++#define DSCR4 __REG(IMX_SYSTEM_CTL_BASE + 0x2C)
++#define DSCR5 __REG(IMX_SYSTEM_CTL_BASE + 0x30)
++#define DSCR6 __REG(IMX_SYSTEM_CTL_BASE + 0x34)
++#define DSCR7 __REG(IMX_SYSTEM_CTL_BASE + 0x38)
++#define DSCR8 __REG(IMX_SYSTEM_CTL_BASE + 0x3C)
++#define DSCR9 __REG(IMX_SYSTEM_CTL_BASE + 0x40)
++#define DSCR10 __REG(IMX_SYSTEM_CTL_BASE + 0x44)
++#define DSCR11 __REG(IMX_SYSTEM_CTL_BASE + 0x48)
++#define DSCR12 __REG(IMX_SYSTEM_CTL_BASE + 0x4C)
++#define DSCR13 __REG(IMX_SYSTEM_CTL_BASE + 0x50)
++#define PSCR __REG(IMX_SYSTEM_CTL_BASE + 0x54)
++#define PMCR __REG(IMX_SYSTEM_CTL_BASE + 0x58)
++#define DCVR0 __REG(IMX_SYSTEM_CTL_BASE + 0x60)
++#define DCVR1 __REG(IMX_SYSTEM_CTL_BASE + 0x64)
++#define DCVR2 __REG(IMX_SYSTEM_CTL_BASE + 0x68)
++#define DCVR3 __REG(IMX_SYSTEM_CTL_BASE + 0x6C)
++
++/* Chip Select Registers */
++#define CS0U __REG(IMX_WEIM_BASE + 0x00) /* Chip Select 0 Upper Register */
++#define CS0L __REG(IMX_WEIM_BASE + 0x04) /* Chip Select 0 Lower Register */
++#define CS0A __REG(IMX_WEIM_BASE + 0x08) /* Chip Select 0 Addition Register */
++#define CS1U __REG(IMX_WEIM_BASE + 0x10) /* Chip Select 1 Upper Register */
++#define CS1L __REG(IMX_WEIM_BASE + 0x14) /* Chip Select 1 Lower Register */
++#define CS1A __REG(IMX_WEIM_BASE + 0x18) /* Chip Select 1 Addition Register */
++#define CS2U __REG(IMX_WEIM_BASE + 0x20) /* Chip Select 2 Upper Register */
++#define CS2L __REG(IMX_WEIM_BASE + 0x24) /* Chip Select 2 Lower Register */
++#define CS2A __REG(IMX_WEIM_BASE + 0x28) /* Chip Select 2 Addition Register */
++#define CS3U __REG(IMX_WEIM_BASE + 0x30) /* Chip Select 3 Upper Register */
++#define CS3L __REG(IMX_WEIM_BASE + 0x34) /* Chip Select 3 Lower Register */
++#define CS3A __REG(IMX_WEIM_BASE + 0x38) /* Chip Select 3 Addition Register */
++#define CS4U __REG(IMX_WEIM_BASE + 0x40) /* Chip Select 4 Upper Register */
++#define CS4L __REG(IMX_WEIM_BASE + 0x44) /* Chip Select 4 Lower Register */
++#define CS4A __REG(IMX_WEIM_BASE + 0x48) /* Chip Select 4 Addition Register */
++#define CS5U __REG(IMX_WEIM_BASE + 0x50) /* Chip Select 5 Upper Register */
++#define CS5L __REG(IMX_WEIM_BASE + 0x54) /* Chip Select 5 Lower Register */
++#define CS5A __REG(IMX_WEIM_BASE + 0x58) /* Chip Select 5 Addition Register */
++#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */
++
++/* SDRAM Controller registers */
++#define ESDCTL0 __REG(IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */
++#define ESDCFG0 __REG(IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
++#define ESDCTL1 __REG(IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */
++#define ESDCFG1 __REG(IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
++#define ESDMISC __REG(IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */
++
++/* PLL registers */
++#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
++#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
++#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */
++#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */
++#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
++#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */
++#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */
++#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */
++#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */
++#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */
++#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */
++
++#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8)
++#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8)
++#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8)
++#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8)
++#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8)
++#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8)
++#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8)
++#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8)
++#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8)
++#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8)
++#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8)
++#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8)
++#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8)
++#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8)
++#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8)
++#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8)
++#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8)
++
++ /* Macros to get byte and bit positions of ECC
++ */
++#define COLPOS(x) ((x) >> 4)
++#define BITPOS(x) ((x)& 0xf)
++
++/**
++ * Memory areas of the NFC
++ */
++#define IMX_NFC_BASE (0xD8000000)
++#define IMX_NFC_MAIN_AREA0 (0xD8000000)
++#define IMX_NFC_MAIN_AREA1 (0xD8000200)
++#define IMX_NFC_SPARE_AREA0 (0xD8000800)
++#define IMX_NFC_REGS (0xD8000E00)
++
++/*
++ * NFC registers address offest
++ */
++#define NFC_OFFSET_BUFSIZE (0x00) /* Internal SRAM Size */
++#define NFC_OFFSET_BLCK_ADD_LOCK (0x02) /* NAND Flash Block Address for Lock Check */
++#define NFC_OFFSET_BUF_ADDR (0x04) /* Buffer Number for Page Data Transfer To/
++ From Flash Memory */
++#define NFC_OFFSET_FLASH_ADDR (0x06) /* NAND Flash Address */
++#define NFC_OFFSET_FLASH_CMD (0x08) /* NAND Flash Command */
++#define NFC_OFFSET_CONFIG (0x0A) /* NFC Internal Buffer Lock Control */
++#define NFC_OFFSET_ECC_STATUS_RESULT (0x0C) /* Controller Status/Result of Flash Operation */
++#define NFC_OFFSET_ECC_RSLT_MAIN_AREA (0x0E) /* ECC Error Position of Main Area Data Error */
++#define NFC_OFFSET_ECC_RSLT_SPARE_AREA (0x10) /* ECC Error Position of Spare Area Data Error */
++#define NFC_OFFSET_WRPROT (0x12) /* Nand Flash Write Protection */
++#define NFC_OFFSET_UNLOCKSTART_BLKADDR (0x14) /* Start Address for Write Protection Unlock */
++#define NFC_OFFSET_UNLOCKEND_BLKADDR (0x16) /* End Address for Write Protection Unlock */
++#define NFC_OFFSET_WRPR_STAT (0x18) /* Current Nand Flash Write Protection Status */
++#define NFC_OFFSET_CONFIG1 (0x1A) /* Nand Flash Operation Configuration 1 */
++#define NFC_OFFSET_CONFIG2 (0x1C) /* Nand Flash Operation Configuration 2 */
++
++/*
++ * NFC registers
++ */
++ /* Internal SRAM Size */
++#define NFC_BUFSIZE __REG16(IMX_NFC_REGS + NFC_OFFSET_BUFSIZE)
++ /* NAND Flash Block Address for Lock Check */
++#define NFC_BLCK_ADD_LOCK __REG16(IMX_NFC_REGS + NFC_OFFSET_BLCK_ADD_LOCK)
++ /* Buffer Number for Page Data Transfer To From Flash Memory */
++#define NFC_BUF_ADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_BUF_ADDR)
++ /* NAND Flash Address */
++#define NFC_FLASH_ADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_FLASH_ADDR)
++ /* NAND Flash Command */
++#define NFC_FLASH_CMD __REG16(IMX_NFC_REGS + NFC_OFFSET_FLASH_CMD)
++ /* NFC Internal Buffer Lock Control */
++#define NFC_CONFIG __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG)
++ /* Controller Status/Result of Flash Operation */
++#define NFC_ECC_STATUS_RESULT __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_STATUS_RESULT)
++ /* ECC Error Position of Main Area Data Error */
++#define NFC_ECC_RSLT_MAIN_AREA __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_RSLT_MAIN_AREA)
++ /* ECC Error Position of Spare Area Data Error */
++#define NFC_ECC_RSLT_SPARE_AREA __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_RSLT_SPARE_AREA)
++ /* Nand Flash Write Protection */
++#define NFC_WRPROT __REG16(IMX_NFC_REGS + NFC_OFFSET_WRPROT)
++ /* Start Address for Write Protection Unlock */
++#define NFC_UNLOCKSTART_BLKADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_UNLOCKSTART_BLKADDR)
++ /* End Address for Write Protection Unlock */
++#define NFC_UNLOCKEND_BLKADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_UNLOCKEND_BLKADDR)
++ /* Current Nand Flash Write Protection Status */
++#define NFC_WRPR_STAT __REG16(IMX_NFC_REGS + NFC_OFFSET_WRPR_STAT)
++ /* Nand Flash Operation Configuration 1 */
++#define NFC_CONFIG1 __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG1)
++ /* Nand Flash Operation Configuration 2 */
++#define NFC_CONFIG2 __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG2)
++
++/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */
++#define NFC_ECC_STAT_ERM_SHFT (2) /* ERM shift */
++#define NFC_ECC_STAT_ERS_MASK (0x03) /* ERS mask */
++#define NFC_ECC_STAT_ERROR1 (1<<0) /* correctable error */
++#define NFC_ECC_STAT_ERROR2 (1<<1) /* non correctable error */
++
++/* NFC_CONFIG Control Register Bit Fields */
++#define NFC_CONFIG_UNLOCKED (1<<1) /* unlocked */
++#define NFC_CONFIG_LOCKED (1<<0) /* locked */
++/* NFC_WRPROT Control Register Bit Fields */
++#define NFC_WRPROT_UNLOCKBLK (4<<0) /* unlock block according to given address range */
++#define NFC_WRPROT_LOCKALL (2<<0) /* lock all */
++#define NFC_WRPROT_LOCKTIGHT (1<<0) /* lock-tight locked blocks */
++/* NFC_WRPR_STAT Status Register Bit Fields */
++#define NFC_WRPR_US (1<<2) /* Unlocked status */
++#define NFC_WRPR_LS (1<<1) /* Locked status */
++#define NFC_WRPR_LTS (1<<0) /* Lock-tight Status */
++/* NFC_CONFIG1 Control Register Bit Fields */
++#define NFC_CONFIG1_CEn (1<<7) /* Flash force CE */
++#define NFC_CONFIG1_RST (1<<6) /* Reset */
++#define NFC_CONFIG1_BIG (1<<5) /* Big Endian Mode */
++#define NFC_CONFIG1_INT_MSK (1<<4) /* Mask Interrupt Bit */
++#define NFC_CONFIG1_ECC_EN (1<<3) /* ECC operation enable */
++#define NFC_CONFIG1_SP_EN (1<<2) /* Flash spare enable */
++/* NFC_CONFIG2 Control Register Bit Fields */
++#define NFC_CONFIG2_INT (1<<15) /* Interrupt */
++#define NFC_CONFIG2_FDO_STATUS (4<<3) /* Flash status output */
++#define NFC_CONFIG2_FDO_ID (2<<3) /* Flash ID output */
++#define NFC_CONFIG2_FDO_PAGE (1<<3) /* Flash data output */
++#define NFC_CONFIG2_FDI (1<<2) /* Flash data input */
++#define NFC_CONFIG2_FADD (1<<1) /* Flash address input */
++#define NFC_CONFIG2_FCMD (1<<0) /* Flash command input */
++
++#define NAND_CMD_LOCK 0x2a
++#define NAND_CMD_LOCK_TIGHT 0x2c
++#define NAND_CMD_UNLOCK1 0x23
++#define NAND_CMD_UNLOCK2 0x24
++#define NAND_CMD_LOCK_STATUS 0x7a
++
++#endif
++
+ #endif /* _IMX_REGS_H */
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
new file mode 100644
index 0000000..6f4b9e9
--- /dev/null
+++ b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -0,0 +1,726 @@
+From fe25e4695b704742eee8ff6e0d01cf0c3413dbd3 Mon Sep 17 00:00:00 2001
+From: Philippe Reynes <tr...@ya...>
+Date: Sun, 25 Sep 2011 11:25:10 +0200
+Subject: [PATCH 2/6] Add support for the armadeus apf27 board
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ board/armadeus/apf27/Makefile | 50 ++
+ board/armadeus/apf27/apf27.c | 200 +++++++
+ board/armadeus/apf27/config.mk | 13 +
+ board/armadeus/apf27/lowlevel_init.S | 343 ++++++++++++
+ board/armadeus/apf27/u-boot-nand.lds | 56 ++
+ boards.cfg | 1 +
+ 6 files changed, 1649 insertions(+), 0 deletions(-)
+ create mode 100644 board/armadeus/apf27/Makefile
+ create mode 100644 board/armadeus/apf27/apf27.c
+ create mode 100644 board/armadeus/apf27/config.mk
+ create mode 100644 board/armadeus/apf27/lowlevel_init.S
+ create mode 100644 board/armadeus/apf27/u-boot-nand.lds
+
+diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
+new file mode 100644
+index 0000000..2a0f7d8
+--- /dev/null
++++ b/board/armadeus/apf27/Makefile
+@@ -0,0 +1,50 @@
++#
++# (C) Copyright 2000-2004
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).o
++
++COBJS := apf27.o
++SOBJS := lowlevel_init.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak $(obj).depend
++
++#########################################################################
++
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
+new file mode 100644
+index 0000000..e08b7a2
+--- /dev/null
++++ b/board/armadeus/apf27/apf27.c
+@@ -0,0 +1,200 @@
++/*
++ * Copyright (C) 2007 Sascha Hauer, Pengutronix
++ * Copyright (C) 2008,2009 Eric Jarrige <jo...@us...>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++#include <common.h>
++#include "crc.h"
++#include "fpga.h"
++#include <nand.h>
++#include <asm/arch/imx-regs.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static int read_firmware (size_t offset, size_t end, u_char * buf)
++{
++ size_t amount_loaded = 0;
++ size_t blocksize;
++
++ u_char *char_ptr;
++
++ blocksize = nand_info[0].erasesize;
++
++ while (offset < end) {
++ if (nand_block_isbad(&nand_info[0], offset)) {
++ offset += blocksize;
++ } else {
++ char_ptr = &buf[amount_loaded];
++ if (nand_read(&nand_info[0], offset, &blocksize, char_ptr))
++ return 1;
++ offset += blocksize;
++ amount_loaded += blocksize;
++ }
++ }
++
++ return amount_loaded;
++}
++
++
++static int apf27_devices_init(void)
++{
++ int i;
++ unsigned int mode[] = {
++ PD0_AIN_FEC_TXD0,
++ PD1_AIN_FEC_TXD1,
++ PD2_AIN_FEC_TXD2,
++ PD3_AIN_FEC_TXD3,
++ PD4_AOUT_FEC_RX_ER,
++ PD5_AOUT_FEC_RXD1,
++ PD6_AOUT_FEC_RXD2,
++ PD7_AOUT_FEC_RXD3,
++ PD8_AF_FEC_MDIO,
++ PD9_AIN_FEC_MDC | GPIO_PUEN,
++ PD10_AOUT_FEC_CRS,
++ PD11_AOUT_FEC_TX_CLK,
++ PD12_AOUT_FEC_RXD0,
++ PD13_AOUT_FEC_RX_DV,
++ PD14_AOUT_FEC_CLR,
++ PD15_AOUT_FEC_COL,
++ PD16_AIN_FEC_TX_ER,
++ PF23_AIN_FEC_TX_EN,
++ PE12_PF_UART1_TXD,
++ PE13_PF_UART1_RXD,
++ };
++
++ for (i = 0; i < ARRAY_SIZE(mode); i++)
++ imx_gpio_mode(mode[i]);
++
++#ifdef CONFIG_MXC_MMC
++ mx27_sd2_init_pins();
++#endif
++ return 0;
++}
++
++int board_mmc_init(bd_t *bis)
++{
++ return -1;
++}
++int
++board_init (void)
++{
++
++ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
++ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
++
++ /* On apf27 U-Boot is always in the relocatated stated */
++ gd->flags |= GD_FLG_RELOC;
++
++ apf27_devices_init();
++
++ return 0;
++}
++
++int
++dram_init (void)
++{
++ /* dram_init must store complete ramsize in gd->ram_size */
++ gd->ram_size = 0;
++#if ( CONFIG_NR_DRAM_BANKS > 0 )
++ gd->ram_size += get_ram_size((void *)CONFIG_SYS_SDRAM_1_BASE,
++ CONFIG_SYS_SDRAM_1_SIZE);
++#endif
++#if ( CONFIG_NR_DRAM_BANKS > 1 )
++ gd->ram_size += get_ram_size((void *)CONFIG_SYS_SDRAM_2_BASE,
++ CONFIG_SYS_SDRAM_2_SIZE);
++#endif
++ return 0;
++}
++
++void dram_init_banksize(void)
++{
++#if ( CONFIG_NR_DRAM_BANKS > 0 )
++ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_1_BASE;
++ gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_1_SIZE;
++#endif
++#if ( CONFIG_NR_DRAM_BANKS > 1 )
++ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_2_BASE;
++ gd->bd->bi_dram[1].size = CONFIG_SYS_SDRAM_2_SIZE;
++#endif
++}
++
++/*
++ * Miscellaneous intialization
++ */
++int
++misc_init_r (void)
++{
++ char *s;
++ u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
++ size_t end = 0;
++ size_t size = 0;
++ size_t offset = -1;
++ char *autoload = getenv ("firmware_autoload");
++
++#if defined(CONFIG_FPGA)
++ /* init and download fpga */
++ if (( autoload ) && (0 == strcmp(autoload, "1"))) {
++ if ((s = getenv("firmware_offset")) != NULL) {
++ offset = simple_strtoul(s, NULL, 16);
++ }
++ if ((s = getenv("firmware_len")) != NULL) {
++ end = offset + simple_strtoul(s, NULL, 16);
++ }
++ if ((-1 != offset) && (offset != end)) {
++ size = read_firmware (offset, end, firmware_buffer);
++ }
++ }
++ APF27_init_fpga (firmware_buffer, size);
++#endif
++
++ /* detect compatibility issue of environment version */
++ s = getenv ("env_version");
++ if (( NULL == s ) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
++ printf("*** Warning - Environment version change suggests: "
++ "run flash_reset_env; reset\n");
++ }
++
++ /* Unlock whole flash but U-Boot */
++ s = getenv ("env_offset");
++ offset = CONFIG_ENV_OFFSET;
++ if ((s != NULL) && (0 != strcmp(s, "0"))) {
++ offset = simple_strtoul(s, NULL, 16);
++ }
++
++ if (nand_unlock(&nand_info[0], offset, nand_info[0].size - offset)) {
++ printf("NAND flash lock/unlocked failed\n");
++ }
++
++
++ return 0;
++}
++
++void
++show_boot_progress (int status)
++{
++#ifdef CONFIG_SHOW_BOOT_PROGRESS
++#endif
++ return;
++}
++
++int checkboard(void)
++{
++ printf("Armadeus APF27\n");
++ return 0;
++}
+diff --git a/board/armadeus/apf27/config.mk b/board/armadeus/apf27/config.mk
+new file mode 100644
+index 0000000..3354ba0
+--- /dev/null
++++ b/board/armadeus/apf27/config.mk
+@@ -0,0 +1,13 @@
++#
++# This config file is used for compilation of armadeus sources
++#
++# You might change location of U-Boot in memory by setting right TEXT_BASE.
++# This allows for example having one copy located at the end of ram and stored
++# in flash device and later on while developing use other location to test
++# the code in RAM device only.
++#
++
++ifndef TEXT_BASE
++TEXT_BASE = 0xAFF00000
++endif
++# CONFIG_NAND_U_BOOT = y
+diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
+new file mode 100644
+index 0000000..4d72d8c
+--- /dev/null
++++ b/board/armadeus/apf27/lowlevel_init.S
+@@ -0,0 +1,343 @@
++/*
++ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
++ * Applications Processor Reference Manual, Rev. 0.2".
++ *
++ * (C) Copyright 2008 Eric Jarrige <eri...@ar...>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
++
++
++
++#define writel(reg, val) \
++ ldr r0, =reg; \
++ ldr r1, =val; \
++ str r1, [r0];
++
++.macro port_init
++ writel( FMCR, CONFIG_SYS_FMCR_VAL)
++/* PORTA */
++ writel( DR(PORTA), CONFIG_SYS_DR_A_VAL)
++ writel( OCR1(PORTA), CONFIG_SYS_OCR1_A_VAL)
++ writel( OCR2(PORTA), CONFIG_SYS_OCR2_A_VAL)
++ writel( ICONFA1(PORTA), CONFIG_SYS_ICFA1_A_VAL)
++ writel( ICONFA2(PORTA), CONFIG_SYS_ICFA2_A_VAL)
++ writel( ICONFB1(PORTA), CONFIG_SYS_ICFB1_A_VAL)
++ writel( ICONFB2(PORTA), CONFIG_SYS_ICFB2_A_VAL)
++ writel( ICR1(PORTA), CONFIG_SYS_ICR1_A_VAL)
++ writel( ICR2(PORTA), CONFIG_SYS_ICR2_A_VAL)
++ writel( IMR(PORTA), CONFIG_SYS_IMR_A_VAL)
++ writel( DDIR(PORTA), CONFIG_SYS_DDIR_A_VAL)
++ writel( GPR(PORTA), CONFIG_SYS_GPR_A_VAL)
++ writel( PUEN(PORTA), CONFIG_SYS_PUEN_A_VAL)
++ writel( GIUS(PORTA), CONFIG_SYS_GIUS_A_VAL)
++/* PORTB */
++ writel( DR(PORTB), CONFIG_SYS_DR_B_VAL)
++ writel( OCR1(PORTB), CONFIG_SYS_OCR1_B_VAL)
++ writel( OCR2(PORTB), CONFIG_SYS_OCR2_B_VAL)
++ writel( ICONFA1(PORTB), CONFIG_SYS_ICFA1_B_VAL)
++ writel( ICONFA2(PORTB), CONFIG_SYS_ICFA2_B_VAL)
++ writel( ICONFB1(PORTB), CONFIG_SYS_ICFB1_B_VAL)
++ writel( ICONFB2(PORTB), CONFIG_SYS_ICFB2_B_VAL)
++ writel( ICR1(PORTB), CONFIG_SYS_ICR1_B_VAL)
++ writel( ICR2(PORTB), CONFIG_SYS_ICR2_B_VAL)
++ writel( IMR(PORTB), CONFIG_SYS_IMR_B_VAL)
++ writel( DDIR(PORTB), CONFIG_SYS_DDIR_B_VAL)
++ writel( GPR(PORTB), CONFIG_SYS_GPR_B_VAL)
++ writel( PUEN(PORTB), CONFIG_SYS_PUEN_B_VAL)
++ writel( GIUS(PORTB), CONFIG_SYS_GIUS_B_VAL)
++/* PORTC */
++ writel( DR(PORTC), CONFIG_SYS_DR_C_VAL)
++ writel( OCR1(PORTC), CONFIG_SYS_OCR1_C_VAL)
++ writel( OCR2(PORTC), CONFIG_SYS_OCR2_C_VAL)
++ writel( ICONFA1(PORTC), CONFIG_SYS_ICFA1_C_VAL)
++ writel( ICONFA2(PORTC), CONFIG_SYS_ICFA2_C_VAL)
++ writel( ICONFB1(PORTC), CONFIG_SYS_ICFB1_C_VAL)
++ writel( ICONFB2(PORTC), CONFIG_SYS_ICFB2_C_VAL)
++ writel( ICR1(PORTC), CONFIG_SYS_ICR1_C_VAL)
++ writel( ICR2(PORTC), CONFIG_SYS_ICR2_C_VAL)
++ writel( IMR(PORTC), CONFIG_SYS_IMR_C_VAL)
++ writel( DDIR(PORTC), CONFIG_SYS_DDIR_C_VAL)
++ writel( GPR(PORTC), CONFIG_SYS_GPR_C_VAL)
++ writel( PUEN(PORTC), CONFIG_SYS_PUEN_C_VAL)
++ writel( GIUS(PORTC), CONFIG_SYS_GIUS_C_VAL)
++/* PORTD */
++ writel( DR(PORTD), CONFIG_SYS_DR_D_VAL)
++ writel( OCR1(PORTD), CONFIG_SYS_OCR1_D_VAL)
++ writel( OCR2(PORTD), CONFIG_SYS_OCR2_D_VAL)
++ writel( ICONFA1(PORTD), CONFIG_SYS_ICFA1_D_VAL)
++ writel( ICONFA2(PORTD), CONFIG_SYS_ICFA2_D_VAL)
++ writel( ICONFB1(PORTD), CONFIG_SYS_ICFB1_D_VAL)
++ writel( ICONFB2(PORTD), CONFIG_SYS_ICFB2_D_VAL)
++ writel( ICR1(PORTD), CONFIG_SYS_ICR1_D_VAL)
++ writel( ICR2(PORTD), CONFIG_SYS_ICR2_D_VAL)
++ writel( IMR(PORTD), CONFIG_SYS_IMR_D_VAL)
++ writel( DDIR(PORTD), CONFIG_SYS_DDIR_D_VAL)
++ writel( GPR(PORTD), CONFIG_SYS_GPR_D_VAL)
++ writel( PUEN(PORTD), CONFIG_SYS_PUEN_D_VAL)
++ writel( GIUS(PORTD), CONFIG_SYS_GIUS_D_VAL)
++/* PORTE */
++ writel( DR(PORTE), CONFIG_SYS_DR_E_VAL)
++ writel( OCR1(PORTE), CONFIG_SYS_OCR1_E_VAL)
++ writel( OCR2(PORTE), CONFIG_SYS_OCR2_E_VAL)
++ writel( ICONFA1(PORTE), CONFIG_SYS_ICFA1_E_VAL)
++ writel( ICONFA2(PORTE), CONFIG_SYS_ICFA2_E_VAL)
++ writel( ICONFB1(PORTE), CONFIG_SYS_ICFB1_E_VAL)
++ writel( ICONFB2(PORTE), CONFIG_SYS_ICFB2_E_VAL)
++ writel( ICR1(PORTE), CONFIG_SYS_ICR1_E_VAL)
++ writel( ICR2(PORTE), CONFIG_SYS_ICR2_E_VAL)
++ writel( IMR(PORTE), CONFIG_SYS_IMR_E_VAL)
++ writel( DDIR(PORTE), CONFIG_SYS_DDIR_E_VAL)
++ writel( GPR(PORTE), CONFIG_SYS_GPR_E_VAL)
++ writel( PUEN(PORTE), CONFIG_SYS_PUEN_E_VAL)
++ writel( GIUS(PORTE), CONFIG_SYS_GIUS_E_VAL)
++/* PORTF */
++ writel( DR(PORTF), CONFIG_SYS_DR_F_VAL)
++ writel( OCR1(PORTF), CONFIG_SYS_OCR1_F_VAL)
++ writel( OCR2(PORTF), CONFIG_SYS_OCR2_F_VAL)
++ writel( ICONFA1(PORTF), CONFIG_SYS_ICFA1_F_VAL)
++ writel( ICONFA2(PORTF), CONFIG_SYS_ICFA2_F_VAL)
++ writel( ICONFB1(PORTF), CONFIG_SYS_ICFB1_F_VAL)
++ writel( ICONFB2(PORTF), CONFIG_SYS_ICFB2_F_VAL)
++ writel( ICR1(PORTF), CONFIG_SYS_ICR1_F_VAL)
++ writel( ICR2(PORTF), CONFIG_SYS_ICR2_F_VAL)
++ writel( IMR(PORTF), CONFIG_SYS_IMR_F_VAL)
++ writel( DDIR(PORTF), CONFIG_SYS_DDIR_F_VAL)
++ writel( GPR(PORTF), CONFIG_SYS_GPR_F_VAL)
++ writel( PUEN(PORTF), CONFIG_SYS_PUEN_F_VAL)
++ writel( GIUS(PORTF), CONFIG_SYS_GIUS_F_VAL)
++.endm /* port_init */
++
++.macro init_aipi
++ /*
++ * setup AIPI1 and AIPI2
++ */
++ writel(AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL)
++ writel(AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL)
++ writel(AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL)
++ writel(AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL)
++
++ /* Change SDRAM signal strengh */
++ ldr r0, =GPCR
++ ldr r1, =CONFIG_SYS_GPCR_VAL
++ ldr r5, [r0]
++ orr r5, r5, r1
++ str r5, [r0]
++
++.endm /* init_aipi */
++
++.macro init_clock
++ ldr r0, =CSCR
++ /* disable MPLL/SPLL first */
++ ldr r1, [r0]
++ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
++ str r1, [r0]
++
++ /*
++ * pll clock initialization predefined in apf27.h
++ */
++ writel(MPCTL0, CONFIG_SYS_MPCTL0_VAL)
++ writel(SPCTL0, CONFIG_SYS_SPCTL0_VAL)
++
++ writel(CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
++
++ /*
++ * add some delay here
++ */
++ mov r1, #0x1000
++ 1: subs r1, r1, #0x1
++ bne 1b
++
++ /* peripheral clock divider */
++ writel(PCDR0, CONFIG_SYS_PCDR0_VAL)
++ writel(PCDR1, CONFIG_SYS_PCDR1_VAL)
++
++ /* Configure PCCR0 and PCCR1 */
++ writel(PCCR0, CONFIG_SYS_PCCR0_VAL)
++ writel(PCCR1, CONFIG_SYS_PCCR1_VAL)
++
++
++.endm /* init_clock */
++
++.macro sdram_init
++ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
++ ldr r0, =ESDMISC
++ ldr r4, =ESDMISC_SDRAM_RDY
++2: ldr r1, [r0]
++ ands r1, r1, r4
++ bpl 2b
++
++ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
++ ldr r0, =ESDMISC
++ ldr r4, =CONFIG_SYS_ESDMISC_VAL
++ orr r1, r4, #ESDMISC_MDDR_DL_RST
++ str r1, [r0]
++
++ /* Hold for more than 200ns */
++ ldr r1, =0x10000
++ 1: subs r1, r1, #0x1
++ bne 1b
++
++ str r4, [r0]
++
++ writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
++
++ /* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
++ ldr r0, =ESDCTL0
++ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
++ str r1, [r0]
++
++ /* writeb(0xA0001000, any value) */
++ ldr r1, =CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldrb r2, [r1]
++
++ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
++ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
++ str r1, [r0]
++
++ ldr r4, =CONFIG_SYS_SDRAM_1_BASE /* CSD0 base address */
++
++ ldr r6,=0x7 /* load loop counter */
++1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
++ subs r6,r6,#1 /* decrease counter value */
++ bne 1b
++
++ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
++ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
++ str r1, [r0]
++
++ /* set standard mode register */
++ ldr r4, = CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ ldrb r2, [r4]
++
++ /* set extended mode register */
++ ldr r4, =CONFIG_SYS_SDRAM_1_BASE+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++ ldrb r5, [r4]
++
++ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
++ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
++ str r1, [r0]
++
++#if (CONFIG_NR_DRAM_BANKS > 1)
++ /* 2nd sdram */
++ writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL )
++
++ /* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
++ ldr r0, =ESDCTL1
++ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
++ str r1, [r0]
++
++ /* writeb(0xB0001000, any value) */
++ ldr r1, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldrb r2, [r1]
++
++ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
++ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
++ str r1, [r0]
++
++ ldr r4, =CONFIG_SYS_SDRAM_2_BASE /* CSD1 base address */
++
++ ldr r6,=0x7 /* load loop counter */
++1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
++ subs r6,r6,#1 /* decrease counter value */
++ bne 1b
++
++ /* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
++ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
++ str r1, [r0]
++
++ /* set standard mode register */
++ ldr r4, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ ldrb r2, [r4]
++
++ /* set extended mode register */
++ ldr r4, =CONFIG_SYS_SDRAM_2_BASE+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++ ldrb r2, [r4]
++
++ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
++ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
++ str r1, [r0]
++#endif /* CONFIG_NR_DRAM_BANKS > 1 */
++.endm /* sdram_init */
++
++.globl board_init_lowlevel
++board_init_lowlevel:
++.globl lowlevel_init
++lowlevel_init:
++
++ mov r10, lr
++
++ init_aipi
++
++ /* configure csx */
++ writel(CS0U, CONFIG_SYS_CS0U_VAL)
++ writel(CS0L, CONFIG_SYS_CS0L_VAL)
++ writel(CS0A, CONFIG_SYS_CS0A_VAL)
++
++ writel(CS1U, CONFIG_SYS_CS1U_VAL)
++ writel(CS1L, CONFIG_SYS_CS1L_VAL)
++ writel(CS1A, CONFIG_SYS_CS1A_VAL)
++
++ writel(CS2U, CONFIG_SYS_CS2U_VAL)
++ writel(CS2L, CONFIG_SYS_CS2L_VAL)
++ writel(CS2A, CONFIG_SYS_CS2A_VAL)
++
++ writel(CS3U, CONFIG_SYS_CS3U_VAL)
++ writel(CS3L, CONFIG_SYS_CS3L_VAL)
++ writel(CS3A, CONFIG_SYS_CS3A_VAL)
++
++ writel(CS4U, CONFIG_SYS_CS4U_VAL)
++ writel(CS4L, CONFIG_SYS_CS4L_VAL)
++ writel(CS4A, CONFIG_SYS_CS4A_VAL)
++
++ writel(CS5U, CONFIG_SYS_CS5U_VAL)
++ writel(CS5L, CONFIG_SYS_CS5L_VAL)
++ writel(CS5A, CONFIG_SYS_CS5A_VAL)
++
++ writel(EIM, CONFIG_SYS_EIM_VAL)
++
++ port_init
++
++ /* Configure FPGA CLKO */
++ writel(CCSR, CONFIG_SYS_CCSR_VAL)
++
++ /* Configure strentgh for FPGA */
++ writel(DSCR10, CONFIG_SYS_DSCR10_VAL)
++ writel(DSCR3, CONFIG_SYS_DSCR3_VAL)
++ writel(DSCR7, CONFIG_SYS_DSCR7_VAL)
++ writel(DSCR2, CONFIG_SYS_DSCR2_VAL)
++
++
++
++ /* skip clock and sdram initialization if we run from ram */
++ cmp pc, #0xa0000000
++ bls 1f
++ cmp pc, #0xc0000000
++ bhi 1f
++
++ mov pc,r10
++1:
++ init_clock
++
++ sdram_init
++
++ mov pc,r10
++
+diff --git a/board/armadeus/apf27/u-boot-nand.lds b/board/armadeus/apf27/u-boot-nand.lds
+new file mode 100644
+index 0000000..f66f20e
+--- /dev/null
++++ b/board/armadeus/apf27/u-boot-nand.lds
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2007
++ * Wolfgang Denk, DENX Software Engineering, wd...@de....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ cpu/arm926ejs/start.o (.text)
++ *(.text)
++ }
++
++ . = ALIGN(4);
++ .rodata : { *(.rodata) }
++
++ . = ALIGN(4);
++ .data : { *(.data) }
++
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
++
+diff --git a/boards.cfg b/boards.cfg
+index 66c27a4..f68c3a7 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -69,6 +69,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd
+ aspenite arm arm926ejs - Marvell armada100
+ gplugd arm arm926ejs - Marvell armada100
+ afeb9260 arm arm926ejs - - at91
++apf27 arm arm926ejs apf27 armadeus mx27
+ at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
+ at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
+ at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
+1.7.4.4
+
diff --git a/patches/u-boot/2011.12/303-Remove-useless-code-in-apf27.patch b/patches/u-boot/2011.12/303-Remove-useless-code-in-apf27.patch
new file mode 100644
index 0000000..d9ed98d
--- /dev/null
+++ b/patches/u-boot/2011.12/303-Remove-useless-code-in-apf27.patch
@@ -0,0 +1,76 @@
+From 7d5eba120d72f2ea5e3a946fd2c87b021759f21b Mon Sep 17 00:00:00 2001
+From: Philippe Reynes <tr...@ya...>
+Date: Tue, 4 Oct 2011 19:30:15 +0200
+Subject: [PATCH 3/6] Remove useless code in apf27
+
+---
+ board/armadeus/apf27/apf27.c | 45 ------------------------------------------
+ 1 files changed, 0 insertions(+), 45 deletions(-)
+
+diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
+index e08b7a2..d4f2082 100644
+--- a/board/armadeus/apf27/apf27.c
++++ b/board/armadeus/apf27/apf27.c
+@@ -27,31 +27,6 @@
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+-static int read_firmware (size_t offset, size_t end, u_char * buf)
+-{
+- size_t amount_loaded = 0;
+- size_t blocksize;
+-
+- u_char *char_ptr;
+-
+- blocksize = nand_info[0].erasesize;
+-
+- while (offset < end) {
+- if (nand_block_isbad(&nand_info[0], offset)) {
+- offset += blocksize;
+- } else {
+- char_ptr = &buf[amount_loaded];
+- if (nand_read(&nand_info[0], offset, &blocksize, char_ptr))
+- return 1;
+- offset += blocksize;
+- amount_loaded += blocksize;
+- }
+- }
+-
+- return amount_loaded;
+-}
+-
+-
+ static int apf27_devices_init(void)
+ {
+ int i;
+@@ -141,27 +116,7 @@ int
+ misc_init_r (void)
+ {
+ char *s;
+- u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
+- size_t end = 0;
+- size_t size = 0;
+ size_t offset = -1;
+- char *autoload = getenv ("firmware_autoload");
+-
+-#if defined(CONFIG_FPGA)
+- /* init and download fpga */
+- if (( autoload ) && (0 == strcmp(autoload, "1"))) {
+- if ((s = getenv("firmware_offset")) != NULL) {
+- offset = simple_strtoul(s, NULL, 16);
+- }
+- if ((s = getenv("firmware_len")) != NULL) {
+- end = offset + simple_strtoul(s, NULL, 16);
+- }
+- if ((-1 != offset) && (offset != end)) {
+- size = read_firmware (offset, end, firmware_buffer);
+- }
+- }
+- APF27_init_fpga (firmware_buffer, size);
+-#endif
+
+ /* detect compatibility issue of environment version */
+ s = getenv ("env_version");
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2011.12/304-Add-type-for-apf27.patch b/patches/u-boot/2011.12/304-Add-type-for-apf27.patch
new file mode 100644
index 0000000..29628c7
--- /dev/null
+++ b/patches/u-boot/2011.12/304-Add-type-for-apf27.patch
@@ -0,0 +1,24 @@
+From bfedc74f6beae4f7bbb5f2ccf0c651a489fe7675 Mon Sep 17 00:00:00 2001
+From: Philippe Reynes <tr...@ya...>
+Date: Wed, 28 Dec 2011 14:26:52 +0100
+Subject: [PATCH 4/6] Add type for apf27
+
+---
+ arch/arm/include/asm/mach-types.h | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
+index 2d5c3bc..c38a816 100644
+--- a/arch/arm/include/asm/mach-types.h
++++ b/arch/arm/include/asm/mach-types.h
+@@ -286,6 +286,7 @@ extern unsigned int __machine_arch_type;
+ #define MACH_TYPE_WBD111 1690
+ #define MACH_TYPE_MV2120 1693
+ #define MACH_TYPE_MX51_3DS 1696
++#define MACH_TYPE_APF27 1698
+ #define MACH_TYPE_IMX27LITE 1701
+ #define MACH_TYPE_USB_A9260 1709
+ #define MACH_TYPE_USB_A9263 1710
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2011.12/305-Define-uart1-for-the-console.patch b/patches/u-boot/2011.12/305-Define-uart1-for-the-console.patch
new file mode 100644
index 0000000..7f00497
--- /dev/null
+++ b/patches/u-boot/2011.12/305-Define-uart1-for-the-console.patch
@@ -0,0 +1,24 @@
+From 434d5acde85c1277d3ff32597a56e50304fd4081 Mon Sep 17 00:00:00 2001
+From: Philippe Reynes <tr...@ya...>
+Date: Wed, 28 Dec 2011 14:27:48 +0100
+Subject: [PATCH 5/6] Define uart1 for the console
+
+---
+ include/configs/apf27.h | 1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/include/configs/apf27.h b/include/configs/apf27.h
+index f1602a0..48c73bb 100644
+--- a/include/configs/apf27.h
++++ b/include/configs/apf27.h
+@@ -66,6 +66,7 @@
+ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
+ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+ #define CONFIG_BAUDRATE 115200
++#define CONFIG_MXC_UART_BASE UART1_BASE
+
+ /*
+ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2011.12/306-Debug-nand-this-patch-should-be-removed.patch b/patches/u-boot/2011.12/306-Debug-nand-this-patch-should-be-removed.patch
new file mode 100644
index 0000000..5746cda
--- /dev/null
+++ b/patches/u-boot/2011.12/306-Debug-nand-this-patch-should-be-removed.patch
@@ -0,0 +1,150 @@
+From 8aa4ee39d003d442cc9f01ea487dcce190274cfc Mon Sep 17 00:00:00 2001
+From: Philippe Reynes <tr...@ya...>
+Date: Wed, 25 Jan 2012 20:36:42 +0100
+Subject: [PATCH 6/6] Debug nand, this patch should be removed
+
+---
+ drivers/mtd/nand/mxc_nand.c | 22 +++++++++++++++++++++-
+ drivers/mtd/nand/nand_base.c | 2 ++
+ include/configs/apf27.h | 16 ++++++++--------
+ 3 files changed, 31 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
+index 35e89a0..929e228 100644
+--- a/drivers/mtd/nand/mxc_nand.c
++++ b/drivers/mtd/nand/mxc_nand.c
+@@ -193,7 +193,8 @@ static struct mxc_nand_host mxc_host;
+ static struct mxc_nand_host *host = &mxc_host;
+
+ /* Define delays in microsec for NAND device operations */
+-#define TROP_US_DELAY 2000
++#define TROP_US_DELAY 10000
++
+ /* Macros to get byte and bit positions of ECC */
+ #define COLPOS(x) ((x) >> 3)
+ #define BITPOS(x) ((x) & 0xf)
+@@ -326,6 +327,21 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
+ {
+ MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
+
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: bufsize = 0x%04x\n", __func__, readw(&host->regs->nfc_buf_size));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_buf_addr = 0x%04x\n", __func__, readw(&host->regs->nfc_buf_addr));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_flash_addr = 0x%04x\n", __func__, readw(&host->regs->nfc_flash_addr));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_flash_cmd = 0x%04x\n", __func__, readw(&host->regs->nfc_flash_cmd));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_config = 0x%04x\n", __func__, readw(&host->regs->nfc_config));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_ecc_status_result = 0x%04x\n", __func__, readw(&host->regs->nfc_ecc_status_result));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_rsltmain_area = 0x%04x\n", __func__, readw(&host->regs->nfc_rsltmain_area));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_rsltspare_area = 0x%04x\n", __func__, readw(&host->regs->nfc_rsltspare_area));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_wrprot = 0x%04x\n", __func__, readw(&host->regs->nfc_wrprot));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_unlockstart_blkaddr = 0x%04x\n", __func__, readw(&host->regs->nfc_unlockstart_blkaddr));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_unlockend_blkaddr = 0x%04x\n", __func__, readw(&host->regs->nfc_unlockend_blkaddr));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: nfc_nf_wrprst = 0x%04x\n", __func__, readw(&host->regs->nfc_nf_wrprst));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: config1 = 0x%04x\n", __func__, readw(&host->regs->nfc_config1));
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: config2 = 0x%04x\n", __func__, readw(&host->regs->nfc_config2));
++
+ writew(cmd, &host->regs->nfc_flash_cmd);
+ writew(NFC_CMD, &host->regs->nfc_config2);
+
+@@ -1308,6 +1324,8 @@ int board_nand_init(struct nand_chip *this)
+ uint16_t tmp;
+ int err = 0;
+
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s(this = %p)\n", __func__, this);
++
+ /* structures must be linked */
+ mtd = &host->mtd;
+ mtd->priv = this;
+@@ -1391,6 +1409,8 @@ int board_nand_init(struct nand_chip *this)
+ if (is_16bit_nand())
+ this->options |= NAND_BUSWIDTH_16;
+
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: this->options = %x\n", __func__, this->options);
++
+ #ifdef CONFIG_SYS_NAND_LARGEPAGE
+ host->pagesize_2k = 1;
+ this->ecc.layout = &nand_hw_eccoob2k;
+diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
+index 27f6c77..6107b8b 100644
+--- a/drivers/mtd/nand/nand_base.c
++++ b/drivers/mtd/nand/nand_base.c
+@@ -2578,6 +2578,8 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
+ tmp_manf = chip->read_byte(mtd);
+ tmp_id = chip->read_byte(mtd);
+
++ MTDDEBUG(MTD_DEBUG_LEVEL1, "%s: manf = %02x, id = %02x\n", __func__, tmp_manf, tmp_id);
++
+ if (tmp_manf != *maf_id || tmp_id != *dev_id) {
+ printk(KERN_INFO "%s: second ID read did not match "
+ "%02x,%02x against %02x,%02x\n", __func__,
+diff --git a/include/configs/apf27.h b/include/configs/apf27.h
+index 48c73bb..162bced 100644
+--- a/include/configs/apf27.h
++++ b/include/configs/apf27.h
+@@ -80,7 +80,7 @@
+ #define CONFIG_CMD_BSP /* Board Specific functions */
+ #define CONFIG_CMD_CACHE /* icache, dcache */
+ #define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
+-//#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
++// #define CONFIG_CMD_DATE /* support for RTC, date/time...*/
+ #define CONFIG_CMD_DHCP /* DHCP Support */
+ #define CONFIG_CMD_DIAG /* Diagnostics */
+ //#define CONFIG_CMD_EEPROM /* EEPROM read/write support */
+@@ -358,7 +358,7 @@
+ /*
+ * SDRAM definition parameter
+ */
+-#define CONFIG_NR_DRAM_BANKS 1
++#define CONFIG_NR_DRAM_BANKS 2
+
+ #define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
+
+@@ -552,8 +552,8 @@
+ //#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+ //#define CONFIG_SYS_NAND_SELECT_DEVICE 0 /* nand driver supports mutipl. chips */
+ //#define CONFIG_SYS_NFC_DEBUG
+-//#define CONFIG_MTD_DEBUG
+-//#define CONFIG_MTD_DEBUG_VERBOSE 3
++#define CONFIG_MTD_DEBUG
++#define CONFIG_MTD_DEBUG_VERBOSE 3
+
+ /*=====================*/
+
+@@ -787,7 +787,7 @@
+ #define CONFIG_SYS_OCR2_B_VAL 0x00000000
+ #define CONFIG_SYS_ICFA1_B_VAL 0xFFFFFFFF
+ #define CONFIG_SYS_ICFA2_B_VAL 0xFFFFFFFF
+-#define CONFIG_SYS_ICFB1_B_VAL 0xFFFFFFFF
++#define CONFIG_SYS_ICFB1_B_VAL 0xFFFFFFFF
+ #define CONFIG_SYS_ICFB2_B_VAL 0xFFFFFFFF
+ #define CONFIG_SYS_DR_B_VAL 0x00000000
+ #define CONFIG_SYS_GIUS_B_VAL 0xFF3FFFF0
+@@ -805,7 +805,7 @@
+ #define CONFIG_SYS_ICFB1_C_VAL 0xFFFFFFFF
+ #define CONFIG_SYS_ICFB2_C_VAL 0xFFFFFFFF
+ #define CONFIG_SYS_DR_C_VAL 0x00000000
+-#define CONFIG_SYS_GIUS_C_VAL 0xFFFFFFFF
++#define CONFIG_SYS_GIUS_C_VAL 0xFFFFC07F
+ #define CONFIG_SYS_ICR1_C_VAL 0x00000000
+ #define CONFIG_SYS_ICR2_C_VAL 0x00000000
+ #define CONFIG_SYS_IMR_C_VAL 0x00000000
+@@ -835,7 +835,7 @@
+ #define CONFIG_SYS_ICFB1_E_VAL 0xFFFFFFFF
+ #define CONFIG_SYS_ICFB2_E_VAL 0xFFFFFFFF
+ #define CONFIG_SYS_DR_E_VAL 0x00000000
+-#define CONFIG_SYS_GIUS_E_VAL 0xFFFFCCF8
++#define CONFIG_SYS_GIUS_E_VAL 0xFCFFCCF8
+ #define CONFIG_SYS_ICR1_E_VAL 0x00000000
+ #define CONFIG_SYS_ICR2_E_VAL 0x00000000
+ #define CONFIG_SYS_IMR_E_VAL 0x00000000
+@@ -880,7 +880,7 @@
+ #define CONFIG_SYS_AIPI2_PSR1_VAL 0xFFFFFFFF
+
+ /* PCCR enable DMA FEC I2C1 IIM SDHC1 */
+-#define CONFIG_SYS_PCCR0_VAL 0x05070410
++#define CONFIG_SYS_PCCR0_VAL 0x05070400
+ #define CONFIG_SYS_PCCR1_VAL 0xA14A0408
+
+ /* CONFIG_SKIP_LOWLEVEL_INIT bypass lowlevel init in bootstrap mode */
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2011.12/310-apf27-nand-spl.patch b/patches/u-boot/2011.12/310-apf27-nand-spl.patch
new file mode 100644
index 0000000..db09282
--- /dev/null
+++ b/patches/u-boot/2011.12/310-apf27-nand-spl.patch
@@ -0,0 +1,721 @@
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,43 @@
++#
++# (C) Copyright 2007
++# Stefan Roese, DENX Software Engineering, sr...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++#
++# This config file is used for compilation of armadeus apf27 board
++#
++
++#
++# TEXT_BASE for SPL:
++#
++#
++# This config file is used for compilation of armadeus sources
++#
++# You might change location of U-Boot in memory by setting right TEXT_BASE.
++# This allows for example having one copy located at the end of ram and stored
++# in flash device and later on while developing use other location to test
++# the code in RAM device only.
++#
++
++TEXT_BASE = 0xa0000000
++
++# PAD_TO used to generate a 2kByte binary needed for the combined image
++# -> PAD_TO = TEXT_BASE + 0x0800
++PAD_TO = 0xa0000800
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,77 @@
++#
++# (C) Copyright 2007
++# Stefan Roese, DENX Software Engineering, sr...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
++
++LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
++LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
++AFLAGS += -DCONFIG_NAND_SPL
++CFLAGS += -DCONFIG_NAND_SPL
++
++SOBJS = start.o
++COBJS =
++
++SRCS := $(addprefix $(src),$(SOBJS:.o=.S) $(COBJS:.o=.c))
++OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
++__OBJS := $(SOBJS) $(COBJS)
++LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
++
++nandobj := $(OBJTREE)/nand_spl/
++
++ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
++ $(nandobj)System.map
++
++all: $(obj).depend $(ALL)
++
++$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
++ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
++
++$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
++ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
++
++$(nandobj)u-boot-spl: $(OBJS)
++ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
++ -Map $(nandobj)u-boot-spl.map \
++ -o $(nandobj)u-boot-spl
++
++$(nandobj)System.map: $(nandobj)u-boot-spl
++ @$(NM) $< | \
++ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
++ sort > $(nandobj)System.map
++
++
++#########################################################################
++
++$(obj)%.o: %.S
++ $(CC) $(AFLAGS) -c -o $@ $<
++
++$(obj)%.o: %.c
++ $(CC) $(CFLAGS) -c -o $@ $<
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,544 @@
++/*
++ * IMX27 NAND Flash SPL (Secondary Program Loader)
++ *
++ * Copyright (c) 2008 Armadeus Project / eja
++ *
++ * Based on Freescale NAND SPL
++ *
++ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
++ * Copyright (c) 2008 Eric Jarrige <eri...@ar...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
++
++/*
++ * Standard NAND flash commands
++ */
++#define NAND_CMD_READ0 0
++#define NAND_CMD_READ1 1
++#define NAND_CMD_PAGEPROG 0x10
++#define NAND_CMD_READOOB 0x50
++#define NAND_CMD_ERASE1 0x60
++#define NAND_CMD_STATUS 0x70
++#define NAND_CMD_STATUS_MULTI 0x71
++#define NAND_CMD_SEQIN 0x80
++#define NAND_CMD_READID 0x90
++#define NAND_CMD_ERASE2 0xd0
++#define NAND_CMD_RESET 0xff
++
++/* Extended commands for large page devices */
++#define NAND_CMD_READSTART 0x30
++#define NAND_CMD_CACHEDPROG 0x15
++
++/* Status bits */
++#define NAND_STATUS_FAIL 0x01
++#define NAND_STATUS_FAIL_N1 0x02
++#define NAND_STATUS_TRUE_READY 0x20
++#define NAND_STATUS_READY 0x40
++#define NAND_STATUS_WP 0x80
++
++#define writel(reg, val) \
++ ldr r0, =reg; \
++ ldr r1, =val; \
++ str r1, [r0];
++
++ .macro nand_boot
++
++#ifdef CONFIG_BOOT_TRACE_REG
++/*
++ * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following
++ * 2 command after SDRAM init
++ */
++
++/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
++#define BACKUP_TRACE() \
++ ldr r4, =CONFIG_BOOT_TRACE_REG; \
++ ldr r3, [r4]; \
++ str r3, [r4, #0x04];
++
++/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
++#define BOOT_TRACE(val) \
++ ldr r4, =CONFIG_BOOT_TRACE_REG; \
++ ldr r3, =val; \
++ str r3, [r4];
++#else
++#define BACKUP_TRACE()
++#define BOOT_TRACE(val)
++#endif
++
++nand_boot_setup:
++
++ /* Copy SPL image from flash to SDRAM first */
++ BOOT_TRACE(1)
++ ldr r0, =IMX_NFC_MAIN_AREA0
++ add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff
++ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
++
++ BOOT_TRACE(2)
++1: ldmia r0!, {r3-r10}
++ stmia r1!, {r3-r10}
++ cmp r0, r2
++ blo 1b
++
++
++
++ /* Jump to SDRAM */
++ BOOT_TRACE(3)
++ ldr r1, =0xFFF
++ and r0, pc, r1 /* offset of pc */
++ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
++ add r1, r1, #0x10
++ add pc, r0, r1
++ nop
++ nop
++ nop
++ nop
++
++NAND_Copy_Main:
++ BOOT_TRACE(4)
++ /* r0: nfc base. Reloaded after each page copying */
++ ldr r0, =IMX_NFC_MAIN_AREA0
++
++ /* r1: starting flash addr to be copied. Updated constantly */
++ /* bypass the first preloaded pages */
++ ldr r1, =(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0)
++
++ /* r2: end of 1st RAM buf. Doesn't change */
++ ldr r2, =IMX_NFC_MAIN_AREA1
++
++ /* r12: NFC register base. Doesn't change */
++ ldr r12, =IMX_NFC_REGS
++
++ ldr r11, =CONFIG_SYS_NAND_U_BOOT_DST
++
++ /* r13: end of SDRAM address for copying. Doesn't change */
++ add r13, r11, #CONFIG_SYS_NAND_U_BOOT_SIZE
++
++ /* r11: starting SDRAM address for copying. Updated constantly */
++ add r11, r11, r1
++
++ /* unlock internal buffer */
++ ldr r3, =NFC_CONFIG_UNLOCKED
++ strh r3, [r12, #NFC_OFFSET_CONFIG]
++
++ /* enable ECC and mask interrupts */
++ ldr r3, =(NFC_CONFIG1_ECC_EN | NFC_CONFIG1_INT_MSK)
++ strh r3, [r12, #NFC_OFFSET_CONFIG1]
++
++Nfc_Read_Page:
++ BOOT_TRACE(5)
++ /* send NAND_CMD_READ0 command */
++ ldr r3, =NAND_CMD_READ0;
++ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
++
++ ldr r3, =NFC_CONFIG2_FCMD
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ /* send NAND address to read. TODO small page support */
++ BOOT_TRACE(6)
++ mov r3, r1, lsr #1
++ bl do_addr_input /* 1st addr cycle */
++
++ mov r3, r1, lsr #9
++ and r3, r3, #0x03
++ bl do_addr_input /* 2nd addr cycle */
++
++ mov r3, r1, lsr #11
++ bl do_addr_input /* 3rd addr cycle */
++
++ mov r3, r1, lsr #19
++ bl do_addr_input /* 4th addr cycle */
++
++ /* Small NAND flashs ...
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