[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-52-gd4e6943

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- Log -----------------------------------------------------------------
commit d4e694321fd9f87e9d11a8ec6c2085fbb31f6ad3
Author: Eric Jarrige <eri...@ar...>
Date:   Mon Feb 13 22:56:23 2012 +0100

    [UBOOT] apf27: U-Boot 2011.12 default configuration

-----------------------------------------------------------------------

Summary of changes:
 ...f27-u-boot-2010.03.h => apf27-u-boot-2011.12.h} |   50 +++++++++++++-------
 1 files changed, 32 insertions(+), 18 deletions(-)
 copy buildroot/target/device/armadeus/apf27/{apf27-u-boot-2010.03.h => apf27-u-boot-2011.12.h} (96%)

diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2010.03.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
similarity index 96%
copy from buildroot/target/device/armadeus/apf27/apf27-u-boot-2010.03.h
copy to buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
index 805bf20..2c5e2a2 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2010.03.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
@@ -66,6 +66,7 @@
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 #define CONFIG_BAUDRATE 	115200
+#define CONFIG_MXC_UART_BASE	UART1_BASE
 
 /*
  * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
@@ -79,15 +80,15 @@
 #define CONFIG_CMD_BSP		/* Board Specific functions	*/
 #define CONFIG_CMD_CACHE	/* icache, dcache		*/
 #define CONFIG_CMD_CDP		/* Cisco Discovery Protocol	*/
-#define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
+// #define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
 #define CONFIG_CMD_DHCP		/* DHCP Support			*/
 #define CONFIG_CMD_DIAG		/* Diagnostics			*/
-#define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
+//#define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
 #define CONFIG_CMD_ELF		/* bootelf, bootvx		*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #undef  CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
-#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+//#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #undef CONFIG_CMD_IMLS		/* List all found images	*/
 #define CONFIG_CMD_IMMAP	/* IMMR dump support		*/
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
@@ -99,15 +100,15 @@
 #define CONFIG_CMD_PING		/* ping support			*/
 #define CONFIG_CMD_SAVES	/* save S record dump		*/
 #define CONFIG_CMD_SETEXPR	/* setexpr support		*/
-#define CONFIG_CMD_SNTP		/* SNTP support			*/
+//#define CONFIG_CMD_SNTP		/* SNTP support			*/
 #define CONFIG_CMD_NFS		/* NFS support			*/
 #define CONFIG_CMD_DNS
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
 #define CONFIG_CMD_IMX_FUSE	/* iMX fuse access commands	*/
 
-#undef CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
 
 /*
  * Select some advanced features of the commande line parser
@@ -357,7 +358,7 @@
 /*
  * SDRAM definition parameter
  */
-#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_NR_DRAM_BANKS 2
 
 #define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
 
@@ -511,6 +512,18 @@
 #define CONFIG_SYS_SDRAM_SINGLE_ACCESS		0  /* 1= single access; 0 = Burst mode */
 #endif
 
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_SDRAM_1_BASE
+
+/* lowlevel_linit copy U-Boot at CONFIG_SYS_INIT_SP_ADDR  (here in RAM) */
+/* making u-boot runnable from flash and also RAM that is usefull to boot */
+/* from serial port and from flash with only one version of U-Boot */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xA0000000
+#endif
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
+		+ CONFIG_SYS_SDRAM_1_SIZE - 0x0100000)
+
 /*
  * Configuration for no NOR FLASH memory
  */
@@ -547,6 +560,7 @@
 #define CONFIG_NAND_U_BOOT
 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_LOAD_ADDR	/* Copy SPL+U-Boot here	     */
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	CONFIG_SYS_MONITOR_LEN /* Size is the partion size  */
+
 /*
  * Environment setup. Definitions of monitor location and size with
  * definition of environment setup ends up in 2 possibilities.
@@ -626,7 +640,7 @@
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CONFIG_FPGA			CONFIG_SYS_SPARTAN3
+// #define CONFIG_FPGA			CONFIG_SYS_SPARTAN3
 //#define FPGA_DEBUG
 #define CONFIG_FPGA_COUNT		2
 #define CONFIG_FPGA_XILINX
@@ -655,14 +669,14 @@
  * I2C bus
  */
 
-#define	CONFIG_HARD_I2C		1	/* I2C with hardware support    */
+// #define	CONFIG_HARD_I2C		1	/* I2C with hardware support    */
 
-#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
+// #define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+// #define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CONFIG_I2C_CMD_TREE
-#define CONFIG_I2C_MULTI_BUS	2
-#define CONFIG_SYS_I2C_NOPROBES 	{ }
+// #define CONFIG_I2C_CMD_TREE
+// #define CONFIG_I2C_MULTI_BUS	2
+// #define CONFIG_SYS_I2C_NOPROBES 	{ }
 
 # define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC02                */
 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address             */
@@ -773,7 +787,7 @@
 #define CONFIG_SYS_OCR2_B_VAL		0x00000000
 #define CONFIG_SYS_ICFA1_B_VAL		0xFFFFFFFF
 #define CONFIG_SYS_ICFA2_B_VAL		0xFFFFFFFF
-#define CONFIG_SYS_ICFB1_B_VAL		0xFFFFFFFF
+#define CONFIG_SYS_ICFB1_B_VAL 		0xFFFFFFFF
 #define CONFIG_SYS_ICFB2_B_VAL		0xFFFFFFFF
 #define CONFIG_SYS_DR_B_VAL		0x00000000
 #define CONFIG_SYS_GIUS_B_VAL		0xFF3FFFF0
@@ -791,7 +805,7 @@
 #define CONFIG_SYS_ICFB1_C_VAL		0xFFFFFFFF
 #define CONFIG_SYS_ICFB2_C_VAL		0xFFFFFFFF
 #define CONFIG_SYS_DR_C_VAL		0x00000000
-#define CONFIG_SYS_GIUS_C_VAL		0xFFFFFFFF
+#define CONFIG_SYS_GIUS_C_VAL		0xFFFFC07F
 #define CONFIG_SYS_ICR1_C_VAL		0x00000000
 #define CONFIG_SYS_ICR2_C_VAL		0x00000000
 #define CONFIG_SYS_IMR_C_VAL		0x00000000
@@ -821,7 +835,7 @@
 #define CONFIG_SYS_ICFB1_E_VAL		0xFFFFFFFF
 #define CONFIG_SYS_ICFB2_E_VAL		0xFFFFFFFF
 #define CONFIG_SYS_DR_E_VAL		0x00000000
-#define CONFIG_SYS_GIUS_E_VAL		0xFFFFCCF8
+#define CONFIG_SYS_GIUS_E_VAL		0xFCFFCCF8
 #define CONFIG_SYS_ICR1_E_VAL		0x00000000
 #define CONFIG_SYS_ICR2_E_VAL		0x00000000
 #define CONFIG_SYS_IMR_E_VAL		0x00000000
@@ -866,7 +880,7 @@
 #define CONFIG_SYS_AIPI2_PSR1_VAL	0xFFFFFFFF
 
 /* PCCR enable DMA FEC I2C1 IIM SDHC1 */
-#define CONFIG_SYS_PCCR0_VAL		0x05070410
+#define CONFIG_SYS_PCCR0_VAL		0x05070400
 #define CONFIG_SYS_PCCR1_VAL		0xA14A0408
 
 /* CONFIG_SKIP_LOWLEVEL_INIT bypass lowlevel init in bootstrap mode */


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