[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2676-g8c3329c
Brought to you by:
sszy
Menu
▾
▴
[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2676-g8c3329c
|
From: jorasse <jo...@us...> - 2012-01-12 19:45:54
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 8c3329cb82dad286bec60ef71bff5aeebfa0a3dd (commit)
via bc1f0da61a19774d0fab3ddef22368e28f95089a (commit)
via f90a0b67282ac673641f23492fe8528b16c7d4a8 (commit)
via bd90491cff20602eb69487c9c4039fee4f914fc0 (commit)
from 2310cbb7c81f94b304eaf5936871c7a041183280 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 8c3329cb82dad286bec60ef71bff5aeebfa0a3dd
Merge: bc1f0da 2310cbb
Author: Eric Jarrige <eri...@ar...>
Date: Thu Jan 12 20:45:09 2012 +0100
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit bc1f0da61a19774d0fab3ddef22368e28f95089a
Author: Eric Jarrige <eri...@ar...>
Date: Thu Jan 12 20:39:19 2012 +0100
[UBOOT] apf51: preliminary migration to u-Boot 2011.12
commit f90a0b67282ac673641f23492fe8528b16c7d4a8
Author: Eric Jarrige <eri...@ar...>
Date: Thu Jan 12 20:30:30 2012 +0100
[LINUX] apf51: make kernel auto relocatble on boot
commit bd90491cff20602eb69487c9c4039fee4f914fc0
Author: Eric Jarrige <eri...@ar...>
Date: Thu Jan 12 20:07:54 2012 +0100
[UBOOT] Workaround to fix bug #102: reboot from Linux doesn't work on APF51, most of the time
-----------------------------------------------------------------------
Summary of changes:
.../armadeus/apf51/apf51-linux-2.6.38.config | 1 +
.../device/armadeus/apf51/apf51-u-boot-2010.03.h | 2 +-
.../u-boot/2010.03/u-boot-2010.03-401-apf51.patch | 5 +-
patches/u-boot/2011.12/400-imx51.patch | 442 ++++++++++++++++
.../401-apf51.patch} | 553 ++++++++++----------
patches/u-boot/2011.12/403-apf51-wdog.patch | 20 +
.../u-boot/2011.12/405-remove_extra_printk.patch | 25 +
.../407-imx51-nand.patch} | 8 +-
.../409-apf51-nand-spl.patch} | 179 +-------
.../410-imx-iim.patch} | 156 ++----
.../2011.12/411-Fix-high-voltage-nand-sd.patch | 29 +
..._i2c-add_support_for_the_iMX51_processor.patch} | 7 +-
patches/u-boot/2011.12/425-cortex-relocation.patch | 23 +
13 files changed, 859 insertions(+), 591 deletions(-)
create mode 100644 patches/u-boot/2011.12/400-imx51.patch
copy patches/u-boot/{2010.03/u-boot-2010.03-401-apf51.patch => 2011.12/401-apf51.patch} (83%)
create mode 100644 patches/u-boot/2011.12/403-apf51-wdog.patch
create mode 100644 patches/u-boot/2011.12/405-remove_extra_printk.patch
copy patches/u-boot/{2010.03/u-boot-2010.03-407-imx51-nand.patch => 2011.12/407-imx51-nand.patch} (99%)
copy patches/u-boot/{2010.03/u-boot-2010.03-409-apf51-nand-spl.patch => 2011.12/409-apf51-nand-spl.patch} (77%)
copy patches/u-boot/{2010.03/u-boot-2010.03-410-imx-iim.patch => 2011.12/410-imx-iim.patch} (82%)
create mode 100644 patches/u-boot/2011.12/411-Fix-high-voltage-nand-sd.patch
copy patches/u-boot/{2010.03/u-boot-2010.03-424-armadeus-mxc_i2c-add_support_for_the_iMX51_processor.patch => 2011.12/424-armadeus-mxc_i2c-add_support_for_the_iMX51_processor.patch} (77%)
create mode 100644 patches/u-boot/2011.12/425-cortex-relocation.patch
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-2.6.38.config b/buildroot/target/device/armadeus/apf51/apf51-linux-2.6.38.config
index 1b5f7e3..25526b3 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-linux-2.6.38.config
+++ b/buildroot/target/device/armadeus/apf51/apf51-linux-2.6.38.config
@@ -26,6 +26,7 @@ CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_AUTO_ZRELADDR=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEBUG=y
CONFIG_CPU_FREQ_STAT_DETAILS=y
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
index c0732f3..78fb140 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
@@ -29,7 +29,7 @@
#define CONFIG_VERSION_VARIABLE
#define CONFIG_ENV_VERSION "0.5"
-#define CONFIG_IDENT_STRING " apf51 patch 0.6"
+#define CONFIG_IDENT_STRING " apf51 patch 0.7"
//#define APF51_PROTO
//#define APF51_RECOVER
diff --git a/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch b/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch
index 5c8d7b9..0d4e2e6 100644
--- a/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch
+++ b/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch
@@ -2,7 +2,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ u-boot-2010.03/board/armadeus/apf51/apf51.c 2011-06-21 16:59:15.000000000 +0200
-@@ -0,0 +1,1157 @@
+@@ -0,0 +1,1160 @@
+/*
+ * (C) Copyright 2010 Eric Jarrige, Armadeus Project
+ *
@@ -911,6 +911,9 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ writel((CONFIG_PLL1_FREQ/CONFIG_ARM_CLK_FREQ)-1,
+ CCM_BASE_ADDR + CLKCTL_CACRR);
+
++ /* Disable warm reset */
++ writel(0x560, SRC_BASE_ADDR);
++
+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_1_BASE + 0x100;
diff --git a/patches/u-boot/2011.12/400-imx51.patch b/patches/u-boot/2011.12/400-imx51.patch
new file mode 100644
index 0000000..ea1f2bb
--- /dev/null
+++ b/patches/u-boot/2011.12/400-imx51.patch
@@ -0,0 +1,442 @@
+diff -purN u-boot-custom.ori/arch/arm/cpu/armv7/imx-common/timer.c u-boot-custom/arch/arm/cpu/armv7/imx-common/timer.c
+--- u-boot-custom.ori/arch/arm/cpu/armv7/imx-common/timer.c 2011-12-19 12:12:54.000000000 +0100
++++ u-boot-custom/arch/arm/cpu/armv7/imx-common/timer.c 2011-12-21 13:01:57.460272879 +0100
+@@ -97,7 +97,7 @@ ulong get_timer(ulong base)
+ void __udelay(unsigned long usec)
+ {
+ unsigned long now, start, tmo;
+- tmo = usec * (CLK_32KHZ / 1000) / 1000;
++ tmo = usec * (CLK_32KHZ / CONFIG_SYS_HZ) / 1000;
+
+ if (!tmo)
+ tmo = 1;
+--- u-boot-2011.12/arch/arm/cpu/armv7/mx5/lowlevel_init.S 2011-12-23 20:25:35.000000000 +0100
++++ u-boot-custom/arch/arm/cpu/armv7/mx5/lowlevel_init.S 2012-01-08 16:57:41.168590215 +0100
+@@ -23,6 +23,71 @@
+ #include <asm/arch/imx-regs.h>
+ #include <generated/asm-offsets.h>
+
++#ifndef CONFIG_SYS_PLL_DP_CTL_VAL
++/* use internal oscillator */
++#define CONFIG_SYS_PLL_DP_CTL_VAL 0x00001232
++#endif
++
++#ifndef CONFIG_SYS_CCSR_VAL
++/* use internal oscillator */
++#define CONFIG_SYS_CCSR_VAL 0x00000000
++#endif
++
++/* define default SDRAM config */
++#ifndef CONFIG_SYS_DRR_MR_VAL
++#define CONFIG_SYS_DRR_MR_VAL 0x0632
++#endif
++
++#ifndef CONFIG_SYS_DRR_EMR_VAL
++#define CONFIG_SYS_DRR_EMR_VAL 0x040
++#endif
++
++#ifndef CONFIG_SYS_SDRAM_ESDCTL_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDCTL_REGISTER_VAL 0xb2a20000
++#endif
++#ifndef CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL 0xE99668BA
++#endif
++#ifndef CONFIG_SYS_SDRAM_ESDMISC_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDMISC_REGISTER_VAL 0x000ad6d0
++#endif
++#ifndef CONFIG_SYS_SDRAM_ESDCDLY1_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDCDLY1_REGISTER_VAL 0x00F48000
++#endif
++#ifndef CONFIG_SYS_SDRAM_ESDCDLY2_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDCDLY2_REGISTER_VAL 0x00F48000
++#endif
++#ifndef CONFIG_SYS_SDRAM_ESDCDLY3_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDCDLY3_REGISTER_VAL 0x00F48000
++#endif
++#ifndef CONFIG_SYS_SDRAM_ESDCDLY4_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDCDLY4_REGISTER_VAL 0x00F48000
++#endif
++#ifndef CONFIG_SYS_SDRAM_ESDCDLY5_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDCDLY5_REGISTER_VAL 0x00F48000
++#endif
++#ifndef CONFIG_SYS_SDRAM_ESDGPR_REGISTER_VAL
++#define CONFIG_SYS_SDRAM_ESDGPR_REGISTER_VAL 0x90000000
++#endif
++
++#ifndef CONFIG_SYS_CBCDR_VAL
++#define CONFIG_SYS_CBCDR_VAL 0x59E35100
++#endif
++
++#ifndef CONFIG_SYS_CBCMR_VAL
++/* Use lp_apm (24MHz) source for perclk */
++#define CONFIG_SYS_CBCMR_VAL 0x000020C2
++#endif
++
++#ifndef CONFIG_SYS_CSCDR1_VAL
++#define CONFIG_SYS_CSCDR1_VAL 0x00C30321
++#endif
++
++#ifndef CONFIG_SYS_CBCMR1_VAL
++/* Use PLL 2 for UART's, get 66.5MHz from it */
++#define CONFIG_SYS_CBCMR1_VAL 0xA5A2A020
++#endif
++
+ /*
+ * L2CC Cache setup/invalidation/disable
+ */
+@@ -81,23 +146,23 @@
+ ldr r0, =M4IF_BASE_ADDR
+
+ ldr r1, =0x00000203
+- str r1, [r0, #0x40]
++ str r1, [r0, #M4IF_FBPM0]
+
+ ldr r1, =0x0
+- str r1, [r0, #0x44]
++ str r1, [r0, #M4IF_FBPM1]
+
+ ldr r1, =0x00120125
+- str r1, [r0, #0x9C]
++ str r1, [r0, #M4IF_FPWC]
+
+ ldr r1, =0x001901A3
+- str r1, [r0, #0x48]
++ str r1, [r0, #M4IF_MIF4]
+
+ #endif
+ .endm /* init_m4if */
+
+ .macro setup_pll pll, freq
+ ldr r0, =\pll
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL_VAL
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+@@ -114,7 +179,7 @@
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL_VAL
+ str r1, [r0, #PLL_DP_CTL]
+ 1: ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+@@ -154,6 +219,16 @@
+ ldr r0, =CCM_BASE_ADDR
+
+ #if defined(CONFIG_MX51)
++#ifdef CONFIG_SYS_CCR_VAL
++ ldr r1, =CONFIG_SYS_CCR_VAL
++ str r1, [r0, #CLKCTL_CCMR]
++
++ /* make sure clocks are ready */
++1: ldr r1, [r0, #CLKCTL_CSR]
++ cmp r1, #CONFIG_SYS_CSR_VAL
++ bne 1b
++#endif
++
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+@@ -198,7 +273,7 @@
+ #endif
+
+ /* Switch ARM to step clock */
+- mov r1, #0x4
++ mov r1, #CONFIG_SYS_CCSR_VAL | 0x04
+ str r1, [r0, #CLKCTL_CCSR]
+
+ #if defined(CONFIG_MX51_PLL_ERRATA)
+@@ -233,7 +308,7 @@
+ /* Set the platform clock dividers */
+ ldr r0, =ARM_BASE_ADDR
+ ldr r1, =0x00000725
+- str r1, [r0, #0x14]
++ str r1, [r0, #CORTEX_A8_ICGC]
+
+ ldr r0, =CCM_BASE_ADDR
+
+@@ -250,16 +325,16 @@
+ #endif
+ str r1, [r0, #CLKCTL_CACRR]
+ /* Switch ARM back to PLL 1 */
+- mov r1, #0
++ mov r1, #CONFIG_SYS_CCSR_VAL
+ str r1, [r0, #CLKCTL_CCSR]
+
+ #if defined(CONFIG_MX51)
+ /* setup the rest */
+- /* Use lp_apm (24MHz) source for perclk */
+- ldr r1, =0x000020C2
++ /* select source for perclk */
++ ldr r1, =CONFIG_SYS_CBCMR_VAL
+ orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
++ /* ddr clock from PLL 1 */
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ str r1, [r0, #CLKCTL_CBCDR]
+ #endif
+@@ -279,9 +354,9 @@
+
+ #if defined(CONFIG_MX51)
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+- ldr r1, =0xA5A2A020
++ ldr r1, =CONFIG_SYS_CBCMR1_VAL
+ str r1, [r0, #CLKCTL_CSCMR1]
+- ldr r1, =0x00C30321
++ ldr r1, =CONFIG_SYS_CSCDR1_VAL
+ str r1, [r0, #CLKCTL_CSCDR1]
+ #elif defined(CONFIG_MX53)
+ ldr r1, [r0, #CLKCTL_CSCDR1]
+@@ -324,6 +399,11 @@ lowlevel_init:
+ str r1, [r0, #0x4]
+ #endif
+
++ /* ARM errata ID #468414 */
++ mrc 15, 0, r1, c1, c0, 1
++ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
++ mcr 15, 0, r1, c1, c0, 1
++
+ init_l2cc
+
+ init_aips
+@@ -332,9 +412,34 @@ lowlevel_init:
+
+ init_clock
+
+- /* r12 saved upper lr*/
++/* make U-Boot runnable form "almost" anywhere */
++/* but SYS_TEXT_BASE should be in RAM */
++copy2ram: /* populate _TEXT_BASE with U-Boot from load addr */
++ ldr r0, _start_adr
++ ldr r1, _copy2ram
++ sub r1, r1, r0
++ adr r0, copy2ram
++ sub r0, r0, r1
++ ldr r1, =CONFIG_SYS_TEXT_BASE
++ cmp r0, r1
++ beq end_of_copy2ram /* skip U-Boot copy */
++ ldr r2, =CONFIG_SYS_MONITOR_LEN
++ add r2, r2, r0 /* r2 <- source end address */
++
++copy_loop:
++ ldmia r0!, {r9-r10} /* copy from source address [r0] */
++ stmia r1!, {r9-r10} /* copy to target address [r1] */
++ cmp r0, r2 /* until source end address [r2] */
++ blo copy_loop
++
++end_of_copy2ram:
+ mov pc,lr
+
++_copy2ram:
++ .word copy2ram
++_start_adr:
++ .word _start /* r12 saved upper lr*/
++
+ /* Board level setting value */
+ W_DP_OP_864: .word DP_OP_864
+ W_DP_MFD_864: .word DP_MFD_864
+diff -purN u-boot-custom.ori/arch/arm/include/asm/arch-mx5/imx-regs.h u-boot-custom/arch/arm/include/asm/arch-mx5/imx-regs.h
+--- u-boot-custom.ori/arch/arm/include/asm/arch-mx5/imx-regs.h 2011-12-19 12:12:54.000000000 +0100
++++ u-boot-custom/arch/arm/include/asm/arch-mx5/imx-regs.h 2011-12-21 17:59:31.411491501 +0100
+@@ -236,6 +236,7 @@
+ #define M4IF_FBPM0 0x40
+ #define M4IF_FIDBP 0x48
+
++#ifndef DP_OP_800
+ /* Assuming 24MHz input clock with doubler ON */
+ /* MFI PDF */
+ #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
+@@ -270,6 +271,7 @@
+ #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+ #define DP_MFD_216 (4 - 1)
+ #define DP_MFN_216 3
++#endif /* DP_OP_800 */
+
+ #define CHIP_REV_1_0 0x10
+ #define CHIP_REV_1_1 0x11
+@@ -282,6 +284,148 @@
+
+ #define IMX_IIM_BASE (IIM_BASE_ADDR)
+
++/* DDR commands */
++/* cs ChipSelect in range of 0..1 */
++/* ba Bank Address in range of 0..3 */
++/* addr Pseudo Address as expected by the DDR */
++
++#define CONFIG_SYS_DDR_NOP_CMD(cs) (0x00008000 + (cs << 2))
++#define CONFIG_SYS_DRR_PRECHARGE_CMD(cs, ba) (0x04008008 + (cs << 2) + ba)
++#define CONFIG_SYS_DRR_AUTOREFRESH_CMD(cs) (0x00008010 + (cs << 2))
++#define CONFIG_SYS_DRR_LMR_CMD(cs, ba, addr) (0x00008018 + (addr << 16) + (cs << 2) + ba)
++
++//#ifdef __ASSEMBLY__
++
++/* ESDCTL */
++#define ESDCTL_ESDCTL0 0x00
++#define ESDCTL_ESDCFG0 0x04
++#define ESDCTL_ESDCTL1 0x08
++#define ESDCTL_ESDCFG1 0x0C
++#define ESDCTL_ESDMISC 0x10
++#define ESDCTL_ESDSCR 0x14
++#define ESDCTL_ESDCDLY1 0x20
++#define ESDCTL_ESDCDLY2 0x24
++#define ESDCTL_ESDCDLY3 0x28
++#define ESDCTL_ESDCDLY4 0x2C
++#define ESDCTL_ESDCDLY5 0x30
++#define ESDCTL_ESDCDLYGD 0x34
++
++/* M4IF */
++#define M4IF_PSM0 0x000
++#define M4IF_PSM1 0x004
++#define M4IF_MDSR6 0x018
++#define M4IF_MDSR7 0x01C
++#define M4IF_MDSR8 0x020
++#define M4IF_MDSR0 0x024
++#define M4IF_MDSR1 0x028
++#define M4IF_MDSR2 0x02C
++#define M4IF_MDSR3 0x030
++#define M4IF_MDSR4 0x034
++#define M4IF_MDSR5 0x038
++/*#define M4IF_FBPM0 0x040*/
++#define M4IF_FBPM1 0x044
++#define M4IF_MIF4 0x048
++#define M4IF_SBAR0 0x04C
++#define M4IF_SERL0 0x050
++#define M4IF_SERH0 0x054
++#define M4IF_SSRL0 0x058
++#define M4IF_SSRH0 0x05C
++#define M4IF_SBAR1 0x060
++#define M4IF_SERL1 0x064
++#define M4IF_SERH1 0x068
++#define M4IF_SSRL1 0x06C
++#define M4IF_SSRH1 0x070
++#define M4IF_I2ULA 0x074
++#define M4IF_I2ACR 0x078
++#define M4IF_RINT2 0x07C
++#define M4IF_SBS0 0x084
++#define M4IF_SBS1 0x088
++#define M4IF_MCR0 0x08C
++#define M4IF_MCR1 0x090
++#define M4IF_MDCR 0x094
++#define M4IF_FACR 0x098
++#define M4IF_FPWC 0x09C
++
++/* IOMUX */
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x04A4
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x04A8
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE 0x04AC
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x04B0
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x04B4
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK 0x04B8
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x04BC
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x04C0
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x04C4
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x04C8
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 0x04CC
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 0x04D0
++
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x04D4
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x04D8
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x04DC
++#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x04E0
++#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2 0x050C
++#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1 0x050C
++#define IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0 0x0510
++
++#define IOMUXC_SW_PAD_CTL_GRP_DDRPKS 0x0820
++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B4 0x082C
++#define IOMUXC_SW_PAD_CTL_GRP_INDDR 0x0830
++#define IOMUXC_SW_PAD_CTL_GRP_PKEDDR 0x0838
++#define IOMUXC_SW_PAD_CTL_GRP_DDR_A0 0x083C
++#define IOMUXC_SW_PAD_CTL_GRP_DDR_A1 0x0848
++#define IOMUXC_SW_PAD_CTL_GRP_DDRAPUS 0x084C
++#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR0 0x085C
++#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR1 0x0864
++#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR2 0x086C
++#define IOMUXC_SW_PAD_CTL_GRP_HVDDR 0x0870
++#define IOMUXC_SW_PAD_CTL_GRP_HYSDDR3 0x0874
++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B0 0x0878
++#define IOMUXC_SW_PAD_CTL_GRP_DDRAPKS 0x087C
++
++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B1 0x0880
++#define IOMUXC_SW_PAD_CTL_GRP_DDRPUS 0x0884
++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B2 0x088C
++#define IOMUXC_SW_PAD_CTL_GRP_PKEADDR 0x0890
++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_SR_B4 0x089C
++#define IOMUXC_SW_PAD_CTL_GRP_INMODE1 0x08A0
++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B0 0x08A4
++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B1 0x08AC
++
++#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0 0x08B0
++
++#define IOMUXC_SW_PAD_CTL_GRP_DRAM_B2 0x08B8
++
++#define IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1 0x08BC
++#ifdef __ASSEMBLY__
++#define PAD_CTL_SRE_SLOW (0x0 << 0) /* Slow slew rate */
++#define PAD_CTL_SRE_FAST (0x1 << 0) /* Fast slew rate */
++#define PAD_CTL_DRV_LOW (0x0 << 1) /* Low drive strength */
++#define PAD_CTL_DRV_MEDIUM (0x1 << 1) /* Medium drive strength */
++#define PAD_CTL_DRV_HIGH (0x2 << 1) /* High drive strength */
++#define PAD_CTL_DRV_MAX (0x3 << 1) /* Max drive strength */
++#define PAD_CTL_ODE_OPENDRAIN_NONE (0x0 << 3) /* Opendrain disable */
++#define PAD_CTL_ODE_OPENDRAIN_ENABLE (0x1 << 3)/* Opendrain enable */
++#define PAD_CTL_100K_PD (0x0 << 4) /* 100Kohm pulldown */
++#define PAD_CTL_47K_PU (0x1 << 4) /* 47Kohm pullup */
++#define PAD_CTL_100K_PU (0x2 << 4) /* 100Kohm pullup */
++#define PAD_CTL_22K_PU (0x3 << 4) /* 22Kohm pullup */
++#define PAD_CTL_PUE_KEEPER (0x0 << 6) /* enable pulldown */
++#define PAD_CTL_PUE_PULL (0x1 << 6) /* enable pullup */
++#define PAD_CTL_PKE_NONE (0x0 << 7) /* Disable pullup/pulldown */
++#define PAD_CTL_PKE_ENABLE (0x1 << 7) /* Enable pullup/pulldown */
++#define PAD_CTL_HYS_NONE (0x0 << 8) /* Hysteresis disabled */
++#define PAD_CTL_HYS_ENABLE (0x1 << 8) /* Hysteresis enabled */
++#define PAD_CTL_DDR_INPUT_CMOS (0x0 << 9)/* DDR input CMOS */
++#define PAD_CTL_DDR_INPUT_DDR (0x1 << 9)/* DDR input DDR */
++#define PAD_CTL_DRV_VOT_LOW (0x0 << 13) /* Low voltage mode */
++#define PAD_CTL_DRV_VOT_HIGH (0x1 << 13)/* High voltage mode */
++#endif /* __ASSEMBLY__ */
++/* ARM CORTEX A8*/
++#define CORTEX_A8_ICGC 0x14
++
++//#endif /* __ASSEMBLY__ */
++
+ #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+ #include <asm/types.h>
+
+--- u-boot-2011.12/arch/arm/cpu/armv7/cpu.c 2011-12-23 20:25:35.000000000 +0100
++++ u-boot-custom/arch/arm/cpu/armv7/cpu.c 2012-01-09 22:44:26.148876883 +0100
+@@ -79,5 +79,9 @@ int cleanup_before_linux(void)
+ */
+ invalidate_dcache_all();
+
++#ifndef CONFIG_L2_OFF
++ v7_outer_cache_enable();
++#endif
++
+ return 0;
+ }
+--- u-boot-custom.ref/arch/arm/lib/cache-cp15.c 2011-12-23 20:25:35.000000000 +0100
++++ u-boot-custom/arch/arm/lib/cache-cp15.c 2012-01-09 22:28:01.960696861 +0100
+@@ -86,10 +86,17 @@ static inline void mmu_setup(void)
+ /* Set the access control to all-supervisor */
+ asm volatile("mcr p15, 0, %0, c3, c0, 0"
+ : : "r" (~0));
++
++ /* Workaround for arm errata #709718 */
++ /* Setup PRRR so device is always mapped to non-shared */
++ asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/);
++ i &= (~(3 << 0x10));
++ asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/);
++
+ /* and enable the mmu */
+ reg = get_cr(); /* get control reg. */
+ cp_delay();
+- set_cr(reg | CR_M);
++ set_cr(reg | CR_M | CR_A | CR_Z);
+ }
+
+ static int mmu_enabled(void)
+
diff --git a/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch b/patches/u-boot/2011.12/401-apf51.patch
similarity index 83%
copy from patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch
copy to patches/u-boot/2011.12/401-apf51.patch
index 5c8d7b9..51ac68b 100644
--- a/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch
+++ b/patches/u-boot/2011.12/401-apf51.patch
@@ -1,10 +1,10 @@
-Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf51/apf51.c 2011-06-21 16:59:15.000000000 +0200
-@@ -0,0 +1,1157 @@
++++ u-boot-custom/board/armadeus/apf51/apf51.c 2012-01-12 17:19:58.434303119 +0100
+@@ -0,0 +1,1263 @@
+/*
-+ * (C) Copyright 2010 Eric Jarrige, Armadeus Project
++ * (C) Copyright 2010-2012 Eric Jarrige, Armadeus Project
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
@@ -27,11 +27,15 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+
+#include <common.h>
+#include <command.h>
++#include <asm/armv7.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
-+#include <asm/arch/asm-offsets.h>
-+#include <asm/arch/mx51_pins.h>
++#include <generated/asm-offsets.h>
++#include <asm/arch/crm_regs.h>
++#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/gpio.h>
+#include <asm/errno.h>
+#include <i2c.h>
+//#include <asm/arch/imx_spi.h>
@@ -43,7 +47,6 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+
+DECLARE_GLOBAL_DATA_PTR;
+
-+static u32 system_rev;
+unsigned long boot_verb = 0;
+
+
@@ -72,22 +75,27 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+}
+
+
-+u32 get_board_rev(void)
++int dram_init(void)
+{
-+ return system_rev;
++ u32 size1, size2=0;
++
++ size1 = get_ram_size((void *)CONFIG_SYS_SDRAM_1_BASE, PHYS_SDRAM_1_SIZE);
++#if ( CONFIG_SYS_NR_DRAM_BANKS > 1 )
++ size2 = get_ram_size((void *)CONFIG_SYS_SDRAM_2_BASE, PHYS_SDRAM_2_SIZE);
++#endif
++
++ gd->ram_size = size1 + size2;
++ return 0;
+}
+
-+int dram_init(void)
++void dram_init_banksize(void)
+{
-+#if ( CONFIG_SYS_NR_DRAM_BANKS > 0 )
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_1_BASE;
-+ gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_1_SIZE;
-+#endif
++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#if ( CONFIG_SYS_NR_DRAM_BANKS > 1 )
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_2_BASE;
-+ gd->bd->bi_dram[1].size = CONFIG_SYS_SDRAM_2_SIZE;
++ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
-+ return 0;
+}
+
+void setup_usb(void)
@@ -194,8 +202,8 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ mxc_iomux_set_pad(MX51_PIN_UART2_RXD, UART_PAD_CFG);
+ mxc_iomux_set_pad(MX51_PIN_UART2_TXD, UART_PAD_CFG);
+
-+ mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,INPUT_CTL_PATH2);
-+ mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,INPUT_CTL_PATH3);
++ mxc_iomux_set_input(MX51_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,INPUT_CTL_PATH2);
++ mxc_iomux_set_input(MX51_UART2_IPP_UART_RTS_B_SELECT_INPUT,INPUT_CTL_PATH3);
+ /*
+ * uart3
+ */
@@ -212,7 +220,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ mxc_iomux_set_pad(MX51_PIN_UART3_RXD, UART_PAD_CFG);
+ mxc_iomux_set_pad(MX51_PIN_UART3_TXD, UART_PAD_CFG);
+
-+ mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,INPUT_CTL_PATH4);
++ mxc_iomux_set_input(MX51_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,INPUT_CTL_PATH4);
+#endif
+}
+
@@ -253,8 +261,8 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS4, AUD_PAD_CFG);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS5, AUD_PAD_CFG);
+
-+ mxc_iomux_set_input(MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,INPUT_CTL_PATH1);
+ /*
+ * audmux6
+ */
@@ -418,7 +426,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST)
+
+ /* pwm 1 & 2 */
-+ mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
++ mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_2, GPIO_PAD_CFG);
+
+ mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT1);
@@ -619,58 +627,14 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D14, CSPI_PAD_CFG);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D15, CSPI_PAD_CFG);
+
-+ mxc_iomux_set_input(MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
++ mxc_iomux_set_input(MX51_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ INPUT_CTL_PATH1);
+}
+
-+#define GPIO_DR 0x00 /* Data Register */
-+#define GPIO_GDIR 0x04 /* GPIO direction */
-+#define GPIO_PSR 0x08 /* Pad Status Reg */
-+#define GPIO_ICR1 0x0c /* Interrupt Configuration Reg 1 */
-+#define GPIO_ICR2 0x10 /* Interrupt Configuration Reg 2 */
-+#define GPIO_IMR 0x14 /* Interrupt Mask Reg */
-+#define GPIO_ISR 0x18 /* Interrupt Status Reg */
-+#define GPIO_EDR 0x1c /* Edge Detect Reg */
-+
-+#define PORT_BADDR(n) (GPIO1_BASE_ADDR + (n) * 0x4000)
-+
-+void imx_gpio_pin_cfg_dir(unsigned int pin, int dir)
-+{
-+ u32 gpio_num = IOMUX_TO_GPIO(pin);
-+ u32 gpio_off = GPIO_TO_INDEX(gpio_num);
-+ u32 baddr = PORT_BADDR(GPIO_TO_PORT(gpio_num));
-+
-+ if (dir)
-+ __REG(baddr + GPIO_GDIR) |= (1 << gpio_off);
-+ else
-+ __REG(baddr + GPIO_GDIR) &= ~(1 << gpio_off);
-+}
-+
-+void imx_gpio_pin_set(unsigned int pin, int value)
-+{
-+ u32 gpio_num = IOMUX_TO_GPIO(pin);
-+ u32 gpio_off = GPIO_TO_INDEX(gpio_num);
-+ u32 baddr = PORT_BADDR(GPIO_TO_PORT(gpio_num));
-+
-+ if (value)
-+ __REG(baddr + GPIO_DR) |= (1 << gpio_off);
-+ else
-+ __REG(baddr + GPIO_DR) &= ~(1 << gpio_off);
-+}
-+
-+int imx_gpio_pin_get(unsigned int pin)
-+{
-+ u32 gpio_num = IOMUX_TO_GPIO(pin);
-+ u32 gpio_off = GPIO_TO_INDEX(gpio_num);
-+ u32 baddr = PORT_BADDR(GPIO_TO_PORT(gpio_num));
-+
-+ return (__REG(baddr + GPIO_PSR) >> gpio_off) & 1;
-+}
-+
-+
+#ifdef CONFIG_I2C_MXC
+#define I2C_PAD_CFG (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | \
+ PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE)
++
+static void setup_i2c(unsigned int module_base)
+{
+ /*
@@ -695,7 +659,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ /* SDA */
+ mxc_request_iomux(MX51_PIN_EIM_D27,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
-+ mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
++ mxc_iomux_set_input(MX51_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ break;
+
@@ -712,9 +676,9 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+#define CFG_FEC_PAD (PAD_CTL_DRV_MEDIUM | PAD_CTL_PUE_KEEPER | \
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_VOT_HIGH)
+
-+ /* Ethernet PHY Reset */
-+ imx_gpio_pin_set(CONFIG_SYS_PHY_RESET_GPIO,0);
-+ imx_gpio_pin_cfg_dir(CONFIG_SYS_PHY_RESET_GPIO, 1);
++
++ gpio_set_value(CONFIG_SYS_PHY_RESET_GPIO, 0);
++ gpio_direction_output(CONFIG_SYS_PHY_RESET_GPIO, 0);
+
+ /* FEC TX_ER muxed with DI_GP3 */
+ mxc_request_iomux(MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT2);
@@ -789,29 +753,48 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ mxc_iomux_set_pad(MX51_PIN_DISP2_DAT15, CFG_FEC_PAD);
+
+ /* FEC signals involved in daisy chain should be mapped to DISP2/DI2 pads */
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_COL_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_CRS_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, INPUT_CTL_PATH1);
-+ mxc_iomux_set_input(MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, INPUT_CTL_PATH1);
-+
-+ imx_gpio_pin_set(CONFIG_SYS_PHY_RESET_GPIO,1);
++ mxc_iomux_set_input(MX51_FEC_FEC_COL_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_CRS_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_MDI_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_RDATA_0_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_RDATA_1_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_RDATA_2_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_RDATA_3_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_RX_CLK_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_RX_DV_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_RX_ER_SELECT_INPUT, INPUT_CTL_PATH1);
++ mxc_iomux_set_input(MX51_FEC_FEC_TX_CLK_SELECT_INPUT, INPUT_CTL_PATH1);
++
++ /* Ethernet PHY leave Reset state (POR only)*/
++ gpio_set_value(CONFIG_SYS_PHY_RESET_GPIO, 1);
++ gpio_direction_output(CONFIG_SYS_PHY_RESET_GPIO, 1);
+#endif
+}
+
-+#ifdef CONFIG_NET_MULTI
+int board_eth_init(bd_t *bis)
+{
++#define STR_ENV_ETHADDR "ethaddr"
+ int rc = -ENODEV;
++
++#if defined(CONFIG_FEC_MXC)
++ struct eth_device *dev;
++ uchar eth_addr[6];
++
++ rc = fecmxc_initialize(bis);
++
++ if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
++ dev = eth_get_dev_by_index(0);
++ if (dev) {
++ eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
++ } else {
++ printf("FEC APF51: Couldn't get eth device\n");
++ rc = -1;
++ }
++ }
++#endif
++
+ return rc;
+}
-+#endif
+
+#ifdef CONFIG_FSL_MMC
+volatile u32 *esdhc_base_pointer;
@@ -903,17 +886,17 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+}
+#endif
+
-+int board_init(void)
++int board_early_init_f(void)
+{
-+ system_rev = get_cpu_rev();
++ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
++ struct src *src = (struct src *)SRC_BASE_ADDR;
+
+ /* Increase freq to CONFIG_ARM_CLK_FREQ (800MHz) */
+ writel((CONFIG_PLL1_FREQ/CONFIG_ARM_CLK_FREQ)-1,
-+ CCM_BASE_ADDR + CLKCTL_CACRR);
++ &mxc_ccm->cacrr);
+
-+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-+ /* address of boot parameters */
-+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_1_BASE + 0x100;
++ /* Disable warm reset */
++ writel(0x560, &src->scr);
+
+ setup_misc();
+ setup_uart();
@@ -922,7 +905,6 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ setup_fec();
+#ifdef CONFIG_I2C_MXC
+ setup_i2c(I2C2_BASE_ADDR);
-+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+ setup_display();
+ setup_usb();
@@ -933,6 +915,15 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+#ifdef CONFIG_FPGA
+ setup_fpga();
+#endif
++
++ return 0;
++}
++
++int board_init(void)
++{
++ /* address of boot parameters */
++ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_1_BASE + 0x100;
++
+ return 0;
+}
+
@@ -942,6 +933,15 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+int
+misc_init_r (void)
+{
++#ifdef CONFIG_I2C_MXC
++ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
++#endif
++ return 0;
++}
++
++#ifdef BOARD_LATE_INIT
++int board_late_init(void)
++{
+ char *s;
+ u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
+ size_t end = 0;
@@ -974,12 +974,6 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+
+ return 0;
+}
-+
-+#ifdef BOARD_LATE_INIT
-+int board_late_init(void)
-+{
-+ return 0;
-+}
+#endif
+
+/*************************************************************************
@@ -991,37 +985,149 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
-+ struct wdog *imx_wdog1 = (struct wdog *)WDOG1_BASE_ADDR;
-+ __raw_writew(0x5555, &imx_wdog1->wsr);
-+ __raw_writew(0xaaaa, &imx_wdog1->wsr);
++ struct wdog_regs *imx_wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
++ writew(0x5555, &imx_wdog1->wsr);
++ writew(0xaaaa, &imx_wdog1->wsr);
+}
+#endif
+
+int checkboard(void)
+{
-+ printf("Board: Armadeus APF51 ");
++ printf("Board: Armadeus APF51\n");
++ return 0;
++}
+
-+ puts("[");
-+ switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
-+ case 0x0001:
-+ puts("POR");
-+ break;
-+ case 0x0009:
-+ puts("RST");
-+ break;
-+ case 0x0010:
-+ case 0x0011:
-+ puts("WDOG");
-+ break;
-+ default:
-+ puts("unknown");
-+ }
-+ puts("]\n");
++#define cache_flush(void) \
++{ \
++ asm volatile ( \
++ "stmfd sp!, {r0-r5, r7, r9-r11};" \
++ "mrc p15, 1, r0, c0, c0, 1;" /*@ read clidr*/ \
++ /* @ extract loc from clidr */ \
++ "ands r3, r0, #0x7000000;" \
++ /* @ left align loc bit field*/ \
++ "mov r3, r3, lsr #23;" \
++ /* @ if loc is 0, then no need to clean*/ \
++ "beq 555f;" /* finished;" */ \
++ /* @ start clean at cache level 0*/ \
++ "mov r10, #0;" \
++ "111:" /*"loop1: */ \
++ /* @ work out 3x current cache level */ \
++ "add r2, r10, r10, lsr #1;" \
++ /* @ extract cache type bits from clidr */ \
++ "mov r1, r0, lsr r2;" \
++ /* @ mask of the bits for current cache only */ \
++ "and r1, r1, #7;" \
++ /* @ see what cache we have at this level*/ \
++ "cmp r1, #2;" \
++ /* @ skip if no cache, or just i-cache*/ \
++ "blt 444f;" /* skip;" */ \
++ /* @ select current cache level in cssr*/ \
++ "mcr p15, 2, r10, c0, c0, 0;" \
++ /* @ isb to sych the new cssr&csidr */ \
++ "mcr p15, 0, r10, c7, c5, 4;" \
++ /* @ read the new csidr */ \
++ "mrc p15, 1, r1, c0, c0, 0;" \
++ /* @ extract the length of the cache lines */ \
++ "and r2, r1, #7;" \
++ /* @ add 4 (line length offset) */ \
++ "add r2, r2, #4;" \
++ "ldr r4, =0x3ff;" \
++ /* @ find maximum number on the way size*/ \
++ "ands r4, r4, r1, lsr #3;" \
++ /*"clz r5, r4;" @ find bit position of way size increment*/ \
++ ".word 0xE16F5F14;" \
++ "ldr r7, =0x7fff;" \
++ /* @ extract max number of the index size*/ \
++ "ands r7, r7, r1, lsr #13;" \
++ "222:" /* loop2:" */ \
++ /* @ create working copy of max way size*/ \
++ "mov r9, r4;" \
++ "333:" /* loop3:" */ \
++ /* @ factor way and cache number into r11*/ \
++ "orr r11, r10, r9, lsl r5;" \
++ /* @ factor index number into r11*/ \
++ "orr r11, r11, r7, lsl r2;" \
++ /* @ clean & invalidate by set/way */ \
++ "mcr p15, 0, r11, c7, c14, 2;" \
++ /* @ decrement the way */ \
++ "subs r9, r9, #1;" \
++ "bge 333b;" /* loop3;" */ \
++ /* @ decrement the index */ \
++ "subs r7, r7, #1;" \
++ "bge 222b;" /* loop2;" */ \
++ "444:" /* skip: */ \
++ /*@ increment cache number */ \
++ "add r10, r10, #2;" \
++ "cmp r3, r10;" \
++ "bgt 111b;" /* loop1; */ \
++ "555:" /* "finished:" */ \
++ /* @ swith back to cache level 0 */ \
++ "mov r10, #0;" \
++ /* @ select current cache level in cssr */ \
++ "mcr p15, 2, r10, c0, c0, 0;" \
++ /* @ isb to sych the new cssr&csidr */ \
++ "mcr p15, 0, r10, c7, c5, 4;" \
++ "ldmfd sp!, {r0-r5, r7, r9-r11};" \
++ "666:" /* iflush:" */ \
++ "mov r0, #0x0;" \
++ /* @ invalidate I+BTB */ \
++ "mcr p15, 0, r0, c7, c5, 0;" \
++ /* @ drain WB */ \
++ "mcr p15, 0, r0, c7, c10, 4;" \
++ : \
++ : \
++ : "r0" /* Clobber list */ \
++ ); \
++}
+
-+ return 0;
++#ifndef CONFIG_SYS_DCACHE_OFF
++void enable_caches(void)
++{
++ /* Enable D-cache. I-cache is already enabled in start.S */
++ //dcache_enable();
++#ifndef CONFIG_L2_OFF
++ //v7_outer_cache_enable();
++#endif
++}
++
++#endif
++
++#ifndef CONFIG_L2_OFF
++void v7_outer_cache_enable(void)
++{
++ asm("mrc 15, 0, r0, c1, c0, 1");
++ asm("orr r0, r0, #0x2");
++ asm("mcr 15, 0, r0, c1, c0, 1");
++}
++
++void v7_outer_cache_disable(void)
++{
++ asm("mrc 15, 0, r0, c1, c0, 1");
++ asm("bic r0, r0, #0x2");
++ asm("mcr 15, 0, r0, c1, c0, 1");
+}
+
+/*
++void v7_outer_cache_flush_all(void)
++{
++}
++
++void v7_outer_cache_inval_all(void)
++{
++}
++
++void v7_outer_cache_flush_range(u32 start, u32 end)
++{
++}
++
++void v7_outer_cache_inval_range(u32 start, u32 end)
++{
++}
++*/
++#endif
++
++
++/*
+ * display dcd table. to delete
+ */
+int do_mx51_show_dcd_tab(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -1160,18 +1266,11 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+);
+
+
-Index: u-boot-2010.03/board/armadeus/apf51/config.mk
+Index: u-boot-2011.12/board/armadeus/apf51/Makefile
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf51/config.mk 2011-06-21 16:03:13.000000000 +0200
-@@ -0,0 +1,2 @@
-+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
-+TEXT_BASE = 0x9FF00000
-Index: u-boot-2010.03/board/armadeus/apf51/Makefile
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf51/Makefile 2011-06-21 16:03:13.000000000 +0200
-@@ -0,0 +1,50 @@
++++ u-boot-2011.12/board/armadeus/apf51/Makefile 2011-06-21 16:03:13.000000000 +0200
+@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg...@de...>
+#
@@ -1196,23 +1295,16 @@ Index: u-boot-2010.03/board/armadeus/apf51/Makefile
+
+include $(TOPDIR)/config.mk
+
-+LIB = $(obj)lib$(BOARD).a
++LIB = $(obj)lib$(BOARD).o
+
+COBJS := apf51.o fpga.o
-+SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-+
-+clean:
-+ rm -f $(SOBJS) $(OBJS)
-+
-+distclean: clean
-+ rm -f $(LIB) core *.bak .depend
++ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
@@ -1222,136 +1314,21 @@ Index: u-boot-2010.03/board/armadeus/apf51/Makefile
+sinclude $(obj).depend
+
+#########################################################################
-Index: u-boot-2010.03/board/armadeus/apf51/u-boot.lds
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf51/u-boot.lds 2011-06-21 16:03:13.000000000 +0200
-@@ -0,0 +1,64 @@
-+/*
-+ * January 2004 - Changed to support H4 device
-+ * Copyright (c) 2004 Texas Instruments
-+ *
-+ * (C) Copyright 2002
-+ * Gary Jennejohn, DENX Software Engineering, <gj...@de...>
-+ *
-+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
-+ * (C) Copyright 2010 Eric Jarrige, Armadeus Project
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-+OUTPUT_ARCH(arm)
-+ENTRY(_start)
-+SECTIONS
-+{
-+ . = 0x00000000;
-+
-+ . = ALIGN(4);
-+ .text :
-+ {
-+ /* WARNING - the following is hand-optimized to fit within */
-+ /* the sector layout of our flash chips! XXX FIXME XXX */
-+ cpu/arm_cortexa8/start.o
-+ *(.text)
-+ }
-+
-+ . = ALIGN(4);
-+ .rodata : { *(.rodata) }
-+
-+ . = ALIGN(4);
-+ .data : { *(.data) }
-+
-+ . = ALIGN(4);
-+ .got : { *(.got) }
-+
-+ . = .;
-+ __u_boot_cmd_start = .;
-+ .u_boot_cmd : { *(.u_boot_cmd) }
-+ __u_boot_cmd_end = .;
-+
-+ . = ALIGN(4);
-+ __bss_start = .;
-+ .bss : { *(.bss) }
-+ _end = .;
-+}
-Index: u-boot-2010.03/include/asm-arm/mach-types.h
-===================================================================
---- u-boot-2010.03.orig/include/asm-arm/mach-types.h 2010-03-31 23:54:39.000000000 +0200
-+++ u-boot-2010.03/include/asm-arm/mach-types.h 2011-06-21 16:03:13.000000000 +0200
-@@ -2699,6 +2699,7 @@
- #define MACH_TYPE_MX53_EVK 2716
- #define MACH_TYPE_IGEP0030 2717
- #define MACH_TYPE_AXELL_H40_H50_CTRL 2718
-+#define MACH_TYPE_APF51 2795
-
- #ifdef CONFIG_ARCH_EBSA110
- # ifdef machine_arch_type
-@@ -34944,6 +34945,18 @@
- # define machine_is_axell_h40_h50_ctrl() (0)
- #endif
-
-+#ifdef CONFIG_MACH_APF51
-+# ifdef machine_arch_type
-+# undef machine_arch_type
-+# define machine_arch_type __machine_arch_type
-+# else
-+# define machine_arch_type MACH_TYPE_APF51
-+# endif
-+# define machine_is_apf51() (machine_arch_type == MACH_TYPE_APF51)
-+#else
-+# define machine_is_apf51() (0)
-+#endif
-+
- /*
- * These have not yet been registered
- */
-Index: u-boot-2010.03/MAKEALL
-===================================================================
---- u-boot-2010.03.orig/MAKEALL 2011-06-21 16:03:13.000000000 +0200
-+++ u-boot-2010.03/MAKEALL 2011-06-21 16:03:13.000000000 +0200
-@@ -549,6 +549,7 @@
- ap946es \
- ap966 \
- apf27 \
-+ apf51 \
- cp920t \
- cp922_XA10 \
- cp926ejs \
-Index: u-boot-2010.03/Makefile
-===================================================================
---- u-boot-2010.03.orig/Makefile 2011-06-21 16:03:13.000000000 +0200
-+++ u-boot-2010.03/Makefile 2011-06-21 16:03:13.000000000 +0200
-@@ -2735,6 +2735,9 @@
- apf27_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm926ejs apf27 armadeus mx27
-
-+apf51_config : unconfig
-+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 apf51 armadeus mx51
-+
- at91cap9adk_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91
-
-Index: u-boot-2010.03/board/armadeus/apf51/fpga.h
+diff -purN u-boot-custom.ori/boards.cfg u-boot-custom/boards.cfg
+--- u-boot-custom.ori/boards.cfg 2011-12-21 11:22:35.456221000 +0100
++++ u-boot-custom/boards.cfg 2011-12-21 15:12:40.283499253 +0100
+@@ -187,6 +187,7 @@ am335x_evm arm
+ highbank arm armv7 highbank - highbank
+ efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg
+ efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg
++apf51 arm armv7 apf51 armadeus mx5
+ mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
+ mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg
+ mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
+Index: u-boot-2011.12/board/armadeus/apf51/fpga.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf51/fpga.h 2011-06-21 17:00:43.000000000 +0200
++++ u-boot-2011.12/board/armadeus/apf51/fpga.h 2011-06-21 17:00:43.000000000 +0200
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2002-2010
@@ -1392,10 +1369,10 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.h
+extern int fpga_abort_fn (int cookie);
+extern int fpga_post_fn (int cookie);
+extern int fpga_busy_fn (int cookie);
-Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+Index: u-boot-2011.12/board/armadeus/apf51/fpga.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf51/fpga.c 2011-06-21 17:10:59.000000000 +0200
++++ u-boot-2011.12/board/armadeus/apf51/fpga.c 2012-01-09 20:37:14.781633420 +0100
@@ -0,0 +1,271 @@
+/*
+ * (C) Copyright 2002-2010
@@ -1426,8 +1403,10 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+
+#if defined(CONFIG_FPGA)
+
++#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
-+#include <asm/arch/asm-offsets.h>
++#include <asm/gpio.h>
++#include <generated/asm-offsets.h>
+#include <asm/io.h>
+#include <command.h>
+#include <config.h>
@@ -1441,10 +1420,6 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+#define PRINTF(fmt,args...)
+#endif
+
-+extern void imx_gpio_pin_set(unsigned int pin, int value);
-+extern void imx_gpio_pin_cfg_dir(unsigned int pin, int dir);
-+extern int imx_gpio_pin_get(unsigned int pin);
-+
+u32 temp_clk; /* use to restore the emi_clk_sel after donwload */
+u32 temp_rcr1;
+u32 temp_wcr1;
@@ -1485,6 +1460,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+fpga_pre_fn (int cookie)
+{
+#define EMI_CLK_SEL 1<<26
++ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+
+ temp_rcr1 = __REG(CONFIG_CS1RCR1_ADDR);
+ __REG(CONFIG_CS1RCR1_ADDR) = 0x01000010;
@@ -1493,26 +1469,26 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+ __REG(CONFIG_CS1WCR1_ADDR) = 0x01000008;
+
+ /* change emi_clk_sel to ensure blck smaller than 50MHz */
-+ temp_clk = __REG(CCM_BASE_ADDR + CLKCTL_CBCDR);
-+ __REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk | EMI_CLK_SEL;
++ temp_clk = readl(&mxc_ccm->cbcdr); //__REG(CCM_BASE_ADDR + CLKCTL_CBCDR);
++ writel(temp_clk | EMI_CLK_SEL, &mxc_ccm->cbcdr); //__REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk | EMI_CLK_SEL;
+
+ /* FPGA PROG */
-+ imx_gpio_pin_set(CONFIG_SYS_FPGA_PRG, 1);
-+ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_PRG, 1);
++ gpio_set_value(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_PRG), 1);
++ gpio_direction_output(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_PRG), 1);
+
+ /* FPGA SUSPEND */
-+ imx_gpio_pin_set(CONFIG_SYS_FPGA_SUSPEND, 1);
-+ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_SUSPEND, 1);
++ gpio_set_value(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_SUSPEND), 1);
++ gpio_direction_output(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_SUSPEND), 1);
+
+ /* FPGA DONE */
-+ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_DONE, 0);
++ gpio_direction_input(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_DONE));
+
+ /* FPGA INIT# */
-+ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_INIT, 0);
++ gpio_direction_input(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_INIT));
+
+ /* FPGA PWR */
-+ imx_gpio_pin_set(CONFIG_SYS_FPGA_PWR, 1);
-+ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_PWR, 1);
++ gpio_set_value(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_PWR), 1);
++ gpio_direction_output(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_PWR), 1);
+
+ PRINTF("FPGA power enabled\n");
+
@@ -1527,7 +1503,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+{
+ PRINTF ("%s:%d: FPGA PROGRAM %s\n", __FUNCTION__, __LINE__,
+ assert?"high":"low");
-+ imx_gpio_pin_set(CONFIG_SYS_FPGA_PRG, !assert);
++ gpio_set_value(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_PRG), !assert);
+ return assert;
+}
+
@@ -1549,7 +1525,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+{
+ int value;
+ PRINTF ("%s:%d: INIT check... \n", __FUNCTION__, __LINE__);
-+ value = imx_gpio_pin_get(CONFIG_SYS_FPGA_INIT);
++ value = gpio_get_value(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_INIT));
+ PRINTF ("init value read %x\n",value);
+ if (value)
+ return 0;
@@ -1563,7 +1539,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+fpga_done_fn (int cookie)
+{
+ int value;
-+ value = imx_gpio_pin_get(CONFIG_SYS_FPGA_DONE);
++ value = gpio_get_value(IOMUX_TO_GPIO(CONFIG_SYS_FPGA_DONE));
+ PRINTF ("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
+ value?"high":"low");
+ return(value?FPGA_SUCCESS:FPGA_FAIL);
@@ -1630,9 +1606,10 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
+int
+fpga_post_fn (int cookie)
+{
++ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ PRINTF ("%s:%d: FPGA POST \n", __FUNCTION__, __LINE__);
+ /* restore emi_clk_sel */
-+ __REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk;
++ writel(temp_clk | EMI_CLK_SEL, &mxc_ccm->cbcdr); //__REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk;
+ udelay(10); /* wait a few us after emi_clk_sel change */
+ __REG(CONFIG_CS1RCR1_ADDR) = temp_rcr1;
+ __REG(CONFIG_CS1WCR1_ADDR) = temp_wcr1;
diff --git a/patches/u-boot/2011.12/403-apf51-wdog.patch b/patches/u-boot/2011.12/403-apf51-wdog.patch
new file mode 100644
index 0000000..840b7f8
--- /dev/null
+++ b/patches/u-boot/2011.12/403-apf51-wdog.patch
@@ -0,0 +1,20 @@
+Index: u-boot-2010.03/include/asm-arm/arch-mx51/imx-regs.h
+===================================================================
+--- u-boot-2010.03.orig/arch/arm/include/asm/arch-mx5/imx-regs.h 2011-01-05 18:10:42.000000000 +0100
++++ u-boot-2010.03/arch/arm/include/asm/arch-mx5/imx-regs.h 2011-01-05 18:11:20.000000000 +0100
+@@ -605,6 +605,15 @@ struct fuse_bank1_regs {
+ u32 fuse15_31[0x11];
+ };
+
++/* WDOG registers */
++struct wdog_regs {
++ u16 wcr;
++ u16 wsr;
++ u16 wrsr;
++ u16 wicr;
++ u16 wmcr;
++};
++
+ #endif /* __ASSEMBLER__*/
+
+ #endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
diff --git a/patches/u-boot/2011.12/405-remove_extra_printk.patch b/patches/u-boot/2011.12/405-remove_extra_printk.patch
new file mode 100644
index 0000000..960bce9
--- /dev/null
+++ b/patches/u-boot/2011.12/405-remove_extra_printk.patch
@@ -0,0 +1,25 @@
+U-Boot-2011-12: remove extra printk in
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- u-boot-2011.12/drivers/mtd/nand/nand_bbt.c 2011-12-23 20:25:35.000000000 +0100
++++ u-boot-2011.12/drivers/mtd/nand/nand_bbt.c 2012-01-12 19:01:14.890416390 +0100
+@@ -179,7 +179,7 @@ static int read_bbt(struct mtd_info *mtd
+ }
+ /* Leave it for now, if its matured we can move this
+ * message to MTD_DEBUG_LEVEL0 */
+- printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n",
++ debug(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n",
+ (loff_t)((offs << 2) + (act >> 1)) <<
+ this->bbt_erase_shift);
+ /* Factory marked bad or worn out ? */
+@@ -513,7 +513,7 @@ static int search_bbt(struct mtd_info *m
+ if (td->pages[i] == -1)
+ printk(KERN_WARNING "Bad block table not found for chip %d\n", i);
+ else
+- printk(KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i],
++ debug(KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i],
+ td->version[i]);
+ }
+ return 0;
+
diff --git a/patches/u-boot/2010.03/u-boot-2010.03-407-imx51-nand.patch b/patches/u-boot/2011.12/407-imx51-nand.patch
similarity index 99%
copy from patches/u-boot/2010.03/u-boot-2010.03-407-imx51-nand.patch
copy to patches/u-boot/2011.12/407-imx51-nand.patch
index b7a7c8b..06a9838 100644
--- a/patches/u-boot/2010.03/u-boot-2010.03-407-imx51-nand.patch
+++ b/patches/u-boot/2011.12/407-imx51-nand.patch
@@ -2,14 +2,14 @@ Index: u-boot-2010.03/drivers/mtd/nand/Makefile
===================================================================
--- u-boot-2010.03.orig/drivers/mtd/nand/Makefile 2011-01-05 18:05:11.000000000 +0100
+++ u-boot-2010.03/drivers/mtd/nand/Makefile 2011-01-05 18:11:26.000000000 +0100
-@@ -43,6 +43,7 @@
+@@ -54,6 +54,7 @@ COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwoo
COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
+COBJS-$(CONFIG_NAND_MXC_V2) += mx51_nand.o
+ COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
- COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
Index: u-boot-2010.03/drivers/mtd/nand/mx51_nand.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1000,10 +1000,10 @@ Index: u-boot-2010.03/drivers/mtd/nand/mx51_nand.c
+
+ return err;
+}
-Index: u-boot-2010.03/include/asm-arm/arch-mx51/mxc_nand.h
+Index: u-boot-2010.03/arch/arm/include/asm/arch-mx5/mxc_nand.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/include/asm-arm/arch-mx51/mxc_nand.h 2011-01-05 18:11:26.000000000 +0100
++++ u-boot-2010.03/arch/arm/include/asm/arch-mx5/mxc_nand.h 2011-01-05 18:11:26.000000000 +0100
@@ -0,0 +1,368 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
diff --git a/patches/u-boot/2010.03/u-boot-2010.03-409-apf51-nand-spl.patch b/patches/u-boot/2011.12/409-apf51-nand-spl.patch
similarity index 77%
copy from patches/u-boot/2010.03/u-boot-2010.03-409-apf51-nand-spl.patch
copy to patches/u-boot/2011.12/409-apf51-nand-spl.patch
index 401df9d..0468427 100644
--- a/patches/u-boot/2010.03/u-boot-2010.03-409-apf51-nand-spl.patch
+++ b/patches/u-boot/2011.12/409-apf51-nand-spl.patch
@@ -74,7 +74,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/flash_header.S
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
-+#include <asm/arch/asm-offsets.h>
++#include <generated/asm-offsets.h>
+
+#ifdef CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
@@ -271,7 +271,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/Makefile
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL
+
-+SOBJS = flash_header.o mxc_nand_load.o
++SOBJS = flash_header.o
+COBJS =
+
+SRCS := $(addprefix $(src),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -317,181 +317,6 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/Makefile
+sinclude $(obj).depend
+
+#########################################################################
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/mxc_nand_load.S
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf51/mxc_nand_load.S 2011-01-05 18:11:55.000000000 +0100
-@@ -0,0 +1,170 @@
-+/*
-+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <config.h>
-+//#include <asm/arch/mx51.h>
-+#include <asm/arch/imx-regs.h>
-+#include <asm/arch/asm-offsets.h>
-+
-+.macro do_wait_op_done
-+1: ldr r7, [r3, #0x2C]
-+ ands r7, r7, #0x80000000
-+ beq 1b
-+ mov r7, #0x0
-+ str r7, [r3, #0x2C]
-+.endm // do_wait_op_done
-+
-+//.section ".text.load", "x"
-+.globl mxc_nand_load
-+/*
-+ * R0: NFC BUF base address
-+ * R1: NFC BUF data end address
-+ * R2: RAM destination offset address
-+ * R3: NFC IP control register base
-+ * R4: NAND block address
-+ * R5: RAM destination end address
-+ * R6: NFC DATA register base
-+ * R7 - r14: 8 working buffer registers
-+ */
-+mxc_nand_load:
-+ ldr r0, =NFC_BASE_ADDR_AXI
-+ add r1, r0, #NFC_BUF_SIZE
-+
-+ /* For non-nand-boot, directly quit */
-+ cmp pc, r0
-+ blo _end //movlo pc, lr
-+ cmp pc, r1
-+ bhi _end //movhi pc, lr
-+
-+ mov r4, #NFC_BUF_SIZE
-+ /* Get NAND page size */
-+ ldr r3, =NFC_BASE_ADDR
-+ ldr r2, [r3, #0x24]
-+ and r2, r2, #0x3
-+ cmp r2, #1
-+ moveq r2, #0x800
-+ movlt r2, #0x200
-+ adrls r5, NFC_PAGE_MODE
-+ strls r2, [r5]
-+ /* Get actually pre-loading size*/
-+ subls r1, r1, #0x800
-+ subls r4, r4, #0x800
-+
-+ /* r1 ~ r3, r12, lr(r14) must not change in relocated operation */
-+ ldr r2, U_BOOT_NAND_START
-+1: ldmia r0!, {r5-r11, r13}
-+ stmia r2!, {r5-r11, r13}
-+ cmp r0, r1
-+ blo 1b
-+
-+ ldr r0, CONST_0X0FFF
-+ ldr r5, U_BOOT_NAND_START
-+ and lr, lr, r0
-+ add lr, lr, r5
-+ and r12, r12, r0
-+ add r12, r12, r5
-+ add r5, r5, #0x8
-+ and r0, pc, r0
-+ add pc, r5, r0
-+ nop
-+ nop
-+ nop
-+ nop
-+ nop
-+ adr r0, SAVE_REGS /* Save r12 & R14(lr) */
-+ str r12, [r0]
-+ str lr, [r0, #4]
-+Copy_Main:
-+ ldr r0, =NFC_BASE_ADDR_AXI
-+
-+ add r6, r0, #0x1E00
-+ ldr r5, =_end /* Try get right image size */
-+ add r5, r2, #0x00040000 /* Fixme to get actual image size */
-+
-+ mov r7, #0xFF000000
-+ add r7, r7, #0x00FF0000
-+ str r7, [r3, #0x4]
-+ str r7, [r3, #0x8]
-+ str r7, [r3, #0xC]
-+ str r7, [r3, #0x10]
-+ str r7, [r3, #0x14]
-+ str r7, [r3, #0x18]
-+ str r7, [r3, #0x1C]
-+ str r7, [r3, #0x20]
-+ mov r8, #0x7
-+ mov r7, #0x84
-+1: add r9, r7, r8, lsr #3
-+ str r9, [r3, #0x0]
-+ subs r8, r8, #0x01
-+ bne 1b
-+
-+ mov r7, #0
-+ str r7, [r3, #0x2C]
-+
-+ ldr r7, NFC_PAGE_MODE
-+Read_Page:
-+ /* start_nfc_addr_ops1(pg_no, pg_off) */
-+ cmp r7, #0x800
-+ movgt r7, r4, lsr #12 /* Get the page number for 4K page */
-+ moveq r7, r4, lsr #11 /* Get the page number for 2K page */
-+ mov r7, r7, lsl #16
-+ str r7, [r6, #0x04] /* Set the address */
-+
-+ /* writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG)*/
-+ mov r7, #0x3000
-+ str r7, [r6,#0x0]
-+
-+ /* writel(0x00000000, NAND_CONFIGURATION1_REG) */
-+ mov r7, #0x0
-+ str r7, [r6, #0x34]
-+
-+ /* start auto-read
-+ * writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
-+ */
-+ mov r7, #0x80
-+ str r7, [r6, #0x40]
-+
-+ do_wait_op_done
-+
-+Copy_Good_Blk:
-+1: ldmia r0!, {r7-r14}
-+ stmia r2!, {r7-r14}
-+ cmp r0, r1
-+ blo 1b
-+ cmp r2, r5
-+ bge Copy_Main_done
-+ ldr r7, NFC_PAGE_MODE
-+ add r4, r4, r7
-+ ldr r0, =NFC_BASE_ADDR_AXI
-+ b Read_Page
-+
-+Copy_Main_done:
-+ adr r0, SAVE_REGS
-+ ldr r12, [r0]
-+ ldr lr, [r0, #4]
-+ mov pc, lr
-+
-+U_BOOT_NAND_START: .word TEXT_BASE
-+CONST_0X0FFF: .word 0x0FFF
-+NFC_PAGE_MODE: .word 0x1000
-+SAVE_REGS: .word 0x0
-+ .word 0x0
Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/u-boot.lds
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
diff --git a/patches/u-boot/2010.03/u-boot-2010.03-410-imx-iim.patch b/patches/u-boot/2011.12/410-imx-iim.patch
similarity index 82%
copy from patches/u-boot/2010.03/u-boot-2010.03-410-imx-iim.patch
copy to patches/u-boot/2011.12/410-imx-iim.patch
index 6fbec8f..f134a61 100644
--- a/patches/u-boot/2010.03/u-boot-2010.03-410-imx-iim.patch
+++ b/patches/u-boot/2011.12/410-imx-iim.patch
@@ -1,7 +1,7 @@
-Index: u-boot-2010.03/common/cmd_iim.c
+Index: u-boot-2011.12/common/cmd_iim.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/common/cmd_iim.c 2011-01-05 18:11:58.000000000 +0100
++++ u-boot-2011.12/common/cmd_iim.c 2011-01-05 18:11:58.000000000 +0100
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
@@ -98,22 +98,22 @@ Index: u-boot-2010.03/common/cmd_iim.c
+ "iim blow fecmac <0x##:0x##:0x##:0x##:0x##:0x##>"
+ "- Blow FEC Mac address");
+
-Index: u-boot-2010.03/common/Makefile
+Index: u-boot-2011.12/common/Makefile
===================================================================
---- u-boot-2010.03.orig/common/Makefile 2011-01-05 18:05:11.000000000 +0100
-+++ u-boot-2010.03/common/Makefile 2011-01-05 18:11:58.000000000 +0100
-@@ -99,6 +99,7 @@
- ifdef CONFIG_FPGA
+--- u-boot-2011.12/common/Makefile 2011-12-23 20:25:35.000000...
[truncated message content] |
