[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2602-g55286b6

[Nicolas <th...@us...>]

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- Log -----------------------------------------------------------------
commit 55286b60475974a4432af12c0ff2d9605cc8529d
Author: Nicolas Colombain <nic...@ar...>
Date:   Fri Dec 2 09:49:18 2011 +0100

    fix ecspi chipselect on iMX5x

-----------------------------------------------------------------------

Summary of changes:
 .../442-armadeus-fix_mx5_ecspi_chipselect.patch    |   33 ++++++++++++++++++++
 1 files changed, 33 insertions(+), 0 deletions(-)
 create mode 100644 patches/linux/2.6.38/442-armadeus-fix_mx5_ecspi_chipselect.patch

diff --git a/patches/linux/2.6.38/442-armadeus-fix_mx5_ecspi_chipselect.patch b/patches/linux/2.6.38/442-armadeus-fix_mx5_ecspi_chipselect.patch
new file mode 100644
index 0000000..4bffc01
--- /dev/null
+++ b/patches/linux/2.6.38/442-armadeus-fix_mx5_ecspi_chipselect.patch
@@ -0,0 +1,33 @@
+Allows more than 4 chip select to be used on mx5 platform
+Chip select management under linux is done through gpios so use
+modulo to stay within the 4 controller chip select
+Signed-off-by: Nicolas Colombain <nic...@ar...>
+
+Index: linux-2.6.38.1/drivers/spi/spi_imx.c
+===================================================================
+--- linux-2.6.38.1.orig/drivers/spi/spi_imx.c	2011-11-30 15:54:07.000000000 +0100
++++ linux-2.6.38.1/drivers/spi/spi_imx.c	2011-12-01 11:53:08.000000000 +0100
+@@ -177,17 +177,17 @@ static unsigned int spi_imx_clkdiv_2(uns
+ #define SPI_IMX2_3_CTRL		0x08
+ #define SPI_IMX2_3_CTRL_ENABLE		(1 <<  0)
+ #define SPI_IMX2_3_CTRL_XCH		(1 <<  2)
+-#define SPI_IMX2_3_CTRL_MODE(cs)	(1 << ((cs) +  4))
++#define SPI_IMX2_3_CTRL_MODE(cs)	(1 << ((cs & 0x03) +  4))
+ #define SPI_IMX2_3_CTRL_POSTDIV_OFFSET	8
+ #define SPI_IMX2_3_CTRL_PREDIV_OFFSET	12
+-#define SPI_IMX2_3_CTRL_CS(cs)		((cs) << 18)
++#define SPI_IMX2_3_CTRL_CS(cs)		((cs & 0x03) << 18)
+ #define SPI_IMX2_3_CTRL_BL_OFFSET	20
+ 
+ #define SPI_IMX2_3_CONFIG	0x0c
+-#define SPI_IMX2_3_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
+-#define SPI_IMX2_3_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
+-#define SPI_IMX2_3_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
+-#define SPI_IMX2_3_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
++#define SPI_IMX2_3_CONFIG_SCLKPHA(cs)	(1 << ((cs & 0x03) +  0))
++#define SPI_IMX2_3_CONFIG_SCLKPOL(cs)	(1 << ((cs & 0x03) +  4))
++#define SPI_IMX2_3_CONFIG_SBBCTRL(cs)	(1 << ((cs & 0x03) +  8))
++#define SPI_IMX2_3_CONFIG_SSBPOL(cs)	(1 << ((cs & 0x03) + 12))
+ 
+ #define SPI_IMX2_3_INT		0x10
+ #define SPI_IMX2_3_INT_TEEN		(1 <<  0)


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