[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2601-gd1830de
Brought to you by:
sszy
Menu
▾
▴
[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2601-gd1830de
|
From: Julien B a. A. <ar...@us...> - 2011-12-02 08:37:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via d1830ded607fd652fd87aecd088b257f65320d9c (commit)
via 659bd82ac3f5673fa6d49d4c631e77e1185f2d46 (commit)
via 043fada8f4f0b2834f91b8cd3d0459af550e9bc0 (commit)
from 4aa3988714511f0fd381845e75a55039f358109e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d1830ded607fd652fd87aecd088b257f65320d9c
Merge: 659bd82 4aa3988
Author: Julien Boibessot <jul...@ar...>
Date: Fri Dec 2 09:35:43 2011 +0100
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit 659bd82ac3f5673fa6d49d4c631e77e1185f2d46
Author: Julien Boibessot <jul...@ar...>
Date: Fri Dec 2 09:28:53 2011 +0100
[BUILDROOT] Improve armadeus drivers-helpers installation
commit 043fada8f4f0b2834f91b8cd3d0459af550e9bc0
Author: Julien Boibessot <jul...@ar...>
Date: Fri Dec 2 09:27:17 2011 +0100
[LINUX] Add 3.0 Linux support to APF51 (experimental)
-----------------------------------------------------------------------
Summary of changes:
.../armadeus/drivers-helpers/drivers-helpers.mk | 3 +-
.../armadeus/apf51/apf51-linux-3.0.10.config | 1 +
.../device/armadeus/apf51/apf51-linux-3.0.config | 271 +
patches/linux/3.0.10 | 1 +
...2-20-pengutronix-3-Add_a_mfd_IPUv3_driver.patch | 3686 +++
...-pengutronix-4-fb-export_fb_mode_fb_table.patch | 48 +
...pengutronix-5-Add_iMX5_framebuffer_driver.patch | 989 +
...engutronix-6-iMX51-Add_IPU_device_support.patch | 113 +
...-7-iMX51-Allow_to_increase_max_zone_order.patch | 25 +
...rease_dma_consistent_size_for_IPU_support.patch | 19 +
...x-9-iMX51-babbage_add_framebuffer_support.patch | 128 +
...fb-prevent_fb_flags_redefinition_of_mx3fb.patch | 46 +
...50-armadeus-add_custom_drivers_to_kconfig.patch | 24 +
.../3.0/322-apf27-armadeus-add_mach_fpga_h.patch | 55 +
...363-armadeus-ADC-Adding_AS1531_adc_driver.patch | 359 +
.../linux/3.0/400-armadeus-add_apf51_module.patch | 583 +
.../linux/3.0/401-armadeus-fix_clock_tree.patch | 49 +
.../402-armadeus-add_nand_device.to_check | 0
.../linux/3.0/403-armadeus-set-uart2-debug.patch | 17 +
.../linux/3.0/404-armadeus-fix_nand_ecc_oob.patch | 81 +
.../3.0/408-armadeus-add_apf51-dev_baseboard.patch | 557 +
.../408b-armadeus-add_apf51-proto_baseboard.patch | 240 +
...rmadeus-gpio_select_dr_register_on_output.patch | 57 +
.../417-armadeus-input-wm831x-driver_hacks.patch | 24 +
...deus-mx5fb-add_ipu_clock_polarity_support.patch | 25 +
...0-armadeus-esdhc-add_gpio_SD_detection.tomerge} | 0
...soc-imx-add_apf51dev_wm8960_audio_support.patch | 204 +
...3-armadeus-adding_mcp4912_dac_chip_driver.patch | 395 +
...eus-audmuxv2-makes_debugfs_interface_work.patch | 75 +
...write_all_CANCTRL_bits_when_changing_mode.patch | 28 +
...d_license_and_author_infos_to_imx-pcm-fiq.patch | 15 +
...rmadeus-mx2-iomux-correct_gpio_port_names.patch | 17 +
...possibility_to_deactivate_SDIO_interrupt.tofix} | 0
.../428-armadeus-asoc-add_debug_to_wm8960.patch | 127 +
...deus-asoc-wm8960-change_channels_min_to_2.patch | 25 +
...ot_link_otg_phy_clock_directly_to_osc_ref.patch | 17 +
...32-armadeus-mcp2525-fix_spi_module_errata.patch | 43 +
...ct_some_mx5_regiter_settings_and_comments.patch | 23 +
.../438-freescale-support-low-power-suspend.patch | 105 +
.../3.0/440-armadeus-add-hms-anybus-driver.patch | 1279 +
..._star_completion_for_source_in_menuconfig.patch | 80 +
...NGR00126692-3-1-add_drivers_mxc_directory.patch | 40 +
...00126692-3-add_hw-events_vpu_srtc_drivers.patch | 2264 ++
...escale-0034-ENGR00126692-3-add_iim_driver.patch | 523 +
...26692-3-add_mx23_mx25_mx28_security_stuff.patch | 4163 +++
...0-add_scc2_and_sahara_drivers_without_rng.patch |31819 ++++++++++++++++++++
target/linux/modules/pwm/pwm.c | 1 +
47 files changed, 48643 insertions(+), 1 deletions(-)
create mode 120000 buildroot/target/device/armadeus/apf51/apf51-linux-3.0.10.config
create mode 100644 buildroot/target/device/armadeus/apf51/apf51-linux-3.0.config
create mode 120000 patches/linux/3.0.10
create mode 100644 patches/linux/3.0/001-2010-12-20-pengutronix-3-Add_a_mfd_IPUv3_driver.patch
create mode 100644 patches/linux/3.0/001-2010-12-20-pengutronix-4-fb-export_fb_mode_fb_table.patch
create mode 100644 patches/linux/3.0/001-2010-12-20-pengutronix-5-Add_iMX5_framebuffer_driver.patch
create mode 100644 patches/linux/3.0/001-2010-12-20-pengutronix-6-iMX51-Add_IPU_device_support.patch
create mode 100644 patches/linux/3.0/001-2010-12-20-pengutronix-7-iMX51-Allow_to_increase_max_zone_order.patch
create mode 100644 patches/linux/3.0/001-2010-12-20-pengutronix-8-iMX51-increase_dma_consistent_size_for_IPU_support.patch
create mode 100644 patches/linux/3.0/001-2010-12-20-pengutronix-9-iMX51-babbage_add_framebuffer_support.patch
create mode 100644 patches/linux/3.0/001-armadeus-mx51fb-prevent_fb_flags_redefinition_of_mx3fb.patch
create mode 100644 patches/linux/3.0/050-armadeus-add_custom_drivers_to_kconfig.patch
create mode 100644 patches/linux/3.0/322-apf27-armadeus-add_mach_fpga_h.patch
create mode 100644 patches/linux/3.0/363-armadeus-ADC-Adding_AS1531_adc_driver.patch
create mode 100644 patches/linux/3.0/400-armadeus-add_apf51_module.patch
create mode 100644 patches/linux/3.0/401-armadeus-fix_clock_tree.patch
copy patches/linux/{2.6.38 => 3.0}/402-armadeus-add_nand_device.to_check (100%)
create mode 100644 patches/linux/3.0/403-armadeus-set-uart2-debug.patch
create mode 100644 patches/linux/3.0/404-armadeus-fix_nand_ecc_oob.patch
create mode 100644 patches/linux/3.0/408-armadeus-add_apf51-dev_baseboard.patch
create mode 100644 patches/linux/3.0/408b-armadeus-add_apf51-proto_baseboard.patch
create mode 100644 patches/linux/3.0/409-armadeus-gpio_select_dr_register_on_output.patch
create mode 100644 patches/linux/3.0/417-armadeus-input-wm831x-driver_hacks.patch
create mode 100644 patches/linux/3.0/419-armadeus-mx5fb-add_ipu_clock_polarity_support.patch
copy patches/linux/{2.6.38/420-armadeus-esdhc-add_gpio_SD_detection.patch => 3.0/420-armadeus-esdhc-add_gpio_SD_detection.tomerge} (100%)
create mode 100644 patches/linux/3.0/421-armadeus-asoc-imx-add_apf51dev_wm8960_audio_support.patch
create mode 100644 patches/linux/3.0/423-armadeus-adding_mcp4912_dac_chip_driver.patch
create mode 100644 patches/linux/3.0/424-armadeus-audmuxv2-makes_debugfs_interface_work.patch
create mode 100644 patches/linux/3.0/425-armadeus-mcp2515-dont_overwrite_all_CANCTRL_bits_when_changing_mode.patch
create mode 100644 patches/linux/3.0/425-armadeus-snd-soc-imx-add_license_and_author_infos_to_imx-pcm-fiq.patch
create mode 100644 patches/linux/3.0/426-armadeus-mx2-iomux-correct_gpio_port_names.patch
copy patches/linux/{2.6.38/427-armadeus-esdhc-imx-add_possibility_to_deactivate_SDIO_interrupt.patch => 3.0/427-armadeus-esdhc-imx-add_possibility_to_deactivate_SDIO_interrupt.tofix} (100%)
create mode 100644 patches/linux/3.0/428-armadeus-asoc-add_debug_to_wm8960.patch
create mode 100644 patches/linux/3.0/430-armadeus-asoc-wm8960-change_channels_min_to_2.patch
create mode 100644 patches/linux/3.0/431-armadeus-clock-mx51-do_not_link_otg_phy_clock_directly_to_osc_ref.patch
create mode 100644 patches/linux/3.0/432-armadeus-mcp2525-fix_spi_module_errata.patch
create mode 100644 patches/linux/3.0/436-armadeus-plat-mxc-ehci-correct_some_mx5_regiter_settings_and_comments.patch
create mode 100644 patches/linux/3.0/438-freescale-support-low-power-suspend.patch
create mode 100644 patches/linux/3.0/440-armadeus-add-hms-anybus-driver.patch
create mode 100644 patches/linux/3.0/441-armadeus-adding_star_completion_for_source_in_menuconfig.patch
create mode 100644 patches/linux/3.0/442-freescale-0034-ENGR00126692-3-1-add_drivers_mxc_directory.patch
create mode 100644 patches/linux/3.0/442-freescale-0034-ENGR00126692-3-add_hw-events_vpu_srtc_drivers.patch
create mode 100644 patches/linux/3.0/442-freescale-0034-ENGR00126692-3-add_iim_driver.patch
create mode 100644 patches/linux/3.0/442-freescale-0034-ENGR00126692-3-add_mx23_mx25_mx28_security_stuff.patch
create mode 100644 patches/linux/3.0/442-freescale-0197-ENGR00131650-add_scc2_and_sahara_drivers_without_rng.patch
diff --git a/buildroot/package/armadeus/drivers-helpers/drivers-helpers.mk b/buildroot/package/armadeus/drivers-helpers/drivers-helpers.mk
index 39b5777..c290be7 100644
--- a/buildroot/package/armadeus/drivers-helpers/drivers-helpers.mk
+++ b/buildroot/package/armadeus/drivers-helpers/drivers-helpers.mk
@@ -10,6 +10,7 @@ ARMADEUS-DRIVERS-HELPERS_TARGET_DIR:=$(TARGET_DIR)/usr/bin
# loadgpio.sh often needs to be overwritten by users
$(ARMADEUS-DRIVERS-HELPERS_TARGET_DIR)/loadgpio.sh:
+ mkdir -p $(ARMADEUS-DRIVERS-HELPERS_TARGET_DIR)
cp -f $(ARMADEUS-DRIVERS_SOURCE_DIR)/gpio/loadgpio.sh $@
ARMADEUS-DRIVERS_TARGETS+=$(ARMADEUS-DRIVERS-HELPERS_TARGET_DIR)/loadgpio.sh
@@ -27,7 +28,7 @@ $(ARMADEUS-DRIVERS-HELPERS_TARGET_DIR)/load_fpga: $(ARMADEUS-DRIVERS_SOURCE_DIR)
ARMADEUS-DRIVERS_TARGETS+=$(ARMADEUS-DRIVERS-HELPERS_TARGET_DIR)/load_fpga
-armadeus-drivers-helpers: $(ARMADEUS-DRIVERS_TARGETS)
+armadeus-drivers-helpers: linux $(ARMADEUS-DRIVERS_TARGETS)
armadeus-drivers-helpers-clean:
rm -f $(ARMADEUS-DRIVERS_TARGETS)
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.0.10.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.0.10.config
new file mode 120000
index 0000000..0e03a6c
--- /dev/null
+++ b/buildroot/target/device/armadeus/apf51/apf51-linux-3.0.10.config
@@ -0,0 +1 @@
+apf51-linux-3.0.config
\ No newline at end of file
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.0.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.0.config
new file mode 100644
index 0000000..861fdc1
--- /dev/null
+++ b/buildroot/target/device/armadeus/apf51/apf51-linux-3.0.config
@@ -0,0 +1,271 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_MX51=y
+CONFIG_MACH_APF51=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_IMX=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_APM_EMULATION=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_MCP251X=m
+CONFIG_BT=m
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_CFG80211=m
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RC_PID=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_FW_LOADER=m
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_MXC=y
+CONFIG_MTD_UBI=y
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_SMSC_PHY=y
+CONFIG_NET_ETHERNET=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_RTL8187=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_RT2X00=m
+CONFIG_RT73USB=m
+CONFIG_ZD1211RW=m
+CONFIG_PPP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_KEYBOARD_IMX=m
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_WM831X=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=m
+CONFIG_INPUT_WM831X_ON=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=m
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_WM831X=m
+CONFIG_POWER_SUPPLY=m
+CONFIG_WM831X_BACKUP=m
+CONFIG_WM831X_POWER=m
+CONFIG_HWMON=m
+CONFIG_SENSORS_AS1531=m
+CONFIG_SENSORS_WM831X=m
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WM831X_WATCHDOG=m
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_WM831X_I2C=y
+CONFIG_MFD_IMX_IPU_V3=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_VIDEO_DEV=m
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+CONFIG_VIDEO_VIVI=m
+CONFIG_USB_VIDEO_CLASS=m
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_FB=y
+CONFIG_FB_MX5=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=m
+# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_IMX_SOC=m
+CONFIG_SND_SOC_APF51_DEV_WM8960=m
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_ACM=y
+CONFIG_USB_PRINTER=y
+CONFIG_USB_WDM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_ETH=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_G_HID=m
+CONFIG_ARMADEUS_DRIVERS=y
+CONFIG_ARMADEUS_FPGA_DRIVERS=y
+CONFIG_ARMADEUS_FPGA_LOADER_DRIVER=m
+# CONFIG_ARMADEUS_FPGA_VIRTUAL_COMPONENTS is not set
+CONFIG_ARMADEUS_PWM_DRIVER=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SPI=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_WM831X_STATUS=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_MXC=y
+CONFIG_RTC_DRV_WM831X=y
+CONFIG_STAGING=y
+CONFIG_IIO=m
+CONFIG_MCP49x2=m
+# CONFIG_MXC_HWEVENT is not set
+# CONFIG_MXC_VPU is not set
+# CONFIG_MXC_VPU_IRAM is not set
+CONFIG_MXC_SECURITY_SCC2=m
+CONFIG_MXC_SAHARA=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_CMODE_NONE=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_FS=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/patches/linux/3.0.10 b/patches/linux/3.0.10
new file mode 120000
index 0000000..f398a20
--- /dev/null
+++ b/patches/linux/3.0.10
@@ -0,0 +1 @@
+3.0
\ No newline at end of file
diff --git a/patches/linux/3.0/001-2010-12-20-pengutronix-3-Add_a_mfd_IPUv3_driver.patch b/patches/linux/3.0/001-2010-12-20-pengutronix-3-Add_a_mfd_IPUv3_driver.patch
new file mode 100644
index 0000000..f274044
--- /dev/null
+++ b/patches/linux/3.0/001-2010-12-20-pengutronix-3-Add_a_mfd_IPUv3_driver.patch
@@ -0,0 +1,3686 @@
+The IPU is the Image Processing Unit found on i.MX50/51/53 SoCs. It
+features several units for image processing, this patch adds support
+for the units needed for Framebuffer support, namely:
+
+- Display Controller (dc)
+- Display Interface (di)
+- Display Multi Fifo Controller (dmfc)
+- Display Processor (dp)
+- Image DMA Controller (idmac)
+
+This patch is based on the Freescale driver, but follows a different
+approach. The Freescale code implements logical idmac channels and
+the handling of the subunits is hidden in common idmac code pathes
+in big switch/case statements. This patch instead just provides code
+and resource management for the different subunits. The user, in this
+case the framebuffer driver, decides how the different units play
+together.
+
+The IPU has other units missing in this patch:
+
+- CMOS Sensor Interface (csi)
+- Video Deinterlacer (vdi)
+- Sensor Multi FIFO Controler (smfc)
+- Image Converter (ic)
+- Image Rotator (irt)
+
+So expect more files to come in this directory.
+
+Signed-off-by: Sascha Hauer <s....@pe...>
+---
+ arch/arm/plat-mxc/include/mach/ipu-v3.h | 49 +++
+ drivers/mfd/Kconfig | 7 +
+ drivers/mfd/Makefile | 1 +
+ drivers/mfd/imx-ipu-v3/Makefile | 3 +
+ drivers/mfd/imx-ipu-v3/ipu-common.c | 708 +++++++++++++++++++++++++++++++
+ drivers/mfd/imx-ipu-v3/ipu-cpmem.c | 612 ++++++++++++++++++++++++++
+ drivers/mfd/imx-ipu-v3/ipu-dc.c | 364 ++++++++++++++++
+ drivers/mfd/imx-ipu-v3/ipu-di.c | 550 ++++++++++++++++++++++++
+ drivers/mfd/imx-ipu-v3/ipu-dmfc.c | 355 ++++++++++++++++
+ drivers/mfd/imx-ipu-v3/ipu-dp.c | 476 +++++++++++++++++++++
+ drivers/mfd/imx-ipu-v3/ipu-prv.h | 216 ++++++++++
+ include/linux/mfd/imx-ipu-v3.h | 219 ++++++++++
+ 12 files changed, 3560 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/plat-mxc/include/mach/ipu-v3.h
+ create mode 100644 drivers/mfd/imx-ipu-v3/Makefile
+ create mode 100644 drivers/mfd/imx-ipu-v3/ipu-common.c
+ create mode 100644 drivers/mfd/imx-ipu-v3/ipu-cpmem.c
+ create mode 100644 drivers/mfd/imx-ipu-v3/ipu-dc.c
+ create mode 100644 drivers/mfd/imx-ipu-v3/ipu-di.c
+ create mode 100644 drivers/mfd/imx-ipu-v3/ipu-dmfc.c
+ create mode 100644 drivers/mfd/imx-ipu-v3/ipu-dp.c
+ create mode 100644 drivers/mfd/imx-ipu-v3/ipu-prv.h
+ create mode 100644 include/linux/mfd/imx-ipu-v3.h
+
+Index: linux-3.0.10/arch/arm/plat-mxc/include/mach/ipu-v3.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.10/arch/arm/plat-mxc/include/mach/ipu-v3.h 2011-11-30 17:07:12.000000000 +0100
+@@ -0,0 +1,49 @@
++/*
++ * Copyright (c) 2010 Sascha Hauer <s....@pe...>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#ifndef __MACH_IPU_V3_H_
++#define __MACH_IPU_V3_H_
++
++/* IPU specific extensions to struct fb_videomode flag field */
++#define FB_SYNC_OE_LOW_ACT (1 << 8)
++#define FB_SYNC_CLK_LAT_FALL (1 << 9)
++#define FB_SYNC_DATA_INVERT (1 << 10)
++#define FB_SYNC_CLK_IDLE_EN (1 << 11)
++#define FB_SYNC_SHARP_MODE (1 << 12)
++#define FB_SYNC_SWAP_RGB (1 << 13)
++
++struct ipuv3_fb_platform_data {
++ const struct fb_videomode *modes;
++ int num_modes;
++ char *mode_str;
++ u32 interface_pix_fmt;
++
++#define IMX_IPU_FB_USE_MODEDB (1 << 0)
++#define IMX_IPU_FB_USE_OVERLAY (1 << 1)
++ unsigned long flags;
++
++ int ipu_channel_bg;
++ int ipu_channel_fg;
++ int dc_channel;
++ int dp_channel;
++ int display;
++};
++
++struct imx_ipuv3_platform_data {
++ int rev;
++ struct ipuv3_fb_platform_data *fb_head0_platform_data;
++ struct ipuv3_fb_platform_data *fb_head1_platform_data;
++};
++
++#endif /* __MACH_IPU_V3_H_ */
+Index: linux-3.0.10/drivers/mfd/Kconfig
+===================================================================
+--- linux-3.0.10.orig/drivers/mfd/Kconfig 2011-11-21 23:37:44.000000000 +0100
++++ linux-3.0.10/drivers/mfd/Kconfig 2011-11-30 17:07:12.000000000 +0100
+@@ -731,6 +731,13 @@
+ config TPS65911_COMPARATOR
+ tristate
+
++config MFD_IMX_IPU_V3
++ tristate "Support the Image Processing Unit (IPU) found on the i.MX51"
++ depends on ARCH_MX51
++ select MFD_CORE
++ help
++ Say yes here to support the IPU on i.MX51.
++
+ endif # MFD_SUPPORT
+
+ menu "Multimedia Capabilities Port drivers"
+Index: linux-3.0.10/drivers/mfd/Makefile
+===================================================================
+--- linux-3.0.10.orig/drivers/mfd/Makefile 2011-11-21 23:37:44.000000000 +0100
++++ linux-3.0.10/drivers/mfd/Makefile 2011-11-30 17:07:12.000000000 +0100
+@@ -90,6 +90,7 @@
+ obj-$(CONFIG_MFD_VX855) += vx855.o
+ obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
+ obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
++obj-$(CONFIG_MFD_IMX_IPU_V3) += imx-ipu-v3/
+ obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o
+ obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
+ obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
+Index: linux-3.0.10/drivers/mfd/imx-ipu-v3/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.10/drivers/mfd/imx-ipu-v3/Makefile 2011-11-30 17:07:12.000000000 +0100
+@@ -0,0 +1,3 @@
++obj-$(CONFIG_MFD_IMX_IPU_V3) += imx-ipu-v3.o
++
++imx-ipu-v3-objs := ipu-common.o ipu-dc.o ipu-di.o ipu-dp.o ipu-dmfc.o ipu-cpmem.o
+Index: linux-3.0.10/drivers/mfd/imx-ipu-v3/ipu-common.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.10/drivers/mfd/imx-ipu-v3/ipu-common.c 2011-11-30 17:07:12.000000000 +0100
+@@ -0,0 +1,708 @@
++/*
++ * Copyright (c) 2010 Sascha Hauer <s....@pe...>
++ * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/spinlock.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/mfd/imx-ipu-v3.h>
++#include <linux/clk.h>
++#include <linux/list.h>
++#include <mach/common.h>
++#include <linux/mfd/core.h>
++#include <mach/ipu-v3.h>
++
++#include "ipu-prv.h"
++
++static struct clk *ipu_clk;
++static struct device *ipu_dev;
++
++static DEFINE_SPINLOCK(ipu_lock);
++static DEFINE_MUTEX(ipu_channel_lock);
++void __iomem *ipu_cm_reg;
++void __iomem *ipu_idmac_reg;
++
++static int ipu_use_count;
++
++static struct ipu_channel channels[64];
++
++struct ipu_channel *ipu_idmac_get(unsigned num)
++{
++ struct ipu_channel *channel;
++
++ dev_dbg(ipu_dev, "%s %d\n", __func__, num);
++
++ if (num > 63)
++ return ERR_PTR(-ENODEV);
++
++ mutex_lock(&ipu_channel_lock);
++
++ channel = &channels[num];
++
++ if (channel->busy) {
++ channel = ERR_PTR(-EBUSY);
++ goto out;
++ }
++
++ channel->busy = 1;
++ channel->num = num;
++
++out:
++ mutex_unlock(&ipu_channel_lock);
++
++ return channel;
++}
++EXPORT_SYMBOL(ipu_idmac_get);
++
++void ipu_idmac_put(struct ipu_channel *channel)
++{
++ dev_dbg(ipu_dev, "%s %d\n", __func__, channel->num);
++
++ mutex_lock(&ipu_channel_lock);
++
++ channel->busy = 0;
++
++ mutex_unlock(&ipu_channel_lock);
++}
++EXPORT_SYMBOL(ipu_idmac_put);
++
++void ipu_idmac_set_double_buffer(struct ipu_channel *channel, bool doublebuffer)
++{
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&ipu_lock, flags);
++
++ reg = ipu_cm_read(IPU_CHA_DB_MODE_SEL(channel->num));
++ if (doublebuffer)
++ reg |= idma_mask(channel->num);
++ else
++ reg &= ~idma_mask(channel->num);
++ ipu_cm_write(reg, IPU_CHA_DB_MODE_SEL(channel->num));
++
++ spin_unlock_irqrestore(&ipu_lock, flags);
++}
++EXPORT_SYMBOL(ipu_idmac_set_double_buffer);
++
++int ipu_module_enable(u32 mask)
++{
++ unsigned long lock_flags;
++ u32 ipu_conf;
++
++ spin_lock_irqsave(&ipu_lock, lock_flags);
++
++ ipu_conf = ipu_cm_read(IPU_CONF);
++ ipu_conf |= mask;
++ ipu_cm_write(ipu_conf, IPU_CONF);
++
++ spin_unlock_irqrestore(&ipu_lock, lock_flags);
++
++ return 0;
++}
++
++int ipu_module_disable(u32 mask)
++{
++ unsigned long lock_flags;
++ u32 ipu_conf;
++
++ spin_lock_irqsave(&ipu_lock, lock_flags);
++
++ ipu_conf = ipu_cm_read(IPU_CONF);
++ ipu_conf &= ~mask;
++ ipu_cm_write(ipu_conf, IPU_CONF);
++
++ spin_unlock_irqrestore(&ipu_lock, lock_flags);
++
++ return 0;
++}
++
++void ipu_idmac_select_buffer(struct ipu_channel *channel, u32 buf_num)
++{
++ unsigned int chno = channel->num;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ipu_lock, flags);
++
++ /* Mark buffer as ready. */
++ if (buf_num == 0)
++ ipu_cm_write(idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
++ else
++ ipu_cm_write(idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
++
++ spin_unlock_irqrestore(&ipu_lock, flags);
++}
++EXPORT_SYMBOL(ipu_idmac_select_buffer);
++
++int ipu_idmac_enable_channel(struct ipu_channel *channel)
++{
++ u32 val;
++ unsigned long flags;
++
++ ipu_get();
++
++ spin_lock_irqsave(&ipu_lock, flags);
++
++ val = ipu_idmac_read(IDMAC_CHA_EN(channel->num));
++ val |= idma_mask(channel->num);
++ ipu_idmac_write(val, IDMAC_CHA_EN(channel->num));
++
++ spin_unlock_irqrestore(&ipu_lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_idmac_enable_channel);
++
++int ipu_idmac_disable_channel(struct ipu_channel *channel)
++{
++ u32 val;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ipu_lock, flags);
++
++ /* Disable DMA channel(s) */
++ val = ipu_idmac_read(IDMAC_CHA_EN(channel->num));
++ val &= ~idma_mask(channel->num);
++ ipu_idmac_write(val, IDMAC_CHA_EN(channel->num));
++
++ /* Set channel buffers NOT to be ready */
++ ipu_cm_write(0xf0000000, IPU_GPR); /* write one to clear */
++
++ if (ipu_idma_is_set(IPU_CHA_BUF0_RDY, channel->num)) {
++ ipu_cm_write(idma_mask(channel->num),
++ IPU_CHA_BUF0_RDY(channel->num));
++ }
++ if (ipu_idma_is_set(IPU_CHA_BUF1_RDY, channel->num)) {
++ ipu_cm_write(idma_mask(channel->num),
++ IPU_CHA_BUF1_RDY(channel->num));
++ }
++
++ ipu_cm_write(0x0, IPU_GPR); /* write one to set */
++
++ /* Reset the double buffer */
++ val = ipu_cm_read(IPU_CHA_DB_MODE_SEL(channel->num));
++ val &= ~idma_mask(channel->num);
++ ipu_cm_write(val, IPU_CHA_DB_MODE_SEL(channel->num));
++
++ spin_unlock_irqrestore(&ipu_lock, flags);
++
++ ipu_put();
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_idmac_disable_channel);
++
++static LIST_HEAD(ipu_irq_handlers);
++
++static void ipu_irq_update_irq_mask(void)
++{
++ struct ipu_irq_handler *handler;
++ int i;
++
++ DECLARE_IPU_IRQ_BITMAP(irqs);
++
++ bitmap_zero(irqs, IPU_IRQ_COUNT);
++
++ list_for_each_entry(handler, &ipu_irq_handlers, list)
++ bitmap_or(irqs, irqs, handler->ipu_irqs, IPU_IRQ_COUNT);
++
++ for (i = 0; i < BITS_TO_LONGS(IPU_IRQ_COUNT); i++)
++ ipu_cm_write(irqs[i], IPU_INT_CTRL(i + 1));
++}
++
++int ipu_irq_add_handler(struct ipu_irq_handler *ipuirq)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&ipu_lock, flags);
++
++ list_add_tail(&ipuirq->list, &ipu_irq_handlers);
++ ipu_irq_update_irq_mask();
++
++ spin_unlock_irqrestore(&ipu_lock, flags);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_irq_add_handler);
++
++void ipu_irq_remove_handler(struct ipu_irq_handler *handler)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&ipu_lock, flags);
++
++ list_del(&handler->list);
++ ipu_irq_update_irq_mask();
++
++ spin_unlock_irqrestore(&ipu_lock, flags);
++}
++EXPORT_SYMBOL(ipu_irq_remove_handler);
++
++int ipu_irq_update_handler(struct ipu_irq_handler *handler,
++ unsigned long *bitmap)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&ipu_lock, flags);
++
++ bitmap_copy(handler->ipu_irqs, bitmap, IPU_IRQ_COUNT);
++ ipu_irq_update_irq_mask();
++
++ spin_unlock_irqrestore(&ipu_lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_irq_update_handler);
++
++static void ipu_completion_handler(unsigned long *bitmask, void *context)
++{
++ struct completion *completion = context;
++
++ complete(completion);
++}
++
++int ipu_wait_for_interrupt(int interrupt, int timeout_ms)
++{
++ struct ipu_irq_handler handler;
++ DECLARE_COMPLETION_ONSTACK(completion);
++ int ret;
++
++ bitmap_zero(handler.ipu_irqs, IPU_IRQ_COUNT);
++ bitmap_set(handler.ipu_irqs, interrupt, 1);
++
++ ipu_cm_write(1 << (interrupt % 32), IPU_INT_STAT(interrupt / 32 + 1));
++
++ handler.handler = ipu_completion_handler;
++ handler.context = &completion;
++ ipu_irq_add_handler(&handler);
++
++ ret = wait_for_completion_timeout(&completion,
++ msecs_to_jiffies(timeout_ms));
++
++ ipu_irq_remove_handler(&handler);
++
++ if (ret > 0)
++ ret = 0;
++ else
++ ret = -ETIMEDOUT;
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_wait_for_interrupt);
++
++static irqreturn_t ipu_irq_handler(int irq, void *desc)
++{
++ DECLARE_IPU_IRQ_BITMAP(status);
++ struct ipu_irq_handler *handler;
++ int i;
++
++ for (i = 0; i < BITS_TO_LONGS(IPU_IRQ_COUNT); i++) {
++ status[i] = ipu_cm_read(IPU_INT_STAT(i + 1));
++ ipu_cm_write(status[i], IPU_INT_STAT(i + 1));
++ }
++
++ list_for_each_entry(handler, &ipu_irq_handlers, list) {
++ DECLARE_IPU_IRQ_BITMAP(tmp);
++ if (bitmap_and(tmp, status, handler->ipu_irqs, IPU_IRQ_COUNT))
++ handler->handler(tmp, handler->context);
++ }
++
++ return IRQ_HANDLED;
++}
++
++ipu_color_space_t format_to_colorspace(u32 fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGB666:
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ case IPU_PIX_FMT_LVDS666:
++ case IPU_PIX_FMT_LVDS888:
++ return RGB;
++
++ default:
++ return YCbCr;
++ }
++}
++
++static int ipu_reset(void)
++{
++ int timeout = 10000;
++ u32 val;
++
++ /* hard reset the IPU */
++ val = readl(MX51_IO_ADDRESS(MX51_SRC_BASE_ADDR));
++ val |= 1 << 3;
++ writel(val, MX51_IO_ADDRESS(MX51_SRC_BASE_ADDR));
++
++ ipu_cm_write(0x807FFFFF, IPU_MEM_RST);
++
++ while (ipu_cm_read(IPU_MEM_RST) & 0x80000000) {
++ if (!timeout--)
++ return -ETIME;
++ udelay(100);
++ }
++
++ return 0;
++}
++
++/*
++ * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
++ * the Freescale marketing division. However this did not remove the
++ * hardware from the chip which still needs to be configured...
++ */
++static int __devinit ipu_mipi_setup(void)
++{
++ struct clk *hsc_clk;
++ void __iomem *hsc_addr;
++ int ret = 0;
++
++ hsc_addr = ioremap(MX51_MIPI_HSC_BASE_ADDR, PAGE_SIZE);
++ if (!hsc_addr)
++ return -ENOMEM;
++
++ hsc_clk = clk_get_sys(NULL, "mipi_hsp");
++ if (IS_ERR(hsc_clk)) {
++ ret = PTR_ERR(hsc_clk);
++ goto unmap;
++ }
++ clk_enable(hsc_clk);
++
++ /* setup MIPI module to legacy mode */
++ __raw_writel(0xF00, hsc_addr);
++
++ /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
++ __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
++ hsc_addr + 0x800);
++
++ clk_disable(hsc_clk);
++ clk_put(hsc_clk);
++unmap:
++ iounmap(hsc_addr);
++
++ return ret;
++}
++
++static int ipu_submodules_init(struct platform_device *pdev,
++ unsigned long ipu_base, struct clk *ipu_clk)
++{
++ char *unit;
++ int ret;
++
++ ret = ipu_di_init(pdev, 0, ipu_base + IPU_DI0_REG_BASE,
++ IPU_CONF_DI0_EN, ipu_clk);
++ if (ret) {
++ unit = "di0";
++ goto err_di_0;
++ }
++
++ ret = ipu_di_init(pdev, 1, ipu_base + IPU_DI1_REG_BASE,
++ IPU_CONF_DI1_EN, ipu_clk);
++ if (ret) {
++ unit = "di1";
++ goto err_di_1;
++ }
++
++ ret = ipu_dc_init(pdev, ipu_base + IPU_DC_REG_BASE,
++ ipu_base + IPU_DC_TMPL_REG_BASE);
++ if (ret) {
++ unit = "dc_template";
++ goto err_dc;
++ }
++
++ ret = ipu_dmfc_init(pdev, ipu_base + IPU_DMFC_REG_BASE, ipu_clk);
++ if (ret) {
++ unit = "dmfc";
++ goto err_dmfc;
++ }
++
++ ret = ipu_dp_init(pdev, ipu_base + IPU_SRM_REG_BASE);
++ if (ret) {
++ unit = "dp";
++ goto err_dp;
++ }
++
++ ret = ipu_cpmem_init(pdev, ipu_base + IPU_CPMEM_REG_BASE);
++ if (ret) {
++ unit = "cpmem";
++ goto err_cpmem;
++ }
++
++ return 0;
++
++err_cpmem:
++ ipu_dp_exit(pdev);
++err_dp:
++ ipu_dmfc_exit(pdev);
++err_dmfc:
++ ipu_dc_exit(pdev);
++err_dc:
++ ipu_di_exit(pdev, 1);
++err_di_1:
++ ipu_di_exit(pdev, 0);
++err_di_0:
++ dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
++ return ret;
++}
++
++void ipu_get(void)
++{
++ mutex_lock(&ipu_channel_lock);
++
++ ipu_use_count++;
++
++ if (ipu_use_count == 1)
++ clk_enable(ipu_clk);
++
++ mutex_unlock(&ipu_channel_lock);
++}
++
++void ipu_put(void)
++{
++ mutex_lock(&ipu_channel_lock);
++
++ ipu_use_count--;
++
++ if (ipu_use_count == 0)
++ clk_disable(ipu_clk);
++
++ if (ipu_use_count < 0) {
++ dev_err(ipu_dev, "ipu use count < 0\n");
++ ipu_use_count = 0;
++ }
++
++ mutex_unlock(&ipu_channel_lock);
++}
++
++static void ipu_submodules_exit(struct platform_device *pdev,
++ unsigned long ipu_base)
++{
++ ipu_cpmem_exit(pdev);
++ ipu_dp_exit(pdev);
++ ipu_dmfc_exit(pdev);
++ ipu_dc_exit(pdev);
++ ipu_di_exit(pdev, 1);
++ ipu_di_exit(pdev, 0);
++}
++
++static int ipu_add_subdevice_pdata(struct platform_device *pdev,
++ const char *name, int id, void *pdata, size_t pdata_size)
++{
++ struct mfd_cell cell = {
++ .platform_data = pdata,
++ .pdata_size = pdata_size,
++ };
++
++ cell.name = name;
++
++ return mfd_add_devices(&pdev->dev, id, &cell, 1, NULL, 0);
++}
++
++static int ipu_add_client_devices(struct platform_device *pdev)
++{
++ struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data;
++ struct ipuv3_fb_platform_data *fbdata;
++
++ fbdata = plat_data->fb_head0_platform_data;
++ if (fbdata) {
++ fbdata->ipu_channel_bg =
++ MX51_IPU_CHANNEL_MEM_BG_SYNC;
++ fbdata->ipu_channel_fg =
++ MX51_IPU_CHANNEL_MEM_FG_SYNC;
++ fbdata->dc_channel = 5;
++ fbdata->dp_channel = IPU_DP_FLOW_SYNC;
++
++ ipu_add_subdevice_pdata(pdev, "imx-ipuv3-fb", 0,
++ fbdata, sizeof(*fbdata));
++ }
++
++ fbdata = plat_data->fb_head1_platform_data;
++ if (fbdata) {
++ fbdata->ipu_channel_bg =
++ MX51_IPU_CHANNEL_MEM_DC_SYNC;
++ fbdata->ipu_channel_fg = -1;
++ fbdata->dc_channel = 1;
++ fbdata->dp_channel = -1;
++
++ ipu_add_subdevice_pdata(pdev, "imx-ipuv3-fb", 1,
++ fbdata, sizeof(*fbdata));
++ }
++
++ return 0;
++}
++
++static int __devinit ipu_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ unsigned long ipu_base;
++ int ret, irq1, irq2;
++
++ /* There can be only one */
++ if (ipu_dev)
++ return -EBUSY;
++
++ spin_lock_init(&ipu_lock);
++
++ ipu_dev = &pdev->dev;
++
++ irq1 = platform_get_irq(pdev, 0);
++ irq2 = platform_get_irq(pdev, 1);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (!res || irq1 < 0 || irq2 < 0)
++ return -ENODEV;
++
++ ipu_base = res->start;
++
++ ipu_cm_reg = ioremap(ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
++ if (!ipu_cm_reg) {
++ ret = -ENOMEM;
++ goto failed_ioremap1;
++ }
++
++ ipu_idmac_reg = ioremap(ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
++ if (!ipu_idmac_reg) {
++ ret = -ENOMEM;
++ goto failed_ioremap2;
++ }
++
++ ret = ipu_mipi_setup();
++ if (ret)
++ goto failed_mipi_setup;
++
++ ipu_clk = clk_get(&pdev->dev, "ipu");
++ if (IS_ERR(ipu_clk)) {
++ ret = PTR_ERR(ipu_clk);
++ dev_err(&pdev->dev, "clk_get failed with %d", ret);
++ goto failed_clk_get;
++ }
++
++ ipu_get();
++
++ ret = request_irq(irq1, ipu_irq_handler, IRQF_DISABLED, pdev->name,
++ &pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "request irq %d failed with: %d\n", irq1, ret);
++ goto failed_request_irq1;
++ }
++
++ ret = request_irq(irq2, ipu_irq_handler, IRQF_DISABLED, pdev->name,
++ &pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "request irq %d failed with: %d\n", irq2, ret);
++ goto failed_request_irq2;
++ }
++
++ ipu_reset();
++
++ ret = ipu_submodules_init(pdev, ipu_base, ipu_clk);
++ if (ret)
++ goto failed_submodules_init;
++
++ /* Set sync refresh channels as high priority */
++ ipu_idmac_write(0x18800000, IDMAC_CHA_PRI(0));
++
++ ret = ipu_add_client_devices(pdev);
++ if (ret) {
++ dev_err(&pdev->dev, "adding client devices failed with %d\n", ret);
++ goto failed_add_clients;
++ }
++
++ ipu_put();
++
++ return 0;
++
++failed_add_clients:
++ ipu_submodules_exit(pdev, ipu_base);
++failed_submodules_init:
++ free_irq(irq2, &pdev->dev);
++failed_request_irq2:
++ free_irq(irq1, &pdev->dev);
++ ipu_put();
++failed_request_irq1:
++ clk_put(ipu_clk);
++failed_clk_get:
++failed_mipi_setup:
++ iounmap(ipu_idmac_reg);
++failed_ioremap2:
++ iounmap(ipu_cm_reg);
++failed_ioremap1:
++
++ return ret;
++}
++
++static int __devexit ipu_remove(struct platform_device *pdev)
++{
++ struct resource *res;
++ unsigned long ipu_base;
++ int irq1, irq2;
++
++ irq1 = platform_get_irq(pdev, 0);
++ irq2 = platform_get_irq(pdev, 1);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ ipu_base = res->start;
++
++ mfd_remove_devices(&pdev->dev);
++ ipu_submodules_exit(pdev, ipu_base);
++ free_irq(irq2, &pdev->dev);
++ free_irq(irq1, &pdev->dev);
++ iounmap(ipu_idmac_reg);
++ iounmap(ipu_cm_reg);
++
++ if (ipu_use_count != 0) {
++ dev_err(ipu_dev, "unbalanced use count: %d\n", ipu_use_count);
++ clk_disable(ipu_clk);
++ }
++
++ clk_put(ipu_clk);
++ ipu_dev = NULL;
++
++ return 0;
++}
++
++static struct platform_driver mxcipu_driver = {
++ .driver = {
++ .name = "imx-ipuv3",
++ },
++ .probe = ipu_probe,
++ .remove = __devexit_p(ipu_remove),
++};
++
++static int __init ipu_gen_init(void)
++{
++ int32_t ret;
++
++ ret = platform_driver_register(&mxcipu_driver);
++ return 0;
++}
++subsys_initcall(ipu_gen_init);
++
++static void __exit ipu_gen_uninit(void)
++{
++ platform_driver_unregister(&mxcipu_driver);
++}
++module_exit(ipu_gen_uninit);
++
++MODULE_DESCRIPTION("i.MX IPU v3 driver");
++MODULE_AUTHOR("Sascha Hauer <s....@pe...>");
++MODULE_LICENSE("GPL");
+Index: linux-3.0.10/drivers/mfd/imx-ipu-v3/ipu-cpmem.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.10/drivers/mfd/imx-ipu-v3/ipu-cpmem.c 2011-11-30 17:07:12.000000000 +0100
+@@ -0,0 +1,612 @@
++/*
++ * Copyright (c) 2010 Sascha Hauer <s....@pe...>
++ * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/mfd/imx-ipu-v3.h>
++#include <linux/types.h>
++#include <linux/bitrev.h>
++#include <linux/io.h>
++
++#include "ipu-prv.h"
++
++#define __F(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
++
++#define IPU_FIELD_XV __F(0, 0, 10)
++#define IPU_FIELD_YV __F(0, 10, 9)
++#define IPU_FIELD_XB __F(0, 19, 13)
++#define IPU_FIELD_YB __F(0, 32, 12)
++#define IPU_FIELD_NSB_B __F(0, 44, 1)
++#define IPU_FIELD_CF __F(0, 45, 1)
++#define IPU_FIELD_UBO __F(0, 46, 22)
++#define IPU_FIELD_VBO __F(0, 68, 22)
++#define IPU_FIELD_IOX __F(0, 90, 4)
++#define IPU_FIELD_RDRW __F(0, 94, 1)
++#define IPU_FIELD_SO __F(0, 113, 1)
++#define IPU_FIELD_BNDM __F(0, 114, 3)
++#define IPU_FIELD_BM __F(0, 117, 2)
++#define IPU_FIELD_ROT __F(0, 119, 1)
++#define IPU_FIELD_HF __F(0, 120, 1)
++#define IPU_FIELD_VF __F(0, 121, 1)
++#define IPU_FIELD_THE __F(0, 122, 1)
++#define IPU_FIELD_CAP __F(0, 123, 1)
++#define IPU_FIELD_CAE __F(0, 124, 1)
++#define IPU_FIELD_FW __F(0, 125, 13)
++#define IPU_FIELD_FH __F(0, 138, 12)
++#define IPU_FIELD_EBA0 __F(1, 0, 29)
++#define IPU_FIELD_EBA1 __F(1, 29, 29)
++#define IPU_FIELD_ILO __F(1, 58, 20)
++#define IPU_FIELD_NPB __F(1, 78, 7)
++#define IPU_FIELD_PFS __F(1, 85, 4)
++#define IPU_FIELD_ALU __F(1, 89, 1)
++#define IPU_FIELD_ALBM __F(1, 90, 3)
++#define IPU_FIELD_ID __F(1, 93, 2)
++#define IPU_FIELD_TH __F(1, 95, 7)
++#define IPU_FIELD_SLY __F(1, 102, 14)
++#define IPU_FIELD_WID3 __F(1, 125, 3)
++#define IPU_FIELD_SLUV __F(1, 128, 14)
++#define IPU_FIELD_CRE __F(1, 149, 1)
++
++#define IPU_FIELD_XV __F(0, 0, 10)
++#define IPU_FIELD_YV __F(0, 10, 9)
++#define IPU_FIELD_XB __F(0, 19, 13)
++#define IPU_FIELD_YB __F(0, 32, 12)
++#define IPU_FIELD_NSB_B __F(0, 44, 1)
++#define IPU_FIELD_CF __F(0, 45, 1)
++#define IPU_FIELD_SX __F(0, 46, 12)
++#define IPU_FIELD_SY __F(0, 58, 11)
++#define IPU_FIELD_NS __F(0, 69, 10)
++#define IPU_FIELD_SDX __F(0, 79, 7)
++#define IPU_FIELD_SM __F(0, 86, 10)
++#define IPU_FIELD_SCC __F(0, 96, 1)
++#define IPU_FIELD_SCE __F(0, 97, 1)
++#define IPU_FIELD_SDY __F(0, 98, 7)
++#define IPU_FIELD_SDRX __F(0, 105, 1)
++#define IPU_FIELD_SDRY __F(0, 106, 1)
++#define IPU_FIELD_BPP __F(0, 107, 3)
++#define IPU_FIELD_DEC_SEL __F(0, 110, 2)
++#define IPU_FIELD_DIM __F(0, 112, 1)
++#define IPU_FIELD_SO __F(0, 113, 1)
++#define IPU_FIELD_BNDM __F(0, 114, 3)
++#define IPU_FIELD_BM __F(0, 117, 2)
++#define IPU_FIELD_ROT __F(0, 119, 1)
++#define IPU_FIELD_HF __F(0, 120, 1)
++#define IPU_FIELD_VF __F(0, 121, 1)
++#define IPU_FIELD_THE __F(0, 122, 1)
++#define IPU_FIELD_CAP __F(0, 123, 1)
++#define IPU_FIELD_CAE __F(0, 124, 1)
++#define IPU_FIELD_FW __F(0, 125, 13)
++#define IPU_FIELD_FH __F(0, 138, 12)
++#define IPU_FIELD_EBA0 __F(1, 0, 29)
++#define IPU_FIELD_EBA1 __F(1, 29, 29)
++#define IPU_FIELD_ILO __F(1, 58, 20)
++#define IPU_FIELD_NPB __F(1, 78, 7)
++#define IPU_FIELD_PFS __F(1, 85, 4)
++#define IPU_FIELD_ALU __F(1, 89, 1)
++#define IPU_FIELD_ALBM __F(1, 90, 3)
++#define IPU_FIELD_ID __F(1, 93, 2)
++#define IPU_FIELD_TH __F(1, 95, 7)
++#define IPU_FIELD_SL __F(1, 102, 14)
++#define IPU_FIELD_WID0 __F(1, 116, 3)
++#define IPU_FIELD_WID1 __F(1, 119, 3)
++#define IPU_FIELD_WID2 __F(1, 122, 3)
++#define IPU_FIELD_WID3 __F(1, 125, 3)
++#define IPU_FIELD_OFS0 __F(1, 128, 5)
++#define IPU_FIELD_OFS1 __F(1, 133, 5)
++#define IPU_FIELD_OFS2 __F(1, 138, 5)
++#define IPU_FIELD_OFS3 __F(1, 143, 5)
++#define IPU_FIELD_SXYS __F(1, 148, 1)
++#define IPU_FIELD_CRE __F(1, 149, 1)
++#define IPU_FIELD_DEC_SEL2 __F(1, 150, 1)
++
++static u32 *ipu_cpmem_base;
++static struct device *ipu_dev;
++
++struct ipu_ch_param_word {
++ u32 data[5];
++ u32 res[3];
++};
++
++struct ipu_ch_param {
++ struct ipu_ch_param_word word[2];
++};
++
++static u32 ipu_bytes_per_pixel(u32 fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_GENERIC: /* generic data */
++ case IPU_PIX_FMT_RGB332:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YUV422P:
++ return 1;
++
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ return 2;
++
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ return 3;
++
++ case IPU_PIX_FMT_GENERIC_32: /* generic data */
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ return 4;
++
++ default:
++ return 1;
++ }
++}
++
++bool ipu_pixel_format_has_alpha(u32 fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_ABGR32:
++ return true;
++
++ default:
++ return false;
++ }
++}
++
++#define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
++
++static inline void ipu_ch_param_set_field(struct ipu_ch_param *base, u32 wbs, u32 v)
++{
++ u32 bit = (wbs >> 8) % 160;
++ u32 size = wbs & 0xff;
++ u32 word = (wbs >> 8) / 160;
++ u32 i = bit / 32;
++ u32 ofs = bit % 32;
++ u32 mask = (1 << size) - 1;
++
++ pr_debug("%s %d %d %d\n", __func__, word, bit , size);
++
++ base->word[word].data[i] &= ~(mask << ofs);
++ base->word[word].data[i] |= v << ofs;
++
++ if ((bit + size - 1) / 32 > i) {
++ base->word[word].data[i + 1] &= ~(v >> (mask ? (32 - ofs) : 0));
++ base->word[word].data[i + 1] |= v >> (ofs ? (32 - ofs) : 0);
++ }
++}
++
++static inline u32 ipu_ch_param_read_field(struct ipu_ch_param *base, u32 wbs)
++{
++ u32 bit = (wbs >> 8) % 160;
++ u32 size = wbs & 0xff;
++ u32 word = (wbs >> 8) / 160;
++ u32 i = bit / 32;
++ u32 ofs = bit % 32;
++ u32 mask = (1 << size) - 1;
++ u32 val = 0;
++
++ pr_debug("%s %d %d %d\n", __func__, word, bit , size);
++
++ val = (base->word[word].data[i] >> ofs) & mask;
++
++ if ((bit + size - 1) / 32 > i) {
++ u32 tmp;
++ tmp = base->word[word].data[i + 1];
++ tmp &= mask >> (ofs ? (32 - ofs) : 0);
++ val |= tmp << (ofs ? (32 - ofs) : 0);
++ }
++
++ return val;
++}
++
++static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
++ int red_width, int red_offset,
++ int green_width, int green_offset,
++ int blue_width, int blue_offset,
++ int alpha_width, int alpha_offset)
++{
++ /* Setup red width and offset */
++ ipu_ch_param_set_field(p, IPU_FIELD_WID0, red_width - 1);
++ ipu_ch_param_set_field(p, IPU_FIELD_OFS0, red_offset);
++ /* Setup green width and offset */
++ ipu_ch_param_set_field(p, IPU_FIELD_WID1, green_width - 1);
++ ipu_ch_param_set_field(p, IPU_FIELD_OFS1, green_offset);
++ /* Setup blue width and offset */
++ ipu_ch_param_set_field(p, IPU_FIELD_WID2, blue_width - 1);
++ ipu_ch_param_set_field(p, IPU_FIELD_OFS2, blue_offset);
++ /* Setup alpha width and offset */
++ ipu_ch_param_set_field(p, IPU_FIELD_WID3, alpha_width - 1);
++ ipu_ch_param_set_field(p, IPU_FIELD_OFS3, alpha_offset);
++}
++
++static inline void ipu_ch_param_dump(int ch)
++{
++ struct ipu_ch_param *p = ipu_ch_param_addr(ch);
++ pr_debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
++ p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
++ p->word[0].data[3], p->word[0].data[4]);
++ pr_debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
++ p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
++ p->word[1].data[3], p->word[1].data[4]);
++ pr_debug("PFS 0x%x\n", ipu_ch_param_read_field(p, IPU_FIELD_PFS));
++ pr_debug("BPP 0x%x\n", ipu_ch_param_read_field(p, IPU_FIELD_BPP));
++ pr_debug("NPB 0x%x\n", ipu_ch_param_read_field(p, IPU_FIELD_NPB));
++
++ pr_debug("FW %d\n", ipu_ch_param_read_field(p, IPU_FIELD_FW));
++ pr_debug("FH %d\n", ipu_ch_param_read_field(p, IPU_FIELD_FH));
++ pr_debug("Stride %d\n", ipu_ch_param_read_field(p, IPU_FIELD_SL));
++
++ pr_debug("Width0 %d+1\n", ipu_ch_param_read_field(p, IPU_FIELD_WID0));
++ pr_debug("Width1 %d+1\n", ipu_ch_param_read_field(p, IPU_FIELD_WID1));
++ pr_debug("Width2 %d+1\n", ipu_ch_param_read_field(p, IPU_FIELD_WID2));
++ pr_debug("Width3 %d+1\n", ipu_ch_param_read_field(p, IPU_FIELD_WID3));
++ pr_debug("Offset0 %d\n", ipu_ch_param_read_field(p, IPU_FIELD_OFS0));
++ pr_debug("Offset1 %d\n", ipu_ch_param_read_field(p, IPU_FIELD_OFS1));
++ pr_debug("Offset2 %d\n", ipu_ch_param_read_field(p, IPU_FIELD_OFS2));
++ pr_debug("Offset3 %d\n", ipu_ch_param_read_field(p, IPU_FIELD_OFS3));
++}
++
++static inline void ipu_ch_param_set_burst_size(u32 ch,
++ u16 burst_pixels)
++{
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_NPB,
++ burst_pixels - 1);
++};
++
++static inline int ipu_ch_param_get_burst_size(u32 ch)
++{
++ return ipu_ch_param_read_field(ipu_ch_param_addr(ch), IPU_FIELD_NPB) + 1;
++};
++
++static inline int ipu_ch_param_get_bpp(u32 ch)
++{
++ return ipu_ch_param_read_field(ipu_ch_param_addr(ch), IPU_FIELD_BPP);
++};
++
++static inline void ipu_ch_param_set_buffer(u32 ch, int bufNum,
++ dma_addr_t phyaddr)
++{
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch),
++ bufNum ? IPU_FIELD_EBA1 : IPU_FIELD_EBA0,
++ phyaddr / 8);
++};
++
++#define IPU_FIELD_ROT_HF_VF __F(0, 119, 3)
++
++static inline void ipu_ch_param_set_rotation(u32 ch,
++ ipu_rotate_mode_t rot)
++{
++ u32 temp_rot = bitrev8(rot) >> 5;
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_ROT_HF_VF, temp_rot);
++};
++
++static inline void ipu_ch_param_set_block_mode(u32 ch)
++{
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_BM, 1);
++};
++
++static inline void ipu_ch_param_set_alpha_use_separate_channel(u32 ch,
++ bool option)
++{
++ if (option)
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_ALU, 1);
++ else
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_ALU, 0);
++};
++
++static inline void ipu_ch_param_set_alpha_condition_read(u32 ch)
++{
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_CRE, 1);
++};
++
++static inline void ipu_ch_param_set_alpha_buffer_memory(u32 ch)
++{
++ int alp_mem_idx;
++
++ switch (ch) {
++ case 14: /* PRP graphic */
++ alp_mem_idx = 0;
++ break;
++ case 15: /* PP graphic */
++ alp_mem_idx = 1;
++ break;
++ case 23: /* DP BG SYNC graphic */
++ alp_mem_idx = 4;
++ break;
++ case 27: /* DP FG SYNC graphic */
++ alp_mem_idx = 2;
++ break;
++ default:
++ dev_err(ipu_dev, "unsupported correlated channel of local alpha channel\n");
++ return;
++ }
++
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_ALBM, alp_mem_idx);
++};
++
++static inline void ipu_ch_param_set_interlaced_scan(u32 ch)
++{
++ u32 stride;
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_SO, 1);
++ stride = ipu_ch_param_read_field(ipu_ch_param_addr(ch), IPU_FIELD_SL) + 1;
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_ILO, stride / 8);
++ stride *= 2;
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_SLY, stride - 1);
++};
++
++static inline void ipu_ch_param_set_high_priority(u32 ch)
++{
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_ID, 1);
++};
++
++static inline void ipu_ch_params_set_alpha_width(u32 ch, int alpha_width)
++{
++ ipu_ch_param_set_field(ipu_ch_param_addr(ch), IPU_FIELD_WID3,
++ alpha_width - 1);
++}
++
++static int ipu_ch_param_init(int ch,
++ u32 pixel_fmt, u32 width,
++ u32 height, u32 stride,
++ u32 u, u32 v,
++ u32 uv_stride, dma_addr_t addr0,
++ dma_addr_t addr1)
++{
++ u32 u_offset = 0;
++ u32 v_offset = 0;
++ struct ipu_ch_param params;
++
++ memset(¶ms, 0, sizeof(params));
++
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_FW, width - 1);
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_FH, height - 1);
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_SLY, stride - 1);
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_EBA0, addr0 >> 3);
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_EBA1, addr1 >> 3);
++
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ /* Represents 8-bit Generic data */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 5); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 6); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 63); /* burst size */
++
++ break;
++ case IPU_PIX_FMT_GENERIC_32:
++ /* Represents 32-bit Generic data */
++ break;
++ case IPU_PIX_FMT_RGB565:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 3); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 7); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 15); /* burst size */
++
++ ipu_ch_params_set_packing(¶ms, 5, 0, 6, 5, 5, 11, 8, 16);
++ break;
++ case IPU_PIX_FMT_BGR24:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 1); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 7); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 19); /* burst size */
++
++ ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 1); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 7); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 19); /* burst size */
++
++ ipu_ch_params_set_packing(¶ms, 8, 16, 8, 8, 8, 0, 8, 24);
++ break;
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 0); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 7); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 15); /* burst size */
++
++ ipu_ch_params_set_packing(¶ms, 8, 8, 8, 16, 8, 24, 8, 0);
++ break;
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 0); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 7); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 15); /* burst size */
++
++ ipu_ch_params_set_packing(¶ms, 8, 24, 8, 16, 8, 8, 8, 0);
++ break;
++ case IPU_PIX_FMT_ABGR32:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 0); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 7); /* pix format */
++
++ ipu_ch_params_set_packing(¶ms, 8, 0, 8, 8, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_UYVY:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 3); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 0xA); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 15); /* burst size */
++ break;
++ case IPU_PIX_FMT_YUYV:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_BPP, 3); /* bits/pixel */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 0x8); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 31); /* burst size */
++ break;
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 2); /* pix format */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * height;
++ v_offset = u_offset + (uv_stride * height / 2);
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 31); /* burst size */
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 1); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 31); /* burst size */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = (v == 0) ? stride * height : v;
++ u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 1); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 31); /* burst size */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = (u == 0) ? stride * height : u;
++ v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
++ break;
++ case IPU_PIX_FMT_NV12:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_PFS, 4); /* pix format */
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_NPB, 31); /* burst size */
++ uv_stride = stride;
++ u_offset = (u == 0) ? stride * height : u;
++ break;
++ default:
++ dev_err(ipu_dev, "mxc ipu: unimplemented pixel format: %d\n",
++ pixel_fmt);
++ return -EINVAL;
++ }
++ /* set burst size to 16 */
++ if (uv_stride)
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_SLUV, uv_stride - 1);
++
++ if (u > u_offset)
++ u_offset = u;
++
++ if (v > v_offset)
++ v_offset = v;
++
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_UBO, u_offset / 8);
++ ipu_ch_param_set_field(¶ms, IPU_FIELD_VBO, v_offset / 8);
++
++ pr_debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
++ memcpy(ipu_ch_param_addr(ch), ¶ms, sizeof(params));
++ return 0;
++}
++
++/*
++ * This function is called to initialize a buffer for a IPU channel.
++ *
++ * @param channel The IPU channel.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width Input parameter for width of buffer in pixels.
++ *
++ * @param height Input parameter for height of buffer in pixels.
++ *
++ * @param stride Input parameter for stride length of buffer
++ * in pixels.
++ *
++ * @param rot_mode Input parameter for rotation setting of buffer.
++ * A rotation setting other than
++ * IPU_ROTATE_VERT_FLIP
++ * should only be used for input buffers of
++ * rotation channels.
++ *
++ * @param phyaddr_0 Input parameter buffer 0 physical address.
++ *
++ * @param phyaddr_1 Input parameter buffer 1 physical address.
++ * Setting this to a value other than NULL enables
++ * double buffering mode.
++ *
++ * @param u private u offset for additional cropping,
++ * zero if not used.
++ *
++ * @param v private v offset for additional cropping,
++ * zero if not used.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int ipu_idmac_init_channel_buffer(struct ipu_channel *channel,
++ u32 pixel_fmt,
++ u16 width, u16 height,
++ u32 stride,
++ ipu_rotate_mode_t rot_mode,
++ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
++ u32 u, u32 v, bool interlaced)
++{
++ int ret = 0;
++ u32 dma_chan = channel->num;
++
++ if (stride < width * ipu_bytes_per_pixel(pixel_fmt))
++ stride = width * ipu_bytes_per_pixel(pixel_fmt);
++
++ if (stride % 4) {
++ dev_err(ipu_dev,
++ "Stride not 32-bit aligned, stride = %d\n", stride);
++ return -EINVAL;
++ }
++
++ ipu_get();
++
++ /* Build parameter memory data for DMA channel */
++ ret = ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
++ phyaddr_0, phyaddr_1);
++ if (ret)
++ goto out;
++
++ if (rot_mode)
++ ipu_ch_param_set_rotation(dma_chan, rot_mode);
++
++ if (interlaced)
++ ipu_ch_param_set_interlaced_scan(dma_chan);
++
++ if (idmac_idma_is_set(IDMAC_CHA_PRI, dma_chan))
++ ipu_ch_param_set_high_priority(dma_chan);
++
++ ipu_ch_param_dump(dma_chan);
++out:
++ ipu_put();
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_idmac_init_channel_buffer);
++
++int ipu_idmac_update_channel_buffer(struct ipu_channel *channel,
++ u32 buf_num, dma_addr_t phyaddr)
++{
++ u32 dma...
[truncated message content] |
