[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2575-gd2776ab
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2575-gd2776ab
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From: jorasse <jo...@us...> - 2011-11-09 21:13:41
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via d2776ab860ba7f5e529eaf1ed4e8330e1babdd1c (commit)
from 879a54afa91f6886edef77f4b6f422a5f40e64ae (commit)
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- Log -----------------------------------------------------------------
commit d2776ab860ba7f5e529eaf1ed4e8330e1babdd1c
Author: Eric Jarrige <eri...@ar...>
Date: Wed Nov 9 22:20:46 2011 +0100
[U-Boot] APF51: Improve mDDR XSR timing and fix EMR configuration.
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf51/apf51-u-boot-2010.03.h | 10 +++++-----
.../u-boot/2010.03/u-boot-2010.03-401-apf51.patch | 4 ++--
.../u-boot-2010.03-409-apf51-nand-spl.patch | 4 ++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
index 5ff0ecb..c0732f3 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
@@ -29,7 +29,7 @@
#define CONFIG_VERSION_VARIABLE
#define CONFIG_ENV_VERSION "0.5"
-#define CONFIG_IDENT_STRING " apf51 patch 0.5"
+#define CONFIG_IDENT_STRING " apf51 patch 0.6"
//#define APF51_PROTO
//#define APF51_RECOVER
@@ -790,7 +790,7 @@
#define CONFIG_SYS_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 13 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.. refresh */
-#define CONFIG_SYS_SDRAM_XSR_DELAY 138 /* ns Exit self refresh to any command */
+#define CONFIG_SYS_SDRAM_XSR_DELAY 138 /* ns Exit self refresh to any command (>= 25 ddr_clk) */
#define CONFIG_SYS_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* WRITE to READ Command Delay 0=1ck 1=2ck */
#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk)*/
@@ -812,7 +812,7 @@
#define CONFIG_SYS_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 13 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.. refresh */
-#define CONFIG_SYS_SDRAM_XSR_DELAY 138 /* ns Exit self refresh to any command */
+#define CONFIG_SYS_SDRAM_XSR_DELAY 138 /* ns Exit self refresh to any command (>= 25 ddr_clk) */
#define CONFIG_SYS_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* WRITE to READ Command Delay 0=1ck 1=2ck */
#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk)*/
@@ -834,7 +834,7 @@
#define CONFIG_SYS_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 14 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.. refresh */
-#define CONFIG_SYS_SDRAM_XSR_DELAY 113 /* ns Exit self refresh to any command */
+#define CONFIG_SYS_SDRAM_XSR_DELAY 125 /* ns Exit self refresh to any command (>= 25 ddr_clk) */
#define CONFIG_SYS_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* WRITE to READ Command Delay 0=1ck 1=2ck */
#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk)*/
@@ -947,7 +947,7 @@
#define CONFIG_SYS_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 column address bits */
#define CONFIG_SYS_SDRAM_NUM_ROW 13 /* 11, 12 or 13 row address bits */
#define CONFIG_SYS_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192.. refresh */
-#define CONFIG_SYS_SDRAM_XSR_DELAY 140 /* ns Exit self refresh to any command */
+#define CONFIG_SYS_SDRAM_XSR_DELAY 140 /* ns Exit self refresh to any command (>= 25 ddr_clk) */
#define CONFIG_SYS_SDRAM_EXIT_PWD 10 /* ns exit power down delay */
#define CONFIG_SYS_SDRAM_W2R_DELAY 1 /* WRITE to READ Command Delay 0=1ck 1=2ck */
#define CONFIG_SYS_SDRAM_ROW_PRECHARGE_DELAY 15 /* ns (>2 x ddr_clk)*/
diff --git a/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch b/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch
index 169458e..5c8d7b9 100644
--- a/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch
+++ b/patches/u-boot/2010.03/u-boot-2010.03-401-apf51.patch
@@ -1123,7 +1123,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_AUTOREFRESH_CMD(0));
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_AUTOREFRESH_CMD(0));
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(0, 0, CONFIG_SYS_DRR_MR_VAL));
-+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(0, 1, CONFIG_SYS_DRR_EMR_VAL));
++ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(0, 2, CONFIG_SYS_DRR_EMR_VAL));
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DDR_NOP_CMD(0));
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, CONFIG_SYS_SDRAM_ESDCTL_REGISTER_VAL);
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL);
@@ -1133,7 +1133,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/apf51.c
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_AUTOREFRESH_CMD(1));
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_AUTOREFRESH_CMD(1));
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(1, 0, CONFIG_SYS_DRR_MR_VAL));
-+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(1, 1, CONFIG_SYS_DRR_EMR_VAL));
++ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(1, 2, CONFIG_SYS_DRR_EMR_VAL));
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DDR_NOP_CMD(1));
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, CONFIG_SYS_SDRAM_ESDCTL_REGISTER_VAL);
+ printf(dcd_item, i++, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL);
diff --git a/patches/u-boot/2010.03/u-boot-2010.03-409-apf51-nand-spl.patch b/patches/u-boot/2010.03/u-boot-2010.03-409-apf51-nand-spl.patch
index 7493c31..401df9d 100644
--- a/patches/u-boot/2010.03/u-boot-2010.03-409-apf51-nand-spl.patch
+++ b/patches/u-boot/2010.03/u-boot-2010.03-409-apf51-nand-spl.patch
@@ -203,7 +203,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/flash_header.S
+MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_AUTOREFRESH_CMD(0))
+MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_AUTOREFRESH_CMD(0))
+MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(0, 0, CONFIG_SYS_DRR_MR_VAL))
-+MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(0, 1, CONFIG_SYS_DRR_EMR_VAL))
++MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(0, 2, CONFIG_SYS_DRR_EMR_VAL))
+MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DDR_NOP_CMD(0))
+MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, CONFIG_SYS_SDRAM_ESDCTL_REGISTER_VAL)
+MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
@@ -215,7 +215,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf51/flash_header.S
+MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_AUTOREFRESH_CMD(1))
+MXC_DCD_ITEM(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_AUTOREFRESH_CMD(1))
+MXC_DCD_ITEM(58, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(1, 0, CONFIG_SYS_DRR_MR_VAL))
-+MXC_DCD_ITEM(59, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(1, 1, CONFIG_SYS_DRR_EMR_VAL))
++MXC_DCD_ITEM(59, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DRR_LMR_CMD(1, 2, CONFIG_SYS_DRR_EMR_VAL))
+MXC_DCD_ITEM(60, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, CONFIG_SYS_DDR_NOP_CMD(1))
+MXC_DCD_ITEM(61, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, CONFIG_SYS_SDRAM_ESDCTL_REGISTER_VAL)
+MXC_DCD_ITEM(62, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
hooks/post-receive
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armadeus
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