[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2543-g388c5b3
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.0-2543-g388c5b3
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From: Julien B a. A. <ar...@us...> - 2011-10-19 09:30:59
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 388c5b328a8fab881fcbb3f2f05433e253509325 (commit)
via 76d730abbdd8c41f10e4eadef8892374f73f8252 (commit)
from 4bead27ab869003c0f23cddee5ed10140bab61c9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 388c5b328a8fab881fcbb3f2f05433e253509325
Author: Julien Boibessot <jul...@ar...>
Date: Wed Oct 19 11:24:27 2011 +0200
Indent
commit 76d730abbdd8c41f10e4eadef8892374f73f8252
Author: Julien Boibessot <jul...@ar...>
Date: Wed Oct 19 11:21:31 2011 +0200
[DEBUG] Add i.MX51 SCC registers to imxregs
-----------------------------------------------------------------------
Summary of changes:
target/linux/debug/imxregs/imx51regs.h | 90 +++++++++++++++++++++++--------
1 files changed, 67 insertions(+), 23 deletions(-)
diff --git a/target/linux/debug/imxregs/imx51regs.h b/target/linux/debug/imxregs/imx51regs.h
index 4d8d787..cc6b0b5 100644
--- a/target/linux/debug/imxregs/imx51regs.h
+++ b/target/linux/debug/imxregs/imx51regs.h
@@ -62,30 +62,30 @@ static struct reg_info regs[] =
{ "CCGR6", 0x73fd4080, 0, 0xffffffff, 'x', "CCM Clock Gating Register 6" },
{ "CMEOR", 0x73fd4084, 0, 0xffffffff, 'x', "CCM Module Enable Override Register" },
/* GPT */
-{ "GPTCR_1", 0x73fa0000, 0, 0xffffffff, 'x', "GPT1 Control Register" },
-{ "GPTPR_1", 0x73fa0004, 0, 0xffffffff, 'x', "GPT1 Prescaler Register" },
-{ "GPTSR_1", 0x73fa0008, 0, 0xffffffff, 'x', "GPT1 Status Register" },
-{ "GPTIR_1", 0x73fa000c, 0, 0xffffffff, 'x', "GPT1 Interrupt Register" },
-{ "GPTOCR1_1", 0x73fa0010, 0, 0xffffffff, 'x', "GPT1 Output Compare Register 1" },
-{ "GPTOCR2_1", 0x73fa0014, 0, 0xffffffff, 'x', "GPT1 Output Compare Register 2" },
-{ "GPTOCR3_1", 0x73fa0018, 0, 0xffffffff, 'x', "GPT1 Output Compare Register 3" },
-{ "GPTICR1_1", 0x73fa001c, 0, 0xffffffff, 'x', "GPT1 Input capture Register 1" },
-{ "GPTICR2_1", 0x73fa0020, 0, 0xffffffff, 'x', "GPT1 Input capture Register 2" },
-{ "GPTCNT_1", 0x73fa0024, 0, 0xffffffff, 'x', "GPT1 Counter Register" },
+{ "GPTCR_1", 0x73fa0000, 0, 0xffffffff, 'x', "GPT1 Control Register" },
+{ "GPTPR_1", 0x73fa0004, 0, 0xffffffff, 'x', "GPT1 Prescaler Register" },
+{ "GPTSR_1", 0x73fa0008, 0, 0xffffffff, 'x', "GPT1 Status Register" },
+{ "GPTIR_1", 0x73fa000c, 0, 0xffffffff, 'x', "GPT1 Interrupt Register" },
+{ "GPTOCR1_1", 0x73fa0010, 0, 0xffffffff, 'x', "GPT1 Output Compare Register 1" },
+{ "GPTOCR2_1", 0x73fa0014, 0, 0xffffffff, 'x', "GPT1 Output Compare Register 2" },
+{ "GPTOCR3_1", 0x73fa0018, 0, 0xffffffff, 'x', "GPT1 Output Compare Register 3" },
+{ "GPTICR1_1", 0x73fa001c, 0, 0xffffffff, 'x', "GPT1 Input capture Register 1" },
+{ "GPTICR2_1", 0x73fa0020, 0, 0xffffffff, 'x', "GPT1 Input capture Register 2" },
+{ "GPTCNT_1", 0x73fa0024, 0, 0xffffffff, 'x', "GPT1 Counter Register" },
/* PWM1 */
-{ "PWMCR_1", 0x73fb4000, 0, 0xffffffff, 'x', "PWM1 Control Register" },
-{ "PWMSR_1", 0x73fb4004, 0, 0xffffffff, 'x', "PWM1 Status Register" },
-{ "PWMIR_1", 0x73fb4008, 0, 0xffffffff, 'x', "PWM1 Interrupt Register" },
-{ "PWMSAR_1", 0x73fb400c, 0, 0xffffffff, 'x', "PWM1 Sample Register" },
-{ "PWMPR_1", 0x73fb4010, 0, 0xffffffff, 'x', "PWM1 Period Register" },
-{ "PWMCNR_1", 0x73fb4014, 0, 0xffffffff, 'x', "PWM1 Counter Register" },
+{ "PWMCR_1", 0x73fb4000, 0, 0xffffffff, 'x', "PWM1 Control Register" },
+{ "PWMSR_1", 0x73fb4004, 0, 0xffffffff, 'x', "PWM1 Status Register" },
+{ "PWMIR_1", 0x73fb4008, 0, 0xffffffff, 'x', "PWM1 Interrupt Register" },
+{ "PWMSAR_1", 0x73fb400c, 0, 0xffffffff, 'x', "PWM1 Sample Register" },
+{ "PWMPR_1", 0x73fb4010, 0, 0xffffffff, 'x', "PWM1 Period Register" },
+{ "PWMCNR_1", 0x73fb4014, 0, 0xffffffff, 'x', "PWM1 Counter Register" },
/* PWM2 */
-{ "PWMCR_2", 0x73fb8000, 0, 0xffffffff, 'x', "PWM2 Control Register" },
-{ "PWMSR_2", 0x73fb8004, 0, 0xffffffff, 'x', "PWM2 Status Register" },
-{ "PWMIR_2", 0x73fb8008, 0, 0xffffffff, 'x', "PWM2 Interrupt Register" },
-{ "PWMSAR_2", 0x73fb800c, 0, 0xffffffff, 'x', "PWM2 Sample Register" },
-{ "PWMPR_2", 0x73fb8010, 0, 0xffffffff, 'x', "PWM2 Period Register" },
-{ "PWMCNR_2", 0x73fb8014, 0, 0xffffffff, 'x', "PWM2 Counter Register" },
+{ "PWMCR_2", 0x73fb8000, 0, 0xffffffff, 'x', "PWM2 Control Register" },
+{ "PWMSR_2", 0x73fb8004, 0, 0xffffffff, 'x', "PWM2 Status Register" },
+{ "PWMIR_2", 0x73fb8008, 0, 0xffffffff, 'x', "PWM2 Interrupt Register" },
+{ "PWMSAR_2", 0x73fb800c, 0, 0xffffffff, 'x', "PWM2 Sample Register" },
+{ "PWMPR_2", 0x73fb8010, 0, 0xffffffff, 'x', "PWM2 Period Register" },
+{ "PWMCNR_2", 0x73fb8014, 0, 0xffffffff, 'x', "PWM2 Counter Register" },
/* I2C1 */
{ "IADR_1", 0x83fc8000, 0, 0xffffffff, 'x', "I2C1 Address Register" },
{ "IFDR_1", 0x83fc8004, 0, 0xffffffff, 'x', "I2C1 Frequency Divider Register" },
@@ -99,7 +99,7 @@ static struct reg_info regs[] =
{ "I2SR_2", 0x83fc400c, 0, 0xffffffff, 'x', "I2C2 Status Register" },
{ "I2DR_2", 0x83fc4010, 0, 0xffffffff, 'x', "I2C2 Data I/O Register" },
/* FEC */
-{ "EIR", 0x83fec004, 0, 0xffffffff, 'x', "FEC Interrupt Event Register" },
+{ "EIR", 0x83fec004, 0, 0xffffffff, 'x', "FEC Interrupt Event Register" },
/* AUDMUX */
{ "PTCR1", 0x83fd0000, 0, 0xffffffff, 'x', "Port Timing Control Register 1" },
{ "PDCR1", 0x83fd0004, 0, 0xffffffff, 'x', "Port Data Control Register 1" },
@@ -185,6 +185,50 @@ static struct reg_info regs[] =
{ "SaharaEn3", 0x83f98048, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
{ "SaharaEn4", 0x83f9804C, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
{ "SaharaEn5", 0x83f98050, 0, 0xffffffff, 'x', "Software setting. Upon setting proper value allows SAHARA_EN blowing." },
+/* SCC */
+{ "SCC_VER", 0x83fb4000, 0, 0xffffffff, 'x', "SCC Version" },
+{ "SCC_IC", 0x83fb4008, 0, 0xffffffff, 'x', "SCC Interrupt Control" },
+{ "SCC_CS", 0x83fb400c, 0, 0xffffffff, 'x', "SCC Command Status" },
+{ "SCC_ES", 0x83fb4010, 0, 0xffffffff, 'x', "SCC Error Status" },
+{ "SCC_DMAF", 0x83fb4014, 0, 0xffffffff, 'x', "SCC DMA Fault" },
+{ "SCC_PART", 0x83fb4018, 0, 0xffffffff, 'x', "SCC Partition Owners" },
+{ "SCC_PART_EN",0x83fb401c, 0, 0xffffffff, 'x', "SCC Partitions Engaged" },
+{ "SCC_UN0", 0x83fb4020, 0, 0xffffffff, 'x', "SCC Unique Number 0" },
+{ "SCC_UN1", 0x83fb4024, 0, 0xffffffff, 'x', "SCC Unique Number 1" },
+{ "SCC_UN2", 0x83fb4028, 0, 0xffffffff, 'x', "SCC Unique Number 2" },
+{ "SCC_UN3", 0x83fb402c, 0, 0xffffffff, 'x', "SCC Unique Number 3" },
+{ "SCC_ZERO", 0x83fb4050, 0, 0xffffffff, 'x', "SCC Zeroize Command" },
+{ "SCC_CMD", 0x83fb4054, 0, 0xffffffff, 'x', "SCC Cipher Command" },
+{ "SCC_BLACK", 0x83fb4058, 0, 0xffffffff, 'x', "SCC Cipher Black RAM Start Address" },
+{ "SCC_DBG", 0x83fb405c, 0, 0xffffffff, 'x', "SCC Internal Debug" },
+{ "SCC_CINIT1", 0x83fb4060, 0, 0xffffffff, 'x', "SCC Cipher Initialization Vector [127-96]" },
+{ "SCC_CINIT2", 0x83fb4064, 0, 0xffffffff, 'x', "SCC Cipher Initialization Vector [95-64]" },
+{ "SCC_CINIT3", 0x83fb4068, 0, 0xffffffff, 'x', "SCC Cipher Initialization Vector [63-32]" },
+{ "SCC_CINIT4", 0x83fb406c, 0, 0xffffffff, 'x', "SCC Cipher Initialization Vector [31-0]" },
+{ "SMID_PART0", 0x83fb4080, 0, 0xffffffff, 'x', "SCC SMID Partition 0" },
+{ "MAP_PART0", 0x83fb4084, 0, 0xffffffff, 'x', "SCC Master Access Permissions Partition 0" },
+{ "SMID_PART1", 0x83fb4088, 0, 0xffffffff, 'x', "SCC SMID Partition 1" },
+{ "MAP_PART1", 0x83fb408c, 0, 0xffffffff, 'x', "SCC Master Access Permissions Partition 1" },
+{ "SMID_PART2", 0x83fb4090, 0, 0xffffffff, 'x', "SCC SMID Partition 2" },
+{ "MAP_PART2", 0x83fb4094, 0, 0xffffffff, 'x', "SCC Master Access Permissions Partition 2" },
+{ "SMID_PART3", 0x83fb4098, 0, 0xffffffff, 'x', "SCC SMID Partition 3" },
+{ "MAP_PART3", 0x83fb409c, 0, 0xffffffff, 'x', "SCC Master Access Permissions Partition 3" },
+{ "SMON_STAT", 0x83fb4100, 0, 0xffffffff, 'x', "SCC Security Monitor Status" },
+{ "SMON_CMD", 0x83fb4104, 0, 0xffffffff, 'x', "SCC Security Monitor Command" },
+{ "SEQ_START", 0x83fb4108, 0, 0xffffffff, 'x', "SCC Sequence Start" },
+{ "SEQ_END", 0x83fb410c, 0, 0xffffffff, 'x', "SCC Sequence End" },
+{ "SEQ_CHK", 0x83fb4110, 0, 0xffffffff, 'x', "SCC Sequence Check" },
+{ "BIT_COUNT", 0x83fb4114, 0, 0xffffffff, 'x', "SCC Bit Count" },
+{ "BANK_INC", 0x83fb4118, 0, 0xffffffff, 'x', "SCC Bit Bank Increment Size" },
+{ "BANK_DEC", 0x83fb411c, 0, 0xffffffff, 'x', "SCC Bit Bank Decrement" },
+{ "CMP_SZ", 0x83fb4120, 0, 0xffffffff, 'x', "SCC Compare Size" },
+{ "PLN_CHK", 0x83fb4124, 0, 0xffffffff, 'x', "SCC Plaintext Check" },
+{ "CPH_CHK", 0x83fb4128, 0, 0xffffffff, 'x', "SCC Ciphertext Check" },
+{ "TIMERIV", 0x83fb412c, 0, 0xffffffff, 'x', "SCC Timer IV" },
+{ "TIMER_CTL", 0x83fb4130, 0, 0xffffffff, 'x', "SCC Timer Control" },
+{ "SEC_VIO", 0x83fb4134, 0, 0xffffffff, 'x', "SCC Security Violation Detector" },
+{ "SEC_TIMER", 0x83fb4138, 0, 0xffffffff, 'x', "SCC Security Timer" },
+{ "HA_CONF", 0x83fb413c, 0, 0xffffffff, 'x', "SCC High Assurance Configuration" },
/* SSI 3 */
{ "STX0_3", 0x83fe8000, 0, 0xffffffff, 'x', "SSI3 Transmit Data Register 0" },
{ "STX1_3", 0x83fe8004, 0, 0xffffffff, 'x', "SSI3 Transmit Data Register 1" },
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armadeus
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