[Armadeus-commitlog] armadeus branch, master, updated. release-3.4-159-g5f553e8
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[Armadeus-commitlog] armadeus branch, master, updated. release-3.4-159-g5f553e8
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From: Julien B a. A. <ar...@us...> - 2011-06-05 20:54:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 5f553e8fa8f99877f686eba49728e546057e862a (commit)
from 0a8d6c367911d0edb852f5a4e967c2c3fd1c8526 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 5f553e8fa8f99877f686eba49728e546057e862a
Author: Julien Boibessot <jul...@ar...>
Date: Sun Jun 5 22:51:41 2011 +0200
[LINUX] 2.6.38: Makes APF27 more mainline friendly and re-activates USB OTG
-----------------------------------------------------------------------
Summary of changes:
.../2.6.38/281-apf27-armadeus-add_apf27.c.patch | 213 ++---
...-apf27-armadeus-add_apf27_to_build_system.patch | 11 +-
...ct_some_mx5_regiter_settings_and_comments.patch | 23 -
...xc-ehci-factor_out_soc_specific_functions.patch | 954 ++++++++++++++++++++
...-do_ehci_init_in_board_specific_functions.patch | 793 ++++++++++++++++
...ct_some_mx5_regiter_settings_and_comments.patch | 23 +
6 files changed, 1855 insertions(+), 162 deletions(-)
delete mode 100644 buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/406-armadeus-plat-mxc-ehci-correct_some_mx5_regiter_settings_and_comments.patch
create mode 100644 buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/434-pengutronix-mxc-ehci-factor_out_soc_specific_functions.patch
create mode 100644 buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/435-pengutronix-mxc-ehci-do_ehci_init_in_board_specific_functions.patch
create mode 100644 buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/436-armadeus-plat-mxc-ehci-correct_some_mx5_regiter_settings_and_comments.patch
diff --git a/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/281-apf27-armadeus-add_apf27.c.patch b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/281-apf27-armadeus-add_apf27.c.patch
index a5c441a..4ce66b7 100644
--- a/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/281-apf27-armadeus-add_apf27.c.patch
+++ b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/281-apf27-armadeus-add_apf27.c.patch
@@ -12,20 +12,17 @@ Signed-off-by: Kevin Joly <jol...@gm...>
Index: linux-2.6.38.1/arch/arm/mach-imx/apf27.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.38.1/arch/arm/mach-imx/apf27.c 2011-05-17 22:34:43.000000000 +0200
-@@ -0,0 +1,675 @@
++++ linux-2.6.38.1/arch/arm/mach-imx/apf27.c 2011-06-03 17:42:03.000000000 +0200
+@@ -0,0 +1,614 @@
+ /*
-+ * apf27.c
-+ *
+ * Support for the APF27 System On Module
+ *
-+ * Copyright (C) 2008 - 2010 Armadeus Systems
-+ * Authors: Julien Boibessot <jul...@ar...>
-+ * Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2008-2011 ARMadeus Systems <su...@ar...>
+ *
-+ * Inspired a lot by pcm038.c which is:
++ * Based on code which is:
+ * Copyright 2007 Robert Schwebel <r.s...@pe...>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (ke...@pe...)
++ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
@@ -38,7 +35,8 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27.c
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ * MA 02110-1301, USA.
+ */
+
+#define IMX_NEEDS_DEPRECATED_SYMBOLS
@@ -153,20 +151,21 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27.c
+ PE5_PF_PWM0,
+};
+
++/* APF27 has an "on module" Ethernet transceiver */
+int lan8700_wakeup(struct phy_device *phydev)
+{
+#define LAN87xx_SPECIAL_REG 0x12
+
-+ int rc = phy_read(phydev, LAN87xx_SPECIAL_REG);
++ int rc = phy_read(phydev, LAN87xx_SPECIAL_REG);
+
-+ phy_write(phydev, LAN87xx_SPECIAL_REG, rc | 0xE0);
-+ phy_write(phydev, MII_BMCR, BMCR_RESET);
-+ udelay(1000);
-+ return 0;
++ phy_write(phydev, LAN87xx_SPECIAL_REG, rc | 0xE0);
++ phy_write(phydev, MII_BMCR, BMCR_RESET);
++ udelay(1000);
++ return 0;
+}
+
+/* APF27 has a Micron 128MiB 1,8V NAND flash, 16 bits width */
-+static struct mxc_nand_platform_data apf27_nand_board_info __initconst = {
++static const struct mxc_nand_platform_data apf27_nand_board_info __initconst = {
+ .width = 2,
+ .hw_ecc = 1,
+ .flash_bbt = 1, /* we handle Bad Block Table */
@@ -174,22 +173,18 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27.c
+
+
+/* APF27 has an I2C EEPROM on I2C2 Bus */
-+static struct imxi2c_platform_data apf27_i2c_1_data __initconst = {
++static const struct imxi2c_platform_data apf27_i2c_1_data __initconst = {
+ .bitrate = 100000,
+};
+
+static struct i2c_board_info apf27_i2c_devices_bus1[] = {
-+ [0] = {
-+ .type = "24c02",
-+ .flags = 0,
-+ .addr = 0x50,
-+ .platform_data = NULL,
-+ .irq = 0
++ {
++ I2C_BOARD_INFO("24c02", 0x50),
+ },
+};
+
-+
-+/* APF27 has an RS232 debug port/console on UART1 with "on module" transceiver */
++/* APF27 has an RS232 debug port/console on UART1 with "on module"
++ transceiver */
+static struct imxuart_platform_data uart0_pdata = {
+ .flags = 0,
+};
@@ -203,44 +198,8 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27.c
+#endif
+};
+
-+
++/* APF27 has an "on module" transceiver for USB OTG */
+#if 0
-+/* APF27 has an onboard PHY (ISP1504) on OTG USB port */
-+
-+static int isp1504_set_vbus_power(void __iomem *view, int on)
-+{
-+ int ret = 0;
-+
-+ ret = isp1504_check_presence(view);
-+ if (ret)
-+ return ret;
-+
-+ if (on) {
-+ /* force disconnection of the DM/DP signals. This
-+ avoid powering the connected device through these lines */
-+ ulpi_set(RESET, ISP1504_FCNCTL, view);
-+ mdelay(10); /*wait until the supply is really down*/
-+ ulpi_clear(RESET, ISP1504_FCNCTL, view);
-+ mdelay(1);
-+
-+ ret = ulpi_set(DRV_VBUS_EXT | /* enable external Vbus */
-+ DRV_VBUS | /* enable internal Vbus */
-+ USE_EXT_VBUS_IND | /* use external indicator */
-+ CHRG_VBUS, /* charge Vbus */
-+ ISP1504_OTGCTL, view);
-+ } else {
-+ ret = ulpi_clear(DRV_VBUS_EXT | /* disable external Vbus */
-+ DRV_VBUS, /* disable internal Vbus */
-+ ISP1504_OTGCTL, view);
-+
-+ ret |= ulpi_set(USE_EXT_VBUS_IND | /* use external indicator */
-+ DISCHRG_VBUS, /* discharge Vbus */
-+ ISP1504_OTGCTL, view);
-+ }
-+
-+ return ret;
-+}
-+
+static void isp1504_suspend(void __iomem *view)
+{
+ /* isp1504_set_vbus_power(view, 0); needed ? */
@@ -258,92 +217,72 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27.c
+ /* STP now managed by the USB host ctrl */
+ mxc_gpio_mode(PE1_PF_USBOTG_STP);
+}
++#endif
++static int otg_mode_host = 1;
+
-+#define UOG_USBCMD 0x140
-+#define UOG_ULPIVIEW 0x170
-+#define UOG_PORTSC1 0x184
-+#define USB_CTRL 0x600
-+#define PORTSC_PTS_MASK (3 << 30)
-+#define PORTSC_PTS_ULPI (2 << 30)
-+
-+static void apf27_usbotg_reset(void)
++static int __init apf27_otg_mode(char *options)
+{
-+ uint32_t temp;
++ if (!strcmp(options, "host"))
++ otg_mode_host = 1;
++ else if (!strcmp(options, "device"))
++ otg_mode_host = 0;
++ else
++ pr_info("otg_mode neither \"host\" nor \"device\". "
++ "Defaulting to host\n");
+
-+ temp = readl(MX27_IO_ADDRESS(OTG_BASE_ADDR) + UOG_USBCMD);
-+ temp |= 0x02;
-+ writel(temp, MX27_IO_ADDRESS(OTG_BASE_ADDR) + UOG_USBCMD);
-+ pr_debug("reset controller: 0x%08x\n", temp);
-+ mdelay(10);
++ return 0;
+}
-+#endif
++__setup("otg_mode=", apf27_otg_mode);
+
-+#if 0
-+static int apf27_usbotg_init(struct platform_device *pdev)
++static void apf27_usbotg_phy_init(void)
+{
-+ int ret;
-+ uint32_t temp;
++#define USBCTRL_OFFSET 0x600
++#define USBCTRL_UIE_BIT (1 << 28)
++#define USBCTRL_WIE_BIT (1 << 27)
++#define USBCMD_OFFSET 0x140
++#define USBCMD_RST_BIT (1 << 1)
++#define PORTSC1_OFFSET 0x184
++#define PORTSC_PTS_MASK (3 << 30)
++#define PORTSC_PTS_ULPI (2 << 30)
+
-+ ret = mxc_gpio_setup_multiple_pins(mxc_usbotg_pins,
-+ ARRAY_SIZE(mxc_usbotg_pins), "USB OTG");
-+ if (ret)
-+ return ret;
++ unsigned int reg;
+
+ /* Tweak power/wake up handling */
-+ temp = readl(IO_ADDRESS(OTG_BASE_ADDR) + USB_CTRL);
-+ temp &= ~( (3 << 29) | 1 );
-+ temp |= (1 << 24) | (1 << 27) | (1 << 28);
-+ writel(temp, IO_ADDRESS(OTG_BASE_ADDR) + USB_CTRL);
++ reg = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR) + USBCTRL_OFFSET);
++ reg |= USBCTRL_WIE_BIT | USBCTRL_UIE_BIT;
++ writel(reg, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR) + USBCTRL_OFFSET);
+
+ /* Select ULPI PHY */
-+ temp = readl(IO_ADDRESS(OTG_BASE_ADDR) + UOG_PORTSC1);
-+ temp = (temp & ~PORTSC_PTS_MASK) | PORTSC_PTS_ULPI;
-+ writel(temp, IO_ADDRESS(OTG_BASE_ADDR) + UOG_PORTSC1);
++ reg = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR) + PORTSC1_OFFSET);
++ reg = (reg & ~PORTSC_PTS_MASK) | PORTSC_PTS_ULPI;
++ writel(reg, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR) + PORTSC1_OFFSET);
+ mdelay(10);
+
-+ apf27_usbotg_reset();
++ /* Reset PHY */
++ reg = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR) + USBCMD_OFFSET);
++ reg |= USBCMD_RST_BIT;
++ writel(reg, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR) + USBCMD_OFFSET);
++ mdelay(10);
++}
+
-+ if (otg_mode_host) {
-+ ret = isp1504_set_vbus_power((void __iomem *)(IO_ADDRESS(OTG_BASE_ADDR + UOG_ULPIVIEW)), 1);
-+ } else {
-+ ret = isp1504_set_device((void __iomem *)(IO_ADDRESS(OTG_BASE_ADDR + UOG_ULPIVIEW)));
-+ }
++static int apf27_otg_init(struct platform_device *pdev)
++{
++ int ret;
+
-+ if (ret)
-+ mxc_gpio_release_multiple_pins(mxc_usbotg_pins,
-+ ARRAY_SIZE(mxc_usbotg_pins));
++ ret = mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
++ apf27_usbotg_phy_init(); /* PHY is in powerdown mode by default */
+
+ return ret;
+}
-+#endif
-+
-+
-+static int otg_mode_host = 1;
-+/*
-+static int __init apf27_otg_mode(char *options)
-+{
-+ if (!strcmp(options, "host"))
-+ otg_mode_host = 1;
-+ else if (!strcmp(options, "device"))
-+ otg_mode_host = 0;
-+ else
-+ pr_info("otg_mode neither \"host\" nor \"device\". "
-+ "Defaulting to host\n");
+
-+ return 0;
-+}
-+__setup("otg_mode=", apf27_otg_mode);
-+*/
-+#if defined(CONFIG_USB_ULPI)
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
++ .init = apf27_otg_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
-+ .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
-+#endif
+
-+static struct fsl_usb2_platform_data otg_device_pdata __initconst = {
++static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
-+ .phy_mode = FSL_USB2_PHY_ULPI,
++ .phy_mode = FSL_USB2_PHY_ULPI,
+};
+
+/* APF27 frequency scaling stuff */
@@ -683,17 +622,17 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27.c
+
+MACHINE_START(APF27, "Armadeus APF27")
+ /* Maintainer: Julien Boibessot <jul...@ar...> */
-+ .boot_params = MX27_PHYS_OFFSET + 0x100,
++ .boot_params = MX27_PHYS_OFFSET + 0x100,
+ .map_io = apf27_map_io,
-+ .init_irq = mx27_init_irq,
-+ .init_machine = apf27_init,
++ .init_irq = mx27_init_irq,
++ .init_machine = apf27_init,
+ .timer = &apf27_timer,
+MACHINE_END
Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c 2011-05-18 12:18:06.000000000 +0200
-@@ -0,0 +1,935 @@
++++ linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c 2011-06-03 17:23:24.000000000 +0200
+@@ -0,0 +1,941 @@
+ /*
+ * apf27-dev.c
+ * Support for AFP27 module's development baseboard
@@ -1283,10 +1222,16 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c
+ return ret;
+}
+#endif
++
++static int apf27dev_usbh1_init(struct platform_device *pdev)
++{
++ return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
++}
++
+struct mxc_usbh_platform_data usbh1_pdata = {
-+// .init = apf27_usbh1_init,
++/* .init = apf27_usbh1_init, */
++ .init = apf27dev_usbh1_init,
+ .portsc = MXC_EHCI_MODE_SERIAL,
-+ .flags = MXC_EHCI_POWER_PINS_ENABLED,
+};
+
+
@@ -1632,7 +1577,7 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c
Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-lcd.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.38.1/arch/arm/mach-imx/apf27-lcd.c 2011-05-17 16:54:22.000000000 +0200
++++ linux-2.6.38.1/arch/arm/mach-imx/apf27-lcd.c 2011-06-03 17:23:24.000000000 +0200
@@ -0,0 +1,168 @@
+/*
+ * apf27-lcd.c
@@ -1805,7 +1750,7 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-lcd.c
Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev-ext-apw.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.38.1/arch/arm/mach-imx/apf27-dev-ext-apw.c 2011-05-17 16:54:22.000000000 +0200
++++ linux-2.6.38.1/arch/arm/mach-imx/apf27-dev-ext-apw.c 2011-06-03 17:23:24.000000000 +0200
@@ -0,0 +1,175 @@
+ /*
+ * apf27-dev-ext-apw.c
@@ -1984,8 +1929,8 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev-ext-apw.c
+
Index: linux-2.6.38.1/arch/arm/plat-mxc/include/mach/uncompress.h
===================================================================
---- linux-2.6.38.1.orig/arch/arm/plat-mxc/include/mach/uncompress.h 2011-03-23 21:04:47.000000000 +0100
-+++ linux-2.6.38.1/arch/arm/plat-mxc/include/mach/uncompress.h 2011-05-18 12:20:17.000000000 +0200
+--- linux-2.6.38.1.orig/arch/arm/plat-mxc/include/mach/uncompress.h 2011-06-03 17:23:13.000000000 +0200
++++ linux-2.6.38.1/arch/arm/plat-mxc/include/mach/uncompress.h 2011-06-03 17:42:11.000000000 +0200
@@ -83,6 +83,7 @@
case MACH_TYPE_MX21ADS:
case MACH_TYPE_PCA100:
diff --git a/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/282-apf27-armadeus-add_apf27_to_build_system.patch b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/282-apf27-armadeus-add_apf27_to_build_system.patch
index ef92ed5..b1a01db 100644
--- a/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/282-apf27-armadeus-add_apf27_to_build_system.patch
+++ b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/282-apf27-armadeus-add_apf27_to_build_system.patch
@@ -1,8 +1,8 @@
Index: linux-2.6.38.1/arch/arm/mach-imx/Kconfig
===================================================================
---- linux-2.6.38.1.orig/arch/arm/mach-imx/Kconfig 2011-05-17 22:35:01.000000000 +0200
-+++ linux-2.6.38.1/arch/arm/mach-imx/Kconfig 2011-05-18 12:18:42.000000000 +0200
-@@ -350,4 +350,116 @@
+--- linux-2.6.38.1.orig/arch/arm/mach-imx/Kconfig 2011-06-01 16:00:05.000000000 +0200
++++ linux-2.6.38.1/arch/arm/mach-imx/Kconfig 2011-06-03 12:44:42.000000000 +0200
+@@ -350,4 +350,117 @@
Include support for i-MXT (aka td60) platform. This
includes specific configurations for the module and its peripherals.
@@ -17,6 +17,7 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/Kconfig
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select IMX_HAVE_PLATFORM_MXC_PWM
++ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select MXC_ULPI if USB_ULPI
+ select SERIAL_IMX_UART1
+ help
@@ -121,8 +122,8 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/Kconfig
endif
Index: linux-2.6.38.1/arch/arm/mach-imx/Makefile
===================================================================
---- linux-2.6.38.1.orig/arch/arm/mach-imx/Makefile 2011-05-17 22:35:00.000000000 +0200
-+++ linux-2.6.38.1/arch/arm/mach-imx/Makefile 2011-05-17 22:35:11.000000000 +0200
+--- linux-2.6.38.1.orig/arch/arm/mach-imx/Makefile 2011-06-01 16:00:05.000000000 +0200
++++ linux-2.6.38.1/arch/arm/mach-imx/Makefile 2011-06-03 17:21:55.000000000 +0200
@@ -38,3 +38,7 @@
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
diff --git a/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/406-armadeus-plat-mxc-ehci-correct_some_mx5_regiter_settings_and_comments.patch b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/406-armadeus-plat-mxc-ehci-correct_some_mx5_regiter_settings_and_comments.patch
deleted file mode 100644
index dd30443..0000000
--- a/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/406-armadeus-plat-mxc-ehci-correct_some_mx5_regiter_settings_and_comments.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-Some HOST1 registers bits seem to be misused. Corresponding comments seem also
-false. Correct that.
-
-Strange that with or without this changes HOST1 seems to work the same way...
-
-Signed-off-by: Julien Boibessot <jul...@ar...>
-
-Index: linux-2.6.38-rc3/arch/arm/plat-mxc/ehci.c
-===================================================================
---- linux-2.6.38-rc3.orig/arch/arm/plat-mxc/ehci.c 2011-02-03 17:38:54.000000000 +0100
-+++ linux-2.6.38-rc3/arch/arm/plat-mxc/ehci.c 2011-02-03 17:39:20.000000000 +0100
-@@ -320,9 +320,9 @@
- }
-
- if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-- v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-+ v |= MXC_H1_UCTRL_H1PM_BIT; /* USBPWR pin used */
- else
-- v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
-+ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* USBPWR pin inactive */
- __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
-
- v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
diff --git a/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/434-pengutronix-mxc-ehci-factor_out_soc_specific_functions.patch b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/434-pengutronix-mxc-ehci-factor_out_soc_specific_functions.patch
new file mode 100644
index 0000000..abea113
--- /dev/null
+++ b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/434-pengutronix-mxc-ehci-factor_out_soc_specific_functions.patch
@@ -0,0 +1,954 @@
+From: Sascha Hauer <s....@pe...>
+Date: Mon, 3 Jan 2011 09:33:01 +0000 (+0100)
+Subject: ARM i.MX ehci: factor out soc specific functions
+X-Git-Url: http://git.pengutronix.de/?p=imx%2Flinux-2.6.git;a=commitdiff_plain;h=cb07625d1f84fb48e6849cb530762ffcc6f8e458
+
+ARM i.MX ehci: factor out soc specific functions
+
+Currently we have a mxc_initialize_usb_hw which is called on every
+i.MX SoC. This function dispatches the different SoC types, which
+is quite ugly. This patch moves the SoC specific USB initialization
+to their correspondive mach directories.
+
+Signed-off-by: Sascha Hauer <s....@pe...>
+---
+
+diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
+index 3e49ae0..b85794d 100644
+--- a/arch/arm/mach-imx/Makefile
++++ b/arch/arm/mach-imx/Makefile
+@@ -9,10 +9,10 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
+ obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
+ obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
+
+-obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o
++obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
+
+ obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
+-obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
++obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
+
+ # Support for CMOS sensor interface
+ obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
+new file mode 100644
+index 0000000..865daf0
+--- /dev/null
++++ b/arch/arm/mach-imx/ehci-imx25.c
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) 2009 Daniel Mack <da...@ca...>
++ * Copyright (C) 2010 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/io.h>
++
++#include <mach/hardware.h>
++#include <mach/mxc_ehci.h>
++
++#define USBCTRL_OTGBASE_OFFSET 0x600
++
++#define MX25_OTG_SIC_SHIFT 29
++#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
++#define MX25_OTG_PM_BIT (1 << 24)
++
++#define MX25_H1_SIC_SHIFT 21
++#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
++#define MX25_H1_PM_BIT (1 << 8)
++#define MX25_H1_IPPUE_UP_BIT (1 << 7)
++#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
++#define MX25_H1_TLL_BIT (1 << 5)
++#define MX25_H1_USBTE_BIT (1 << 4)
++
++int mx25_initialize_usb_hw(int port, unsigned int flags)
++{
++ unsigned int v;
++
++ v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
++
++ switch (port) {
++ case 0: /* OTG port */
++ v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX25_OTG_PM_BIT;
++
++ break;
++ case 1: /* H1 port */
++ v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
++ MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX25_H1_PM_BIT;
++
++ if (!(flags & MXC_EHCI_TTL_ENABLED))
++ v |= MX25_H1_TLL_BIT;
++
++ if (flags & MXC_EHCI_INTERNAL_PHY)
++ v |= MX25_H1_USBTE_BIT;
++
++ if (flags & MXC_EHCI_IPPUE_DOWN)
++ v |= MX25_H1_IPPUE_DOWN_BIT;
++
++ if (flags & MXC_EHCI_IPPUE_UP)
++ v |= MX25_H1_IPPUE_UP_BIT;
++
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
++
++ return 0;
++}
++
+diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
+new file mode 100644
+index 0000000..fa69419
+--- /dev/null
++++ b/arch/arm/mach-imx/ehci-imx27.c
+@@ -0,0 +1,82 @@
++/*
++ * Copyright (c) 2009 Daniel Mack <da...@ca...>
++ * Copyright (C) 2010 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/io.h>
++
++#include <mach/hardware.h>
++#include <mach/mxc_ehci.h>
++
++#define USBCTRL_OTGBASE_OFFSET 0x600
++
++#define MX27_OTG_SIC_SHIFT 29
++#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT)
++#define MX27_OTG_PM_BIT (1 << 24)
++
++#define MX27_H2_SIC_SHIFT 21
++#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT)
++#define MX27_H2_PM_BIT (1 << 16)
++#define MX27_H2_DT_BIT (1 << 5)
++
++#define MX27_H1_SIC_SHIFT 13
++#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT)
++#define MX27_H1_PM_BIT (1 << 8)
++#define MX27_H1_DT_BIT (1 << 4)
++
++int mx27_initialize_usb_hw(int port, unsigned int flags)
++{
++ unsigned int v;
++
++ v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
++
++ switch (port) {
++ case 0: /* OTG port */
++ v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX27_OTG_PM_BIT;
++ break;
++ case 1: /* H1 port */
++ v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX27_H1_PM_BIT;
++
++ if (!(flags & MXC_EHCI_TTL_ENABLED))
++ v |= MX27_H1_DT_BIT;
++
++ break;
++ case 2: /* H2 port */
++ v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX27_H2_PM_BIT;
++
++ if (!(flags & MXC_EHCI_TTL_ENABLED))
++ v |= MX27_H2_DT_BIT;
++
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
++
++ return 0;
++}
++
+diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
+index bc7294f..224d07a 100644
+--- a/arch/arm/mach-mx3/Makefile
++++ b/arch/arm/mach-mx3/Makefile
+@@ -5,8 +5,8 @@
+ # Object file lists.
+
+ obj-y := mm.o devices.o cpu.o
+-obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o
+-obj-$(CONFIG_SOC_IMX35) += clock-imx35.o
++obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o
++obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o
+ obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
+ obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
+ obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
+diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-mx3/ehci-imx31.c
+new file mode 100644
+index 0000000..314a983
+--- /dev/null
++++ b/arch/arm/mach-mx3/ehci-imx31.c
+@@ -0,0 +1,83 @@
++/*
++ * Copyright (c) 2009 Daniel Mack <da...@ca...>
++ * Copyright (C) 2010 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/io.h>
++
++#include <mach/hardware.h>
++#include <mach/mxc_ehci.h>
++
++#define USBCTRL_OTGBASE_OFFSET 0x600
++
++#define MX31_OTG_SIC_SHIFT 29
++#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
++#define MX31_OTG_PM_BIT (1 << 24)
++
++#define MX31_H2_SIC_SHIFT 21
++#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
++#define MX31_H2_PM_BIT (1 << 16)
++#define MX31_H2_DT_BIT (1 << 5)
++
++#define MX31_H1_SIC_SHIFT 13
++#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
++#define MX31_H1_PM_BIT (1 << 8)
++#define MX31_H1_DT_BIT (1 << 4)
++
++int mx31_initialize_usb_hw(int port, unsigned int flags)
++{
++ unsigned int v;
++
++ v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
++
++ switch (port) {
++ case 0: /* OTG port */
++ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX31_OTG_PM_BIT;
++
++ break;
++ case 1: /* H1 port */
++ v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX31_H1_PM_BIT;
++
++ if (!(flags & MXC_EHCI_TTL_ENABLED))
++ v |= MX31_H1_DT_BIT;
++
++ break;
++ case 2: /* H2 port */
++ v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX31_H2_PM_BIT;
++
++ if (!(flags & MXC_EHCI_TTL_ENABLED))
++ v |= MX31_H2_DT_BIT;
++
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
++
++ return 0;
++}
++
+diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-mx3/ehci-imx35.c
+new file mode 100644
+index 0000000..33983a4
+--- /dev/null
++++ b/arch/arm/mach-mx3/ehci-imx35.c
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) 2009 Daniel Mack <da...@ca...>
++ * Copyright (C) 2010 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/io.h>
++
++#include <mach/hardware.h>
++#include <mach/mxc_ehci.h>
++
++#define USBCTRL_OTGBASE_OFFSET 0x600
++
++#define MX35_OTG_SIC_SHIFT 29
++#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
++#define MX35_OTG_PM_BIT (1 << 24)
++
++#define MX35_H1_SIC_SHIFT 21
++#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
++#define MX35_H1_PM_BIT (1 << 8)
++#define MX35_H1_IPPUE_UP_BIT (1 << 7)
++#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
++#define MX35_H1_TLL_BIT (1 << 5)
++#define MX35_H1_USBTE_BIT (1 << 4)
++
++int mx35_initialize_usb_hw(int port, unsigned int flags)
++{
++ unsigned int v;
++
++ v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
++
++ switch (port) {
++ case 0: /* OTG port */
++ v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX35_OTG_PM_BIT;
++
++ break;
++ case 1: /* H1 port */
++ v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
++ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
++ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
++
++ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
++ v |= MX35_H1_PM_BIT;
++
++ if (!(flags & MXC_EHCI_TTL_ENABLED))
++ v |= MX35_H1_TLL_BIT;
++
++ if (flags & MXC_EHCI_INTERNAL_PHY)
++ v |= MX35_H1_USBTE_BIT;
++
++ if (flags & MXC_EHCI_IPPUE_DOWN)
++ v |= MX35_H1_IPPUE_DOWN_BIT;
++
++ if (flags & MXC_EHCI_IPPUE_UP)
++ v |= MX35_H1_IPPUE_UP_BIT;
++
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
++
++ return 0;
++}
++
+diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
+index 0d43be9..dc27288 100644
+--- a/arch/arm/mach-mx5/Makefile
++++ b/arch/arm/mach-mx5/Makefile
+@@ -3,7 +3,7 @@
+ #
+
+ # Object file lists.
+-obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o
++obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o
+ obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
+
+ obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
+diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
+new file mode 100644
+index 0000000..7ce12c8
+--- /dev/null
++++ b/arch/arm/mach-mx5/ehci.c
+@@ -0,0 +1,156 @@
++/*
++ * Copyright (c) 2009 Daniel Mack <da...@ca...>
++ * Copyright (C) 2010 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/io.h>
++
++#include <mach/hardware.h>
++#include <mach/mxc_ehci.h>
++
++#define MXC_OTG_OFFSET 0
++#define MXC_H1_OFFSET 0x200
++#define MXC_H2_OFFSET 0x400
++
++/* USB_CTRL */
++#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
++#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
++#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
++#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
++#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
++
++/* USB_PHY_CTRL_FUNC */
++#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
++#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
++
++/* USBH2CTRL */
++#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
++#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
++#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
++
++#define MXC_USBCMD_OFFSET 0x140
++
++/* USBCMD */
++#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
++
++int mx51_initialize_usb_hw(int port, unsigned int flags)
++{
++ unsigned int v;
++ void __iomem *usb_base;
++ void __iomem *usbotg_base;
++ void __iomem *usbother_base;
++ int ret = 0;
++
++ usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
++ if (!usb_base) {
++ printk(KERN_ERR "%s(): ioremap failed\n", __func__);
++ return -ENOMEM;
++ }
++
++ switch (port) {
++ case 0: /* OTG port */
++ usbotg_base = usb_base + MXC_OTG_OFFSET;
++ break;
++ case 1: /* Host 1 port */
++ usbotg_base = usb_base + MXC_H1_OFFSET;
++ break;
++ case 2: /* Host 2 port */
++ usbotg_base = usb_base + MXC_H2_OFFSET;
++ break;
++ default:
++ printk(KERN_ERR"%s no such port %d\n", __func__, port);
++ ret = -ENOENT;
++ goto error;
++ }
++ usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
++
++ switch (port) {
++ case 0: /*OTG port */
++ if (flags & MXC_EHCI_INTERNAL_PHY) {
++ v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
++
++ if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
++ /* OC/USBPWR is not used */
++ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
++ } else {
++ /* OC/USBPWR is used */
++ v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
++ }
++ __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
++
++ v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
++ if (flags & MXC_EHCI_WAKEUP_ENABLED)
++ v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
++ else
++ v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
++ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
++ v |= MXC_OTG_UCTRL_OPM_BIT;
++ else
++ v &= ~MXC_OTG_UCTRL_OPM_BIT;
++ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
++ }
++ break;
++ case 1: /* Host 1 */
++ /*Host ULPI */
++ v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
++ if (flags & MXC_EHCI_WAKEUP_ENABLED) {
++ /* HOST1 wakeup/ULPI intr enable */
++ v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
++ } else {
++ /* HOST1 wakeup/ULPI intr disable */
++ v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
++ }
++
++ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
++ v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
++ else
++ v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
++ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
++
++ v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
++ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
++ v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
++ else
++ v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
++ __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
++
++ v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
++ if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
++ /* Interrupt Threshold Control:Immediate (no threshold) */
++ v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
++ __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
++ break;
++ case 2: /* Host 2 ULPI */
++ v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
++ if (flags & MXC_EHCI_WAKEUP_ENABLED) {
++ /* HOST1 wakeup/ULPI intr enable */
++ v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
++ } else {
++ /* HOST1 wakeup/ULPI intr disable */
++ v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
++ }
++
++ if (flags & MXC_EHCI_POWER_PINS_ENABLED)
++ v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
++ else
++ v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
++ __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
++ break;
++ }
++
++error:
++ iounmap(usb_base);
++ return ret;
++}
++
+diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
+index 8772ce3..06fb3a4 100644
+--- a/arch/arm/plat-mxc/ehci.c
++++ b/arch/arm/plat-mxc/ehci.c
+@@ -14,352 +14,29 @@
+ */
+
+ #include <linux/platform_device.h>
+-#include <linux/io.h>
+
+ #include <mach/hardware.h>
+ #include <mach/mxc_ehci.h>
+
+-#define USBCTRL_OTGBASE_OFFSET 0x600
+-
+-#define MX31_OTG_SIC_SHIFT 29
+-#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
+-#define MX31_OTG_PM_BIT (1 << 24)
+-
+-#define MX31_H2_SIC_SHIFT 21
+-#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
+-#define MX31_H2_PM_BIT (1 << 16)
+-#define MX31_H2_DT_BIT (1 << 5)
+-
+-#define MX31_H1_SIC_SHIFT 13
+-#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
+-#define MX31_H1_PM_BIT (1 << 8)
+-#define MX31_H1_DT_BIT (1 << 4)
+-
+-#define MX35_OTG_SIC_SHIFT 29
+-#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
+-#define MX35_OTG_PM_BIT (1 << 24)
+-
+-#define MX35_H1_SIC_SHIFT 21
+-#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
+-#define MX35_H1_PM_BIT (1 << 8)
+-#define MX35_H1_IPPUE_UP_BIT (1 << 7)
+-#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
+-#define MX35_H1_TLL_BIT (1 << 5)
+-#define MX35_H1_USBTE_BIT (1 << 4)
+-
+-#define MXC_OTG_OFFSET 0
+-#define MXC_H1_OFFSET 0x200
+-#define MXC_H2_OFFSET 0x400
+-
+-/* USB_CTRL */
+-#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
+-#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
+-#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
+-#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
+-#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
+-
+-/* USB_PHY_CTRL_FUNC */
+-#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
+-#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
+-
+-/* USBH2CTRL */
+-#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
+-#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
+-#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
+-
+-#define MXC_USBCMD_OFFSET 0x140
+-
+-/* USBCMD */
+-#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
+-
+ int mxc_initialize_usb_hw(int port, unsigned int flags)
+ {
+- unsigned int v;
+ #if defined(CONFIG_SOC_IMX25)
+- if (cpu_is_mx25()) {
+- v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
+- USBCTRL_OTGBASE_OFFSET));
+-
+- switch (port) {
+- case 0: /* OTG port */
+- v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX35_OTG_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX35_OTG_PM_BIT;
+-
+- break;
+- case 1: /* H1 port */
+- v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+- MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX35_H1_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX35_H1_PM_BIT;
+-
+- if (!(flags & MXC_EHCI_TTL_ENABLED))
+- v |= MX35_H1_TLL_BIT;
+-
+- if (flags & MXC_EHCI_INTERNAL_PHY)
+- v |= MX35_H1_USBTE_BIT;
+-
+- if (flags & MXC_EHCI_IPPUE_DOWN)
+- v |= MX35_H1_IPPUE_DOWN_BIT;
+-
+- if (flags & MXC_EHCI_IPPUE_UP)
+- v |= MX35_H1_IPPUE_UP_BIT;
+-
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
+- USBCTRL_OTGBASE_OFFSET));
+- return 0;
+- }
++ if (cpu_is_mx25())
++ return mx25_initialize_usb_hw(port, flags);
+ #endif /* if defined(CONFIG_SOC_IMX25) */
+ #if defined(CONFIG_ARCH_MX3)
+- if (cpu_is_mx31()) {
+- v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
+- USBCTRL_OTGBASE_OFFSET));
+-
+- switch (port) {
+- case 0: /* OTG port */
+- v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX31_OTG_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX31_OTG_PM_BIT;
+-
+- break;
+- case 1: /* H1 port */
+- v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX31_H1_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX31_H1_PM_BIT;
+-
+- if (!(flags & MXC_EHCI_TTL_ENABLED))
+- v |= MX31_H1_DT_BIT;
+-
+- break;
+- case 2: /* H2 port */
+- v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX31_H2_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX31_H2_PM_BIT;
+-
+- if (!(flags & MXC_EHCI_TTL_ENABLED))
+- v |= MX31_H2_DT_BIT;
+-
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
+- USBCTRL_OTGBASE_OFFSET));
+- return 0;
+- }
+-
+- if (cpu_is_mx35()) {
+- v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
+- USBCTRL_OTGBASE_OFFSET));
+-
+- switch (port) {
+- case 0: /* OTG port */
+- v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX35_OTG_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX35_OTG_PM_BIT;
+-
+- break;
+- case 1: /* H1 port */
+- v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+- MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX35_H1_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX35_H1_PM_BIT;
+-
+- if (!(flags & MXC_EHCI_TTL_ENABLED))
+- v |= MX35_H1_TLL_BIT;
+-
+- if (flags & MXC_EHCI_INTERNAL_PHY)
+- v |= MX35_H1_USBTE_BIT;
+-
+- if (flags & MXC_EHCI_IPPUE_DOWN)
+- v |= MX35_H1_IPPUE_DOWN_BIT;
+-
+- if (flags & MXC_EHCI_IPPUE_UP)
+- v |= MX35_H1_IPPUE_UP_BIT;
+-
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
+- USBCTRL_OTGBASE_OFFSET));
+- return 0;
+- }
++ if (cpu_is_mx31())
++ return mx31_initialize_usb_hw(port, flags);
++ if (cpu_is_mx35())
++ return mx35_initialize_usb_hw(port, flags);
+ #endif /* CONFIG_ARCH_MX3 */
+ #ifdef CONFIG_MACH_MX27
+- if (cpu_is_mx27()) {
+- /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
+- * are identical
+- */
+- v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
+- USBCTRL_OTGBASE_OFFSET));
+- switch (port) {
+- case 0: /* OTG port */
+- v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX31_OTG_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX31_OTG_PM_BIT;
+- break;
+- case 1: /* H1 port */
+- v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX31_H1_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX31_H1_PM_BIT;
+-
+- if (!(flags & MXC_EHCI_TTL_ENABLED))
+- v |= MX31_H1_DT_BIT;
+-
+- break;
+- case 2: /* H2 port */
+- v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+- v |= (flags & MXC_EHCI_INTERFACE_MASK)
+- << MX31_H2_SIC_SHIFT;
+- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+- v |= MX31_H2_PM_BIT;
+-
+- if (!(flags & MXC_EHCI_TTL_ENABLED))
+- v |= MX31_H2_DT_BIT;
+-
+- break;
+- default:
+- return -EINVAL;
+- }
+- writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
+- USBCTRL_OTGBASE_OFFSET));
+- return 0;
+- }
++ if (cpu_is_mx27())
++ return mx27_initialize_usb_hw(port, flags);
+ #endif /* CONFIG_MACH_MX27 */
+ #ifdef CONFIG_SOC_IMX51
+- if (cpu_is_mx51()) {
+- void __iomem *usb_base;
+- void __iomem *usbotg_base;
+- void __iomem *usbother_base;
+- int ret = 0;
+-
+- usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+- if (!usb_base) {
+- printk(KERN_ERR "%s(): ioremap failed\n", __func__);
+- return -ENOMEM;
+- }
+-
+- switch (port) {
+- case 0: /* OTG port */
+- usbotg_base = usb_base + MXC_OTG_OFFSET;
+- break;
+- case 1: /* Host 1 port */
+- usbotg_base = usb_base + MXC_H1_OFFSET;
+- break;
+- case 2: /* Host 2 port */
+- usbotg_base = usb_base + MXC_H2_OFFSET;
+- break;
+- default:
+- printk(KERN_ERR"%s no such port %d\n", __func__, port);
+- ret = -ENOENT;
+- goto error;
+- }
+- usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+-
+- switch (port) {
+- case 0: /*OTG port */
+- if (flags & MXC_EHCI_INTERNAL_PHY) {
+- v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+-
+- if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
+- /* OC/USBPWR is not used */
+- v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+- } else {
+- /* OC/USBPWR is used */
+- v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+- }
+- __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+-
+- v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+- if (flags & MXC_EHCI_WAKEUP_ENABLED)
+- v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
+- else
+- v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
+- if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+- v |= MXC_OTG_UCTRL_OPM_BIT;
+- else
+- v &= ~MXC_OTG_UCTRL_OPM_BIT;
+- __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+- }
+- break;
+- case 1: /* Host 1 */
+- /*Host ULPI */
+- v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+- if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+- /* HOST1 wakeup/ULPI intr enable */
+- v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+- } else {
+- /* HOST1 wakeup/ULPI intr disable */
+- v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+- }
+-
+- if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+- v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+- else
+- v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+- __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+-
+- v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+- if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+- v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
+- else
+- v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
+- __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+-
+- v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
+- if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
+- /* Interrupt Threshold Control:Immediate (no threshold) */
+- v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
+- __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
+- break;
+- case 2: /* Host 2 ULPI */
+- v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+- if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+- /* HOST1 wakeup/ULPI intr enable */
+- v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+- } else {
+- /* HOST1 wakeup/ULPI intr disable */
+- v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+- }
+-
+- if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+- v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+- else
+- v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+- __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+- break;
+- }
+-
+-error:
+- iounmap(usb_base);
+- return ret;
+- }
++ if (cpu_is_mx51())
++ return mx51_initialize_usb_hw(port, flags);
+ #endif
+ printk(KERN_WARNING
+ "%s() unable to setup USBCONTROL for this CPU\n", __func__);
+diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+index a523a40..7e555a1 100644
+--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
++++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+@@ -50,5 +50,11 @@ struct mxc_usbh_platform_data {
+
+ int mxc_initialize_usb_hw(int port, unsigned int flags);
+
++int mx51_initialize_usb_hw(int port, unsigned int flags);
++int mx25_initialize_usb_hw(int port, unsigned int flags);
++int mx31_initialize_usb_hw(int port, unsigned int flags);
++int mx35_initialize_usb_hw(int port, unsigned int flags);
++int mx27_initialize_usb_hw(int port, unsigned int flags);
++
+ #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
+
diff --git a/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/435-pengutronix-mxc-ehci-do_ehci_init_in_board_specific_functions.patch b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/435-pengutronix-mxc-ehci-do_ehci_init_in_board_specific_functions.patch
new file mode 100644
index 0000000..b92b656
--- /dev/null
+++ b/buildroot/target/device/armadeus/linux/kernel-patches/2.6.38/435-pengutronix-mxc-ehci-do_ehci_init_in_board_specific_functions.patch
@@ -0,0 +1,793 @@
+From: Sascha Hauer <s....@pe...>
+Date: Mon, 3 Jan 2011 10:30:28 +0000 (+0100)
+Subject: ARM i.MX ehci: do ehci init in board specific functions
+X-Git-Url: http://git.pengutronix.de/?p=imx%2Flinux-2.6.git;a=commitdiff_plain;h=4bd597b633ae630e09d58957bd99870eac35fcb4
+
+ARM i.MX ehci: do ehci init in board specific functions
+
+The mxc-ehci driver calls SoC specific phy initialization right after
+calling board specific initialization. To offer greater flexibility for
+boards to setup the phy and to get rid of some unnecessary flags in
+platform data this patch lets the boards call the SoC specific phy
+initialization and remove it from the driver.
+
+Signed-off-by: Sascha Hauer <s....@pe...>
+---
+
+diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
+index cabb800..6b724c2 100644
+--- a/arch/arm/mach-imx/mach-cpuimx27.c
++++ b/arch/arm/mach-imx/mach-cpuimx27.c
+@@ -210,14 +210,24 @@ static struct platform_device serial_device = {
+ #endif
+
+ #if defined(CONFIG_USB_ULPI)
++static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
++{
++ return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
++}
++
+ static struct mxc_usbh_platform_data otg_pdata __initdata = {
++ .init = eukrea_cpuimx27_otg_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+
++static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
++{
++ return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
++}
++
+ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
++ .init = eukrea_cpuimx27_usbh2_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+ #endif
+
+diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+index 439167d..9da8d18 100644
+--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
++++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+@@ -84,15 +84,25 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
+ },
+ };
+
++static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
++{
++ return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
++}
++
+ static const struct mxc_usbh_platform_data otg_pdata __initconst = {
++ .init = eukrea_cpuimx25_otg_init,
+ .portsc = MXC_EHCI_MODE_UTMI,
+- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+
++static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
++{
++ return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
++ MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
++}
++
+ static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
++ .init = eukrea_cpuimx25_usbh2_init,
+ .portsc = MXC_EHCI_MODE_SERIAL,
+- .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+- MXC_EHCI_IPPUE_DOWN,
+ };
+
+ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+index 494723b..ffff2d0 100644
+--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
++++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+@@ -30,6 +30,7 @@
+ #include <linux/gpio_keys.h>
+ #include <linux/input.h>
+ #include <linux/gpio.h>
++#include <linux/delay.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/time.h>
+@@ -210,14 +211,16 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
+ static int otg_phy_init(struct platform_device *pdev)
+ {
+ gpio_set_value(OTG_PHY_CS_GPIO, 0);
+- return 0;
++
++ mdelay(10);
++
++ return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+ }
+
+ static const struct mxc_usbh_platform_data
+ visstrim_m10_usbotg_pdata __initconst = {
+ .init = otg_phy_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+- .flags = MXC_EHCI_POWER_PINS_ENABLED,
+ };
+
+ static void __init visstrim_m10_board_init(void)
+diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
+index cd18a0c..aafc6f7 100644
+--- a/arch/arm/mach-imx/mach-mx25_3ds.c
++++ b/arch/arm/mach-imx/mach-mx25_3ds.c
+@@ -185,9 +185,14 @@ static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
+ .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
+ };
+
++static int mx25pdk_usbh2_init(struct platform_device *pdev)
++{
++ return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
++}
++
+ static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
++ .init = mx25pdk_usbh2_init,
+ .portsc = MXC_EHCI_MODE_SERIAL,
+- .flags = MXC_EHCI_INTERNAL_PHY,
+ };
+
+ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
+index 4e0e225..ba88417 100644
+--- a/arch/arm/mach-imx/mach-mx27_3ds.c
++++ b/arch/arm/mach-imx/mach-mx27_3ds.c
+@@ -160,10 +160,14 @@ static int otg_phy_init(void)
+ }
+
+ #if defined(CONFIG_USB_ULPI)
++static int mx27_3ds_otg_init(struct platform_device *pdev)
++{
++ return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
++}
+
+ static struct mxc_usbh_platform_data otg_pdata __initdata = {
++ .init = mx27_3ds_otg_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+ #endif
+
+diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
+index 3514178..f754bab 100644
+--- a/arch/arm/mach-imx/mach-pca100.c
++++ b/arch/arm/mach-imx/mach-pca100.c
+@@ -271,25 +271,29 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
+ static int otg_phy_init(struct platform_device *pdev)
+ {
+ gpio_set_value(OTG_PHY_CS_GPIO, 0);
+- return 0;
++
++ mdelay(10);
++
++ return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+ }
+
+ static struct mxc_usbh_platform_data otg_pdata __initdata = {
+ .init = otg_phy_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+
+ static int usbh2_phy_init(struct platform_device *pdev)
+ {
+ gpio_set_value(USBH2_PHY_CS_GPIO, 0);
+- return 0;
++
++ mdelay(10);
++
++ return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+ }
+
+ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = usbh2_phy_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+ #endif
+
+diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
+index 9656ef3..38c7708 100644
+--- a/arch/arm/mach-imx/mach-pcm038.c
++++ b/arch/arm/mach-imx/mach-pcm038.c
+@@ -281,9 +281,15 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
+ }
+ };
+
++static int pcm038_usbh2_init(struct platform_device *pdev)
++{
++ return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
++ MXC_EHCI_INTERFACE_DIFF_UNI);
++}
++
+ static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
++ .init = pcm038_usbh2_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+- .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+
+ static void __init pcm038_init(void)
+diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
+index 835e2a0..34e619e 100644
+--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
++++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
+@@ -176,8 +176,10 @@ static int usbotg_init(struct platform_device *pdev)
+ gpio_set_value(OTG_RESET, 0/*LOW*/);
+ mdelay(5);
+ gpio_set_value(OTG_RESET, 1/*HIGH*/);
++ mdelay(10);
+
+- return 0;
++ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
++ MXC_EHCI_INTERFACE_DIFF_UNI);
+
+ otg_free_reset:
+ gpio_free(OTG_RESET);
+@@ -233,8 +235,10 @@ static int usbh2_init(struct platform_device *pdev)
+ gpio_set_value(USBH2_RESET, 0/*LOW*/);
+ mdelay(5);
+ gpio_set_value(USBH2_RESET, 1/*HIGH*/);
++ mdelay(10);
+
+- return 0;
++ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
++ MXC_EHCI_INTERFACE_DIFF_UNI);
+
+ h2_free_reset:
+ gpio_free(USBH2_RESET);
+@@ -246,13 +250,11 @@ h2_free_cs:
+ static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
+ .init = usbotg_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+- .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+
+ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = usbh2_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+- .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+ #endif /* CONFIG_USB_ULPI */
+
+diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
+index 3eedf0f..0f23056 100644
+--- a/arch/arm/mach-mx3/mach-cpuimx35.c
++++ b/arch/arm/mach-mx3/mach-cpuimx35.c
+@@ -111,15 +111,25 @@ static const struct mxc_nand_platform_data
+ .flash_bbt = 1,
+ };
+
++static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
++{
++ return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
++}
++
+ static const struct mxc_usbh_platform_data otg_pdata __initconst = {
++ .init = eukrea_cpuimx35_otg_init,
+ .portsc = MXC_EHCI_MODE_UTMI,
+- .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
+ };
+
++static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
++{
++ return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
++ MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
++}
++
+ static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
++ .init = eukrea_cpuimx35_usbh1_init,
+ .portsc = MXC_EHCI_MODE_SERIAL,
+- .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+- MXC_EHCI_IPPUE_DOWN,
+ };
+
+ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
+index 1c3f491..be79a0d 100644
+--- a/arch/arm/mach-mx3/mach-mx31lilly.c
++++ b/arch/arm/mach-mx3/mach-mx31lilly.c
+@@ -24,6 +24,7 @@
+ #include <linux/init.h>
+ #include <linux/clk.h>
+ #include <linux/gpio.h>
++#include <linux/delay.h>
+ #include <linux/platform_device.h>
+ #include <linux/interrupt.h>
+ #include <linux/smsc911x.h>
+@@ -156,7 +157,9 @@ static int usbotg_init(struct platform_device *pdev)
+ gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
+ gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
+
+- return 0;
++ mdelay(10);
++
++ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+ }
+
+ static int usbh1_init(struct platform_device *pdev)
+@@ -183,7 +186,10 @@ static int usbh1_init(struct platform_device *pdev)
+
+ mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+
+- return 0;
++ mdelay(10);
++
++ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
++ MXC_EHCI_INTERFACE_SINGLE_UNI);
+ }
+
+ static int usbh2_init(struct platform_device *pdev)
+@@ -220,25 +226,24 @@ static int usbh2_init(struct platform_device *pdev)
+ gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
+ gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
+
+- return 0;
++ mdelay(10);
++
++ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+ }
+
+ static struct mxc_usbh_platform_data usbotg_pdata = {
+ .init = usbotg_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+- .flags = MXC_EHCI_POWER_PINS_ENABLED,
+ };
+
+ static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
+ .init = usbh1_init,
+ .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+- .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
+ };
+
+ static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = usbh2_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+- .flags = MXC_EHCI_POWER_PINS_ENABLED,
+ };
+
+ sta...
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