[Armadeus-commitlog] armadeus branch, master, updated. release-3.4-123-ga37bbee

[Nicolas <th...@us...>]

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- Log -----------------------------------------------------------------
commit a37bbee0f20ee304c24ad2c7c3a61e43313a99f3
Author: Nicolas Colombain <nic...@ar...>
Date:   Tue May 10 11:16:15 2011 +0200

    [U-BOOT] APF51 fix erratic fpga load

-----------------------------------------------------------------------

Summary of changes:
 .../target/u-boot/u-boot-2010.03-401-apf51.patch   |   23 ++++++++++---------
 1 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/buildroot/target/u-boot/u-boot-2010.03-401-apf51.patch b/buildroot/target/u-boot/u-boot-2010.03-401-apf51.patch
index b72597d..14172fe 100644
--- a/buildroot/target/u-boot/u-boot-2010.03-401-apf51.patch
+++ b/buildroot/target/u-boot/u-boot-2010.03-401-apf51.patch
@@ -1390,7 +1390,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ u-boot-2010.03/board/armadeus/apf51/fpga.c	2011-01-05 18:11:15.000000000 +0100
-@@ -0,0 +1,270 @@
+@@ -0,0 +1,271 @@
 +/*
 + * (C) Copyright 2002-2010
 + * Nicolas Colombain <nic...@ar...>
@@ -1480,26 +1480,20 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
 +{
 +#define EMI_CLK_SEL		1<<26
 +
-+	/* change emi_clk_sel to ensure blck smaller than 50MHz */
-+	temp_clk = __REG(CCM_BASE_ADDR + CLKCTL_CBCDR);
-+	__REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk | EMI_CLK_SEL;
-+
 +	temp_rcr1 = __REG(CONFIG_CS1RCR1_ADDR);
 +	__REG(CONFIG_CS1RCR1_ADDR) = 0x01000010;
 +
 +	temp_wcr1 = __REG(CONFIG_CS1WCR1_ADDR);
 +	__REG(CONFIG_CS1WCR1_ADDR) = 0x01000008;
 +
++	/* change emi_clk_sel to ensure blck smaller than 50MHz */
++	temp_clk = __REG(CCM_BASE_ADDR + CLKCTL_CBCDR);
++	__REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk | EMI_CLK_SEL;
++
 +	/* FPGA PROG */
 +	imx_gpio_pin_set(CONFIG_SYS_FPGA_PRG, 1);
 +	imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_PRG, 1);
 +
-+	/* FPGA PWR */
-+	imx_gpio_pin_set(CONFIG_SYS_FPGA_PWR, 1);
-+	imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_PWR, 1);
-+
-+	printf("Enable fpga power\n");
-+
 +	/* FPGA SUSPEND */
 +	imx_gpio_pin_set(CONFIG_SYS_FPGA_SUSPEND, 1);
 +	imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_SUSPEND, 1);
@@ -1510,6 +1504,12 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
 +	/* FPGA INIT# */
 +	imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_INIT, 0);
 +
++	/* FPGA PWR */
++	imx_gpio_pin_set(CONFIG_SYS_FPGA_PWR, 1);
++	imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_PWR, 1);
++
++	printf("Enable fpga power\n");
++
 +	return cookie;
 +}
 +
@@ -1627,6 +1627,7 @@ Index: u-boot-2010.03/board/armadeus/apf51/fpga.c
 +	PRINTF ("%s:%d: FPGA POST \n", __FUNCTION__, __LINE__);
 +	/* restore emi_clk_sel */
 +	__REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk;
++	udelay(10); /* wait a few us after emi_clk_sel change */
 +	__REG(CONFIG_CS1RCR1_ADDR) = temp_rcr1;
 +	__REG(CONFIG_CS1WCR1_ADDR) = temp_wcr1;
 +	return cookie;


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