[Armadeus-commitlog] armadeus branch, master, updated. release-3.4-20-g5fbad6a

[Fabien M <fa...@us...>]

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- Log -----------------------------------------------------------------
commit 5fbad6a21aeba8c9e3e652f24d0a0970557ece61
Author: Fabien Marteau <fab...@ar...>
Date:   Mon Mar 28 11:25:15 2011 +0200

    [u-boot] WEIM clock at 95MHz and 4 wait states for read/write

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf51/apf51-u-boot-2010.03.h   |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
index dc10f3a..ad62869 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
@@ -371,7 +371,7 @@
 #define CONFIG_ARM_CLK_FREQ	800	/* MHZ CPU frequency from PLL1*/
 #define CONFIG_AXIA_CLK_FREQ	166	/* MHZ AXI A frequency from PLL2*/
 #define CONFIG_AXIB_CLK_FREQ	110	/* 110.8 133 MHZ AXI B frequency from PLL2*/
-#define CONFIG_EMI_CLK_FREQ	83	/* MHZ AHB frequency from PLL2*/
+#define CONFIG_EMI_CLK_FREQ	95	/* MHZ AHB frequency from PLL2*/
 #define CONFIG_AHB_CLK_FREQ	133	/* MHZ AHB frequency from PLL2*/
 #define CONFIG_IPG_CLK_FREQ	66	/* 66.5 MHZ IPG frequency from PLL2*/
 #define CONFIG_PERCLK_FREQ	55	/* 55.4 MHZ PERCLK frequency */
@@ -597,7 +597,7 @@
 #define	CONFIG_FPGA_RCR1_VALUE	0x04000010
 #define	CONFIG_FPGA_RCR2_VALUE	0x00000000
                                            
-#define	CONFIG_FPGA_WCR1_VALUE	0x03000008
+#define	CONFIG_FPGA_WCR1_VALUE	0x04000008
 #define	CONFIG_FPGA_WCR2_VALUE	0x00000000
 
 


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