[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-277-ga040ebf
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[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-277-ga040ebf
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From: jorasse <jo...@us...> - 2011-02-03 23:46:18
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This is an automated email from the git hooks/post-receive script. It was
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the project "armadeus".
The branch, master has been updated
via a040ebfe4a8727d12244c1acbe94ad4a6a80e93b (commit)
via 14ae256decfe5ea48b8e92e2185801858f79ac9a (commit)
from 8b31f3229f7789295dbb874f39f06846eebea069 (commit)
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- Log -----------------------------------------------------------------
commit a040ebfe4a8727d12244c1acbe94ad4a6a80e93b
Merge: 14ae256decfe5ea48b8e92e2185801858f79ac9a 8b31f3229f7789295dbb874f39f06846eebea069
Author: Eric Jarrige <eri...@ar...>
Date: Fri Feb 4 00:53:55 2011 +0100
Merge branch 'master' of ssh://jorasse@armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit 14ae256decfe5ea48b8e92e2185801858f79ac9a
Author: Eric Jarrige <eri...@ar...>
Date: Fri Feb 4 00:49:43 2011 +0100
[UBOOT] Set NAND and SD outputs to high voltage
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf51/apf51-u-boot-2010.03.h | 22 +++---
...boot-2010.03-411-Fix-high-voltage-nand-sd.patch | 93 ++++++++++++++++++++
2 files changed, 104 insertions(+), 11 deletions(-)
create mode 100644 buildroot/target/u-boot/u-boot-2010.03-411-Fix-high-voltage-nand-sd.patch
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
index f694e6b..dc10f3a 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
@@ -891,12 +891,12 @@
#define CONFIG_IOMUX_PAD_DRAM_DQM3 PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU \
+PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
-#define CONFIG_IOMUX_PAD_EIM_SDBA2 PAD_CTL_DRV_VOT_HIGH+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PU /* imx default */
-#define CONFIG_IOMUX_PAD_EIM_SDODT1 PAD_CTL_DRV_VOT_HIGH+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST /* imx default */
-#define CONFIG_IOMUX_PAD_EIM_SDODT0 PAD_CTL_DRV_VOT_HIGH+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
- +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST /* imx default */
+#define CONFIG_IOMUX_PAD_EIM_SDBA2 PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+ +PAD_CTL_100K_PU
+#define CONFIG_IOMUX_PAD_EIM_SDODT1 PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+ +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST
+#define CONFIG_IOMUX_PAD_EIM_SDODT0 PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+ +PAD_CTL_100K_PD+PAD_CTL_DRV_LOW+PAD_CTL_SRE_FAST
#define CONFIG_IOMUX_GRP_DDRPKS PAD_CTL_PUE_PULL /* imx default */
#define CONFIG_IOMUX_GRP_DRAM_B4 PAD_CTL_DRV_HIGH /* imx default */
@@ -908,7 +908,7 @@
#define CONFIG_IOMUX_GRP_HYSDDR0 PAD_CTL_HYS_NONE /* imx default */
#define CONFIG_IOMUX_GRP_HYSDDR1 PAD_CTL_HYS_NONE /* imx default */
#define CONFIG_IOMUX_GRP_HYSDDR2 PAD_CTL_HYS_NONE /* imx default */
-#define CONFIG_IOMUX_GRP_HVDDR PAD_CTL_DRV_VOT_HIGH /* imx default */
+#define CONFIG_IOMUX_GRP_HVDDR PAD_CTL_DRV_VOT_LOW
#define CONFIG_IOMUX_GRP_HYSDDR3 PAD_CTL_HYS_NONE /* imx default */
#define CONFIG_IOMUX_GRP_DRAM_SR_B0 PAD_CTL_SRE_SLOW
#define CONFIG_IOMUX_GRP_DDRAPKS PAD_CTL_PUE_PULL /* imx default */
@@ -989,10 +989,10 @@
#define CONFIG_IOMUX_PAD_DRAM_DQM2 PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU+PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
#define CONFIG_IOMUX_PAD_DRAM_DQM3 PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU+PAD_CTL_DRV_HIGH+PAD_CTL_SRE_SLOW
-#define CONFIG_IOMUX_PAD_EIM_SDBA2 PAD_CTL_DRV_VOT_HIGH+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU /* imx default */
-#define CONFIG_IOMUX_PAD_EIM_SDODT1 PAD_CTL_DRV_VOT_HIGH+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+#define CONFIG_IOMUX_PAD_EIM_SDBA2 PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL+PAD_CTL_100K_PU
+#define CONFIG_IOMUX_PAD_EIM_SDODT1 PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+PAD_CTL_100K_PD+PAD_CTL_DRV_HIGH+PAD_CTL_SRE_FAST
-#define CONFIG_IOMUX_PAD_EIM_SDODT0 PAD_CTL_DRV_VOT_HIGH+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+#define CONFIG_IOMUX_PAD_EIM_SDODT0 PAD_CTL_DRV_VOT_LOW+PAD_CTL_PKE_ENABLE+PAD_CTL_PUE_PULL \
+PAD_CTL_100K_PD+PAD_CTL_DRV_HIGH+PAD_CTL_SRE_FAST
#define CONFIG_IOMUX_GRP_DDRPKS PAD_CTL_PUE_KEEPER
@@ -1005,7 +1005,7 @@
#define CONFIG_IOMUX_GRP_HYSDDR0 PAD_CTL_HYS_NONE
#define CONFIG_IOMUX_GRP_HYSDDR1 PAD_CTL_HYS_NONE
#define CONFIG_IOMUX_GRP_HYSDDR2 PAD_CTL_HYS_NONE
-#define CONFIG_IOMUX_GRP_HVDDR PAD_CTL_DRV_VOT_HIGH
+#define CONFIG_IOMUX_GRP_HVDDR PAD_CTL_DRV_VOT_LOW
#define CONFIG_IOMUX_GRP_HYSDDR3 PAD_CTL_HYS_NONE
#define CONFIG_IOMUX_GRP_DRAM_SR_B0 PAD_CTL_SRE_FAST
#define CONFIG_IOMUX_GRP_DDRAPKS PAD_CTL_PUE_PULL
diff --git a/buildroot/target/u-boot/u-boot-2010.03-411-Fix-high-voltage-nand-sd.patch b/buildroot/target/u-boot/u-boot-2010.03-411-Fix-high-voltage-nand-sd.patch
new file mode 100644
index 0000000..1a62b78
--- /dev/null
+++ b/buildroot/target/u-boot/u-boot-2010.03-411-Fix-high-voltage-nand-sd.patch
@@ -0,0 +1,93 @@
+diff -purN u-boot-2010.03.ori/board/armadeus/apf51/apf51.c u-boot-2010.03/board/armadeus/apf51/apf51.c
+--- u-boot-2010.03.ori/board/armadeus/apf51/apf51.c 2011-01-25 22:43:23.000000000 +0100
++++ u-boot-2010.03/board/armadeus/apf51/apf51.c 2011-02-04 00:21:21.000000000 +0100
+@@ -513,22 +513,61 @@ void setup_nfc(void)
+ /*
+ * Configure iomux for NFC interface
+ */
++#define NAND_PAD47K_CFG (PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | \
++ PAD_CTL_PKE_ENABLE | PAD_CTL_47K_PU | \
++ PAD_CTL_DRV_HIGH)
++
++#define NAND_PAD100K_CFG (PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | \
++ PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | \
++ PAD_CTL_DRV_HIGH)
++
+ mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, NAND_PAD47K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, NAND_PAD47K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_ALE , IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_ALE , NAND_PAD47K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_CLE , IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_CLE , NAND_PAD47K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, NAND_PAD100K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_RB0 , IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_RB0 , PAD_CTL_DRV_VOT_HIGH |
++ PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE |
++ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
++
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+
++ /* MX51_PIN_NANDF_RDY_INT */
++
+ mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_D0, NAND_PAD100K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_D1, NAND_PAD100K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_D2, NAND_PAD100K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_D3, NAND_PAD100K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_D4, NAND_PAD100K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_D5, NAND_PAD100K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_D6, NAND_PAD100K_CFG);
++
+ mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_NANDF_D7, NAND_PAD100K_CFG);
+
+ writel(0, NFC_IPC);
+ NFC_SET_FW(1);
+diff -purN u-boot-2010.03.ori/include/asm-arm/arch-mx51/asm-offsets.h u-boot-2010.03/include/asm-arm/arch-mx51/asm-offsets.h
+--- u-boot-2010.03.ori/include/asm-arm/arch-mx51/asm-offsets.h 2011-01-25 22:43:22.000000000 +0100
++++ u-boot-2010.03/include/asm-arm/arch-mx51/asm-offsets.h 2011-02-03 23:08:33.000000000 +0100
+@@ -176,7 +176,7 @@
+ #define PAD_CTL_HYS_ENABLE (0x1 << 8) /* Hysteresis enabled */
+ #define PAD_CTL_DDR_INPUT_CMOS (0x0 << 9)/* DDR input CMOS */
+ #define PAD_CTL_DDR_INPUT_DDR (0x1 << 9)/* DDR input DDR */
+-#define PAD_CTL_DRV_VOT_LOW (0x0 << 13) /* Low voltage mode */
+-#define PAD_CTL_DRV_VOT_HIGH (0x1 << 13)/* High voltage mode */
++#define PAD_CTL_DRV_VOT_HIGH (0x0 << 13) /* High voltage mode */
++#define PAD_CTL_DRV_VOT_LOW (0x1 << 13)/* Low voltage mode */
+
+ #endif /* __ASSEMBLY__ */
+diff -purN u-boot-2010.03.ori/include/asm-arm/arch-mx51/iomux.h u-boot-2010.03/include/asm-arm/arch-mx51/iomux.h
+--- u-boot-2010.03.ori/include/asm-arm/arch-mx51/iomux.h 2010-03-31 23:54:39.000000000 +0200
++++ u-boot-2010.03/include/asm-arm/arch-mx51/iomux.h 2011-02-03 23:08:48.000000000 +0100
+@@ -66,8 +66,8 @@ typedef enum iomux_pad_config {
+ PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */
+ PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */
+ PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */
+- PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */
+- PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
++ PAD_CTL_DRV_VOT_HIGH = 0x0 << 13, /* High voltage mode */
++ PAD_CTL_DRV_VOT_LOW = 0x1 << 13,/* Low voltage mode */
+ } iomux_pad_config_t;
+
+ /* various IOMUX input select register index */
+
hooks/post-receive
--
armadeus
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