[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-219-g2ef8b0d
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[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-219-g2ef8b0d
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From: Fabien M <fa...@us...> - 2011-01-07 10:16:10
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 2ef8b0d7acd4a4d90bc50867b8476a2fe1c613f8 (commit)
via 20c2ca77f88a91a04afd5f3e539b9ebbb31c630d (commit)
via c58cdacb2346eb06b3fd13a92f8a4f6ffb40a412 (commit)
from a6350cd5e7a181dcad9194ded381855a5deb680b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2ef8b0d7acd4a4d90bc50867b8476a2fe1c613f8
Merge: 20c2ca77f88a91a04afd5f3e539b9ebbb31c630d a6350cd5e7a181dcad9194ded381855a5deb680b
Author: Fabien Marteau <fab...@ar...>
Date: Fri Jan 7 11:15:38 2011 +0100
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit 20c2ca77f88a91a04afd5f3e539b9ebbb31c630d
Author: Fabien Marteau <fab...@ar...>
Date: Fri Jan 7 11:15:08 2011 +0100
[U-BOOT] Adding second load operator for sp_vision spartan6 configuration (to be cleaned)
commit c58cdacb2346eb06b3fd13a92f8a4f6ffb40a412
Author: Fabien Marteau <fab...@ar...>
Date: Thu Jan 6 10:30:11 2011 +0100
[U-BOOT] Adding patch to add spartan6 under u-boot-2010.03
-----------------------------------------------------------------------
Summary of changes:
buildroot/target/device/armadeus/apf27/apf27.h | 3 +-
.../u-boot/u-boot-2010.03-321-add_spartan6.patch | 730 ++++++++++++++++++++
...oot-2010.03-322-fpga_second_load_operator.patch | 334 +++++++++
3 files changed, 1066 insertions(+), 1 deletions(-)
create mode 100644 buildroot/target/u-boot/u-boot-2010.03-321-add_spartan6.patch
create mode 100644 buildroot/target/u-boot/u-boot-2010.03-322-fpga_second_load_operator.patch
diff --git a/buildroot/target/device/armadeus/apf27/apf27.h b/buildroot/target/device/armadeus/apf27/apf27.h
index 6ef742f..3b3cc13 100644
--- a/buildroot/target/device/armadeus/apf27/apf27.h
+++ b/buildroot/target/device/armadeus/apf27/apf27.h
@@ -581,9 +581,10 @@
* FPGA stuff
*/
#define CONFIG_FPGA
-#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA_COUNT 2
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA_SPARTAN6
#define CFG_FPGA_WAIT 20000 /* 20 ms */
#define CFG_FPGA_PROG_FEEDBACK
#define CFG_FPGA_CHECK_CTRLC
diff --git a/buildroot/target/u-boot/u-boot-2010.03-321-add_spartan6.patch b/buildroot/target/u-boot/u-boot-2010.03-321-add_spartan6.patch
new file mode 100644
index 0000000..a0678c5
--- /dev/null
+++ b/buildroot/target/u-boot/u-boot-2010.03-321-add_spartan6.patch
@@ -0,0 +1,730 @@
+Index: u-boot-2010.03/include/spartan6.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/include/spartan6.h 2011-01-06 11:38:23.000000000 +0100
+@@ -0,0 +1,132 @@
++/*
++ * (C) Copyright 2010-2011 Fabien Marteau <fab...@ar...>
++ * Sponsorised by ARMadeus Systems.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++/*
++ * Configuration support for Xilinx Spartan6 devices. Based
++ * on spartan2.h (Rich Ireland, rir...@en...).
++ */
++
++#ifndef _SPARTAN6_H_
++#define _SPARTAN6_H_
++
++#include <xilinx.h>
++
++extern int Spartan6_load( Xilinx_desc *desc, void *image, size_t size );
++extern int Spartan6_dump( Xilinx_desc *desc, void *buf, size_t bsize );
++extern int Spartan6_info( Xilinx_desc *desc );
++extern int Spartan6_reloc( Xilinx_desc *desc, ulong reloc_off );
++
++/* Slave Parallel Implementation function table */
++typedef struct {
++ Xilinx_pre_fn pre;
++ Xilinx_pgm_fn pgm;
++ Xilinx_init_fn init;
++ Xilinx_err_fn err;
++ Xilinx_done_fn done;
++ Xilinx_clk_fn clk;
++ Xilinx_cs_fn cs;
++ Xilinx_wr_fn wr;
++ Xilinx_rdata_fn rdata;
++ Xilinx_wdata_fn wdata;
++ Xilinx_busy_fn busy;
++ Xilinx_abort_fn abort;
++ Xilinx_post_fn post;
++ int relocated;
++} Xilinx_Spartan6_Slave_Parallel_fns;
++
++/* Slave SelectMap Implementation function table */
++typedef struct {
++ Xilinx_pre_fn pre;
++ Xilinx_pgm_fn pgm;
++ Xilinx_init_fn init;
++ Xilinx_err_fn err;
++ Xilinx_done_fn done;
++ Xilinx_clk_fn clk;
++ Xilinx_cs_fn cs;
++ Xilinx_wr_fn wr;
++ Xilinx_rdata_fn rdata;
++ Xilinx_wdata_fn wdata;
++ Xilinx_busy_fn busy;
++ Xilinx_abort_fn abort;
++ Xilinx_post_fn post;
++ int relocated;
++} Xilinx_Spartan6_Slave_SelectMap_fns;
++
++/* Device Image Sizes
++ *********************************************************************/
++/* Spartan-VI */
++#define XILINX_XC6SLX4_SIZE (2724704l/8)
++#define XILINX_XC6SLX9_SIZE (2724704l/8)
++#define XILINX_XC6SLX16_SIZE (3713440l/8)
++#define XILINX_XC6SLX25_SIZE (6411440l/8)
++#define XILINX_XC6SLX25T_SIZE (6411440l/8)
++#define XILINX_XC6SLX45_SIZE (11875104l/8)
++#define XILINX_XC6SLX45T_SIZE (11875104l/8)
++#define XILINX_XC6SLX75_SIZE (19624608l/8)
++#define XILINX_XC6SLX75T_SIZE (19624608l/8)
++#define XILINX_XC6SLX100_SIZE (26543136l/8)
++#define XILINX_XC6SLX100T_SIZE (26543136l/8)
++#define XILINX_XC6SLX150_SIZE (33761568l/8)
++#define XILINX_XC6SLX150T40_SIZE (33761568l/8)
++
++/* Descriptor Macros
++ *********************************************************************/
++/* Spartan-VI devices */
++#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX9_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX9_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX16_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX16_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX25_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX25_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX25T_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX25T_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX25T_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX45_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX45_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX45T_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX45T_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX75_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX75_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX75T_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX75T_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX100_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX100_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX100T_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface, XILINX_XC6SLX100T_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX150_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface, XILINX_XC6SLX150_SIZE , fn_table, cookie }
++
++#define XILINX_XC6SLX150T40_DESC(iface, fn_table, cookie) \
++{ Xilinx_Spartan6, iface,XILINX_XC6SLX150T40_SIZE , fn_table, cookie }
++
++#endif /* _SPARTAN6_H_ */
+Index: u-boot-2010.03/drivers/fpga/spartan6.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/drivers/fpga/spartan6.c 2011-01-06 11:50:51.000000000 +0100
+@@ -0,0 +1,538 @@
++/*
++ * (C) Copyright 2010 Fabien Marteau <fab...@ar...>
++ * Sponsorised by ARMadeus Systems.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++/*
++ * Configuration support for Xilinx Spartan6 devices. Based
++ * on spartan6.c (Rich Ireland, rir...@en...).
++ */
++
++#include <common.h> /* core U-Boot definitions */
++#include <spartan6.h> /* Spartan-II device family */
++
++#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN6)
++
++/* Define FPGA_DEBUG to get debug printf's */
++#ifdef FPGA_DEBUG
++#define PRINTF(fmt,args...) printf (fmt ,##args)
++#else
++#define PRINTF(fmt,args...)
++#endif
++
++#undef CONFIG_SYS_FPGA_CHECK_BUSY
++#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
++
++/* Note: The assumption is that we cannot possibly run fast enough to
++ * overrun the device (the Slave Parallel mode can free run at 50MHz).
++ * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
++ * the board config file to slow things down.
++ */
++#ifndef CONFIG_FPGA_DELAY
++#define CONFIG_FPGA_DELAY()
++#endif
++
++#ifndef CONFIG_SYS_FPGA_WAIT
++#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
++#endif
++
++static int Spartan6_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
++static int Spartan6_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
++/* static int Spartan6_sp_info( Xilinx_desc *desc ); */
++static int Spartan6_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
++
++static int Spartan6_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
++static int Spartan6_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
++/* static int Spartan6_ss_info( Xilinx_desc *desc ); */
++static int Spartan6_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
++static int Spartan6_ssm_reloc( Xilinx_desc *desc, ulong reloc_offset );
++
++/* ------------------------------------------------------------------------- */
++/* Spartan-II Generic Implementation */
++int Spartan6_load (Xilinx_desc * desc, void *buf, size_t bsize)
++{
++ int ret_val = FPGA_FAIL;
++
++ printf("ERROR: spartan6 simple load function is not implemented\n");
++
++ return ret_val;
++}
++
++/* ------------------------------------------------------------------------- */
++/* Spartan-VI Generic Implementation */
++int Spartan6_dump (Xilinx_desc * desc, void *buf, size_t bsize)
++{
++ int ret_val = FPGA_FAIL;
++
++
++ return ret_val;
++}
++
++int Spartan6_info( Xilinx_desc *desc )
++{
++ return FPGA_SUCCESS;
++}
++
++
++int Spartan6_reloc (Xilinx_desc * desc, ulong reloc_offset)
++{
++ int ret_val = FPGA_FAIL; /* assume a failure */
++
++ if (desc->family != Xilinx_Spartan6) {
++ printf ("%s: Unsupported family type (spartan6 line %d), %d\n",
++ __FUNCTION__, __LINE__, desc->family);
++ return FPGA_FAIL;
++ } else
++ switch (desc->iface) {
++ case slave_serial:
++ ret_val = Spartan6_ss_reloc (desc, reloc_offset);
++ break;
++
++ case slave_parallel:
++ ret_val = Spartan6_sp_reloc (desc, reloc_offset);
++ break;
++
++ case slave_selectmap:
++ ret_val = Spartan6_ssm_reloc (desc, reloc_offset);
++ break;
++
++ default:
++ printf ("%s: Unsupported interface type (spartan6 line %d), %d\n",
++ __FUNCTION__, __LINE__, desc->iface);
++ }
++
++ return ret_val;
++}
++
++/* ------------------------------------------------------------------------- */
++/* Spartan-VI Slave Parallel Generic Implementation */
++static int Spartan6_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
++{
++ int ret_val = FPGA_FAIL; /* assume the worst */
++ Xilinx_Spartan6_Slave_Parallel_fns *fn = desc->iface_fns;
++
++ PRINTF ("%s: start with interface functions @ 0x%p\n",
++ __FUNCTION__, fn);
++
++ if (fn) {
++ size_t bytecount = 0;
++ unsigned char *data = (unsigned char *) buf;
++ int cookie = desc->cookie; /* make a local copy */
++ unsigned long ts; /* timestamp */
++
++ PRINTF ("%s: Function Table:\n"
++ "ptr:\t0x%p\n"
++ "struct: 0x%p\n"
++ "pre: 0x%p\n"
++ "pgm:\t0x%p\n"
++ "init:\t0x%p\n"
++ "err:\t0x%p\n"
++ "clk:\t0x%p\n"
++ "cs:\t0x%p\n"
++ "wr:\t0x%p\n"
++ "read data:\t0x%p\n"
++ "write data:\t0x%p\n"
++ "busy:\t0x%p\n"
++ "abort:\t0x%p\n",
++ "post:\t0x%p\n\n",
++ __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
++ fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
++ fn->abort, fn->post);
++
++ /*
++ * This code is designed to emulate the "Express Style"
++ * Continuous Data Loading in Slave Parallel Mode for
++ * the Spartan-II Family.
++ */
++#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
++ printf ("Loading FPGA Device %d...\n", cookie);
++#endif
++ /*
++ * Run the pre configuration function if there is one.
++ */
++ if (*fn->pre) {
++ (*fn->pre) (cookie);
++ }
++
++ /* Establish the initial state */
++ (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
++
++ /* Get ready for the burn */
++ CONFIG_FPGA_DELAY ();
++ (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
++
++ ts = get_timer (0); /* get current time */
++ /* Now wait for INIT and BUSY to go high */
++ do {
++ CONFIG_FPGA_DELAY ();
++ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
++ puts ("** Timeout waiting for INIT to clear.\n");
++ (*fn->abort) (cookie); /* abort the burn */
++ return FPGA_FAIL;
++ }
++ } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
++
++ (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
++ (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
++ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
++
++ /* Load the data */
++ while ( (*fn->done) (cookie) == FPGA_FAIL){
++ /* XXX - do we check for an Ctrl-C press in here ??? */
++ /* XXX - Check the error bit? */
++
++ (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
++ CONFIG_FPGA_DELAY ();
++ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
++ CONFIG_FPGA_DELAY ();
++ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
++
++ ts = get_timer (0); /* get current time */
++#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
++ while ((*fn->busy) (cookie)) {
++ /* XXX - we should have a check in here somewhere to
++ * make sure we aren't busy forever... */
++
++ CONFIG_FPGA_DELAY ();
++ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
++ CONFIG_FPGA_DELAY ();
++ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
++
++ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
++ puts ("** Timeout waiting for BUSY to clear.\n");
++ (*fn->abort) (cookie); /* abort the burn */
++ return FPGA_FAIL;
++ }
++ }
++#endif
++ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
++ puts ("** Timeout waiting for BUSY to clear.\n");
++ (*fn->abort) (cookie); /* abort the burn */
++ return FPGA_FAIL;
++ }
++
++#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
++ if (bytecount % (bsize / 40) == 0)
++ putc ('.'); /* let them know we are alive */
++#endif
++ }
++
++ CONFIG_FPGA_DELAY ();
++ (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
++ (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
++
++#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
++ putc ('\n'); /* terminate the dotted line */
++#endif
++
++ /* now check for done signal */
++ ts = get_timer (0); /* get current time */
++ ret_val = FPGA_SUCCESS;
++ while ((*fn->done) (cookie) == FPGA_FAIL) {
++ /* XXX - we should have a check in here somewhere to
++ * make sure we aren't busy forever... */
++
++ CONFIG_FPGA_DELAY ();
++ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
++ CONFIG_FPGA_DELAY ();
++ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
++
++ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
++ puts ("** Timeout waiting for DONE to clear.\n");
++ (*fn->abort) (cookie); /* abort the burn */
++ ret_val = FPGA_FAIL;
++ break;
++ }
++ }
++
++ if (ret_val == FPGA_SUCCESS) {
++#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
++ puts ("Done.\n");
++#endif
++ }
++ /*
++ * Run the post configuration function if there is one.
++ */
++ if (*fn->post) {
++ (*fn->post) (cookie);
++ }
++
++ else {
++#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
++ puts ("Fail.\n");
++#endif
++ }
++
++ } else {
++ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
++ }
++
++ return ret_val;
++}
++
++static int Spartan6_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
++{
++ int ret_val = FPGA_FAIL; /* assume the worst */
++ Xilinx_Spartan6_Slave_Parallel_fns *fn = desc->iface_fns;
++
++ if (fn) {
++ unsigned char *data = (unsigned char *) buf;
++ size_t bytecount = 0;
++ int cookie = desc->cookie; /* make a local copy */
++
++ printf ("Starting Dump of FPGA Device %d...\n", cookie);
++
++ (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
++ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
++
++ /* dump the data */
++ while (bytecount < bsize) {
++ /* XXX - do we check for an Ctrl-C press in here ??? */
++
++ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
++ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
++ (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
++#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
++ if (bytecount % (bsize / 40) == 0)
++ putc ('.'); /* let them know we are alive */
++#endif
++ }
++
++ (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
++ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
++ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
++
++#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
++ putc ('\n'); /* terminate the dotted line */
++#endif
++ puts ("Done.\n");
++
++ /* XXX - checksum the data? */
++ } else {
++ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
++ }
++
++ return ret_val;
++}
++
++
++static int Spartan6_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
++{
++ int ret_val = FPGA_FAIL; /* assume the worst */
++ Xilinx_Spartan6_Slave_Parallel_fns *fn_r, *fn =
++ (Xilinx_Spartan6_Slave_Parallel_fns *) (desc->iface_fns);
++
++ if (fn) {
++ ulong addr;
++
++ /* Get the relocated table address */
++ addr = (ulong) fn + reloc_offset;
++ fn_r = (Xilinx_Spartan6_Slave_Parallel_fns *) addr;
++
++ if (!fn_r->relocated) {
++
++ if (memcmp (fn_r, fn,
++ sizeof (Xilinx_Spartan6_Slave_Parallel_fns))
++ == 0) {
++ /* good copy of the table, fix the descriptor pointer */
++ desc->iface_fns = fn_r;
++ } else {
++ PRINTF ("%s: Invalid function table at 0x%p\n",
++ __FUNCTION__, fn_r);
++ return FPGA_FAIL;
++ }
++
++ PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
++ desc);
++
++ addr = (ulong) (fn->pre) + reloc_offset;
++ fn_r->pre = (Xilinx_pre_fn) addr;
++
++ addr = (ulong) (fn->pgm) + reloc_offset;
++ fn_r->pgm = (Xilinx_pgm_fn) addr;
++
++ addr = (ulong) (fn->init) + reloc_offset;
++ fn_r->init = (Xilinx_init_fn) addr;
++
++ addr = (ulong) (fn->done) + reloc_offset;
++ fn_r->done = (Xilinx_done_fn) addr;
++
++ addr = (ulong) (fn->clk) + reloc_offset;
++ fn_r->clk = (Xilinx_clk_fn) addr;
++
++ addr = (ulong) (fn->err) + reloc_offset;
++ fn_r->err = (Xilinx_err_fn) addr;
++
++ addr = (ulong) (fn->cs) + reloc_offset;
++ fn_r->cs = (Xilinx_cs_fn) addr;
++
++ addr = (ulong) (fn->wr) + reloc_offset;
++ fn_r->wr = (Xilinx_wr_fn) addr;
++
++ addr = (ulong) (fn->rdata) + reloc_offset;
++ fn_r->rdata = (Xilinx_rdata_fn) addr;
++
++ addr = (ulong) (fn->wdata) + reloc_offset;
++ fn_r->wdata = (Xilinx_wdata_fn) addr;
++
++ addr = (ulong) (fn->busy) + reloc_offset;
++ fn_r->busy = (Xilinx_busy_fn) addr;
++
++ addr = (ulong) (fn->abort) + reloc_offset;
++ fn_r->abort = (Xilinx_abort_fn) addr;
++
++ addr = (ulong) (fn->post) + reloc_offset;
++ fn_r->post = (Xilinx_post_fn) addr;
++
++ fn_r->relocated = TRUE;
++
++ } else {
++ /* this table has already been moved */
++ /* XXX - should check to see if the descriptor is correct */
++ desc->iface_fns = fn_r;
++ }
++
++ ret_val = FPGA_SUCCESS;
++ } else {
++ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
++ }
++
++ return ret_val;
++
++}
++
++/* ------------------------------------------------------------------------- */
++
++static int Spartan6_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
++{
++ int ret_val = FPGA_FAIL; /* assume the worst */
++
++ printf ("%s: Slave Serial load is unavailable\n",
++ __FUNCTION__);
++
++ return ret_val;
++}
++
++static int Spartan6_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
++{
++ /* Readback is only available through the Slave Parallel and */
++ /* boundary-scan interfaces. */
++ printf ("%s: Slave Serial Dumping is unavailable\n",
++ __FUNCTION__);
++ return FPGA_FAIL;
++}
++
++static int Spartan6_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
++{
++ int ret_val = FPGA_FAIL; /* assume the worst */
++
++ printf ("%s: Slave Serial reloc is unavailable\n",
++ __FUNCTION__);
++
++ return ret_val;
++
++}
++
++static int Spartan6_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset)
++{
++ int ret_val = FPGA_FAIL; /* assume the worst */
++
++ Xilinx_Spartan6_Slave_SelectMap_fns *fn_r, *fn =
++ (Xilinx_Spartan6_Slave_SelectMap_fns *) (desc->iface_fns);
++
++ if (fn) {
++ ulong addr;
++
++ /* Get the relocated table address */
++ addr = (ulong) fn + reloc_offset;
++ fn_r = (Xilinx_Spartan6_Slave_SelectMap_fns *) addr;
++
++ if (!fn_r->relocated) {
++
++ if (memcmp (fn_r, fn,
++ sizeof (Xilinx_Spartan6_Slave_SelectMap_fns))
++ == 0) {
++ /* good copy of the table, fix the descriptor pointer */
++ desc->iface_fns = fn_r;
++ } else {
++ PRINTF ("%s: Invalid function table at 0x%p\n",
++ __FUNCTION__, fn_r);
++ return FPGA_FAIL;
++ }
++
++ PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
++ desc);
++
++ addr = (ulong) (fn->pre) + reloc_offset;
++ fn_r->pre = (Xilinx_pre_fn) addr;
++
++ addr = (ulong) (fn->pgm) + reloc_offset;
++ fn_r->pgm = (Xilinx_pgm_fn) addr;
++
++ addr = (ulong) (fn->init) + reloc_offset;
++ fn_r->init = (Xilinx_init_fn) addr;
++
++ addr = (ulong) (fn->done) + reloc_offset;
++ fn_r->done = (Xilinx_done_fn) addr;
++
++ addr = (ulong) (fn->clk) + reloc_offset;
++ fn_r->clk = (Xilinx_clk_fn) addr;
++
++ addr = (ulong) (fn->err) + reloc_offset;
++ fn_r->err = (Xilinx_err_fn) addr;
++
++ addr = (ulong) (fn->cs) + reloc_offset;
++ fn_r->cs = (Xilinx_cs_fn) addr;
++
++ addr = (ulong) (fn->wr) + reloc_offset;
++ fn_r->wr = (Xilinx_wr_fn) addr;
++
++ addr = (ulong) (fn->rdata) + reloc_offset;
++ fn_r->rdata = (Xilinx_rdata_fn) addr;
++
++ addr = (ulong) (fn->wdata) + reloc_offset;
++ fn_r->wdata = (Xilinx_wdata_fn) addr;
++
++ addr = (ulong) (fn->busy) + reloc_offset;
++ fn_r->busy = (Xilinx_busy_fn) addr;
++
++ addr = (ulong) (fn->abort) + reloc_offset;
++ fn_r->abort = (Xilinx_abort_fn) addr;
++
++ addr = (ulong) (fn->post) + reloc_offset;
++ fn_r->post = (Xilinx_post_fn) addr;
++
++ fn_r->relocated = TRUE;
++
++ } else {
++ /* this table has already been moved */
++ /* XXX - should check to see if the descriptor is correct */
++ desc->iface_fns = fn_r;
++ }
++
++ ret_val = FPGA_SUCCESS;
++ } else {
++ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
++ }
++
++
++ return ret_val;
++
++}
++#endif
+Index: u-boot-2010.03/drivers/fpga/Makefile
+===================================================================
+--- u-boot-2010.03.orig/drivers/fpga/Makefile 2011-01-06 11:38:21.000000000 +0100
++++ u-boot-2010.03/drivers/fpga/Makefile 2011-01-06 11:38:23.000000000 +0100
+@@ -29,6 +29,7 @@
+ COBJS-y += fpga.o
+ COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
+ COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
++COBJS-$(CONFIG_FPGA_SPARTAN6) += spartan6.o
+ COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
+ COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
+ ifdef CONFIG_FPGA_ALTERA
+Index: u-boot-2010.03/include/xilinx.h
+===================================================================
+--- u-boot-2010.03.orig/include/xilinx.h 2011-01-06 11:38:21.000000000 +0100
++++ u-boot-2010.03/include/xilinx.h 2011-01-06 11:48:43.000000000 +0100
+@@ -33,10 +33,12 @@
+ #define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 )
+ #define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 )
+ #define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 )
++#define CONFIG_SYS_SPARTAN6 CONFIG_SYS_FPGA_DEV( 0xa )
+ #define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
+ #define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
+ #define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
+ #define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
++#define CONFIG_SYS_XILINX_SPARTAN6 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN6)
+ /* XXX - Add new models here */
+
+
+@@ -68,6 +70,7 @@
+ Xilinx_VirtexE, /* Virtex-E Family */
+ Xilinx_Virtex2, /* Virtex2 Family */
+ Xilinx_Spartan3, /* Spartan-III Family */
++ Xilinx_Spartan6, /* Spartan-VI Family */
+ max_xilinx_type /* insert all new types before this */
+ } Xilinx_Family; /* end, typedef Xilinx_Family */
+
+Index: u-boot-2010.03/README
+===================================================================
+--- u-boot-2010.03.orig/README 2011-01-06 11:38:21.000000000 +0100
++++ u-boot-2010.03/README 2011-01-06 11:38:23.000000000 +0100
+@@ -1639,7 +1639,7 @@
+ CONFIG_FPGA_<family>
+
+ Enables support for FPGA family.
+- (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
++ (SPARTAN2, SPARTAN3,SPARTAN6, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
+
+ CONFIG_FPGA_COUNT
+
diff --git a/buildroot/target/u-boot/u-boot-2010.03-322-fpga_second_load_operator.patch b/buildroot/target/u-boot/u-boot-2010.03-322-fpga_second_load_operator.patch
new file mode 100644
index 0000000..ef412dc
--- /dev/null
+++ b/buildroot/target/u-boot/u-boot-2010.03-322-fpga_second_load_operator.patch
@@ -0,0 +1,334 @@
+Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
+===================================================================
+--- u-boot-2010.03.orig/board/armadeus/apf27/fpga.c 2011-01-06 11:44:48.000000000 +0100
++++ u-boot-2010.03/board/armadeus/apf27/fpga.c 2011-01-06 11:44:54.000000000 +0100
+@@ -33,6 +33,7 @@
+ #include <config.h>
+ #include "fpga.h"
+ #include <spartan3.h>
++#include <spartan6.h>
+
+ #define GPIO_PORT(x) ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT)
+ #define GPIO_SET(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | (1 << (x & GPIO_PIN_MASK)), \
+@@ -67,21 +68,48 @@
+ fpga_wr_fn,
+ fpga_rdata_fn,
+ fpga_wdata_fn,
+- fpga_busy_fn,
++ fpga_busy_fn,
+ fpga_abort_fn,
+ fpga_post_fn,
+ };
+
++Xilinx_Spartan6_Slave_SelectMap_fns fpga_second_fns= {
++ fpga_spartan6_pre_fn,
++ fpga_spartan6_pgm_fn,
++ fpga_spartan6_init_fn,
++ NULL,
++ fpga_spartan6_done_fn,
++ fpga_spartan6_clk_fn,
++ fpga_spartan6_cs_fn,
++ fpga_spartan6_wr_fn,
++ fpga_spartan6_rdata_fn,
++ fpga_spartan6_wdata_fn,
++ fpga_spartan6_busy_fn,
++ fpga_spartan6_abort_fn,
++ fpga_spartan6_post_fn,
++
++};
++
+ Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+ {Xilinx_Spartan3,
+ slave_parallel,
+ 1196128l/8,
+ (void *) &fpga_fns,
+- 0}
++ 0},
++ {Xilinx_Spartan6,
++ slave_selectmap,
++ XILINX_XC6SLX45_SIZE,
++ (void *) &fpga_fns,
++ 0xD6000000l,
++ 0, 0,
++ 1}
+ };
+
++/*******************************************
++ * SPARTAN3 APF27 configuration functions *
++ *******************************************/
+ /*
+- * nitialize GPIO port B before download
++ * Initialize GPIO port B before download
+ */
+ int
+ fpga_pre_fn (int cookie)
+@@ -264,4 +292,228 @@
+ return lout;
+ }
+
++/**********************************************
++* SPARTAN6 sp_vision configuration functions *
++***********************************************/
++
++#define SELECTMAP_ID_REG (desc->ip_addr)
++#define SELECTMAP_CONFIG_REG (desc->ip_addr+2)
++#define SELECTMAP_STATUS_REG (desc->ip_addr+4)
++#define SELECTMAP_DATA_REG (desc->ip_addr+6)
++
++#define SELECTMAP_CONFIG_CLK 4
++#define SELECTMAP_CONFIG_CSI_N 2
++#define SELECTMAP_CONFIG_PROGRAM_N 1
++#define SELECTMAP_CONFIG_RDWR_N 0
++
++#define SELECTMAP_STATUS_INIT_N 2
++#define SELECTMAP_STATUS_BUSY 1
++#define SELECTMAP_STATUS_DONE 0
++
++/*
++ * Initialize FPGA before download
++ */
++int
++fpga_spartan6_pre_fn (int cookie)
++{
++ int config;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ config = *((volatile uint16_t *)SELECTMAP_CONFIG_REG); /* read config */
++
++ config &= ~(1 << SELECTMAP_CONFIG_CLK); /* IP in selectmap mode */
++ config |= (1 << SELECTMAP_CONFIG_CSI_N); /* CSI_n High */
++ config |= (1 << SELECTMAP_CONFIG_PROGRAM_N); /* PROGRAM_n High */
++ config |= (1 << SELECTMAP_CONFIG_RDWR_N); /* rdwr_n High */
++
++ *((ushort *)SELECTMAP_CONFIG_REG) = (ushort)config; /* write config */
++
++ udelay(1); /*wait until supply started*/
++ return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int
++fpga_spartan6_pgm_fn (int assert, int flush, int cookie)
++{
++ unsigned short config;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ config = *((volatile uint16_t *)SELECTMAP_CONFIG_REG); /* read config */
++
++ PRINTF ("%s:%d: FPGA SET PROGRAM %s", __FUNCTION__, __LINE__,
++ assert?"high":"low");
++ PRINTF ("\n");
++
++ if (assert)
++ config &= ~(1 << SELECTMAP_CONFIG_PROGRAM_N);
++ else
++ config |= (1 << SELECTMAP_CONFIG_PROGRAM_N);
++
++ *((unsigned short *)SELECTMAP_CONFIG_REG) = config; /* write config */
++
++ return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int
++fpga_spartan6_clk_fn (int assert_clk, int flush, int cookie)
++{
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ PRINTF ("%s:%d: FPGA SETÂ CLOCK %s", __FUNCTION__, __LINE__,
++ assert_clk?"high":"low");
++ PRINTF ("\n");
++
++ /* clock pulse is generated when a data is wrote */
++
++ return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line.
++ */
++int
++fpga_spartan6_init_fn (int cookie)
++{
++ int value=0;
++ uint16_t status;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ status = *((volatile uint16_t *)SELECTMAP_STATUS_REG); /* read config */
++
++ PRINTF ("%s:%d: INIT check", __FUNCTION__, __LINE__);
++ PRINTF ("%d\n",(((status&(1<<SELECTMAP_STATUS_INIT_N))==0)?1:0));
++ PRINTF ("\n");
++
++ return (((status&(1<<SELECTMAP_STATUS_INIT_N))==0)?FPGA_SUCCESS:FPGA_FAIL);
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int
++fpga_spartan6_done_fn (int cookie)
++{
++ uint16_t status;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ status = *((volatile uint16_t *)SELECTMAP_STATUS_REG); /* read config */
++ PRINTF ("%s:%d: DONE check %s\n", __FUNCTION__, __LINE__,
++ (((status&(1<<SELECTMAP_STATUS_DONE))==0)?0:1)?"high":"low");
++
++ return (((status&(1<<SELECTMAP_STATUS_DONE))==0)?FPGA_FAIL:FPGA_SUCCESS);
++}
++
++/*
++ * Set the FPGA's wr line to the specified level
++ */
++int
++fpga_spartan6_wr_fn (int assert_write, int flush, int cookie)
++{
++ unsigned short config;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ PRINTF ("%s:%d: FPGA SETÂ RW %s ", __FUNCTION__, __LINE__,
++ assert_write?"high":"low");
++ PRINTF ("\n");
++
++ config = *((volatile uint16_t *)SELECTMAP_CONFIG_REG); /* read config */
++ if (assert_write)
++ config &= ~(1 << SELECTMAP_CONFIG_RDWR_N);
++ else
++ config |= (1 << SELECTMAP_CONFIG_RDWR_N);
++ *((unsigned short*)SELECTMAP_CONFIG_REG) = config; /* write config */
++
++ return assert_write;
++}
++
++int
++fpga_spartan6_cs_fn (int assert_cs, int flush, int cookie)
++{
++ int config;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ PRINTF ("%s:%d: FPGA SETÂ CS %s ", __FUNCTION__, __LINE__,
++ assert_cs?"high":"low");
++ PRINTF ("\n");
++
++ config = *((volatile uint16_t *)SELECTMAP_CONFIG_REG); /* read config */
++ if (assert_cs)
++ config &= ~(1 << SELECTMAP_CONFIG_CSI_N);
++ else
++ config |= (1 << SELECTMAP_CONFIG_CSI_N);
++ *((ushort *)SELECTMAP_CONFIG_REG) = (ushort)config; /* write config */
++
++ return assert_cs;
++}
++
++/* TODO: read/write in 16bits mode */
++int
++fpga_spartan6_rdata_fn ( unsigned char *data, int cookie )
++{
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ *data = (unsigned char)((*((unsigned short*)SELECTMAP_DATA_REG))&0x00FF);
++ PRINTF(".");
++
++ return *data;
++}
++
++int
++fpga_spartan6_wdata_fn ( unsigned char data, int cookie )
++{
++ int config;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ *((unsigned short*)SELECTMAP_DATA_REG) = data&0x00ff;
++
++ return data;
++}
++/* end of TODO */
++
++int
++fpga_spartan6_abort_fn ( int cookie )
++{
++ int config;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ config = *((volatile uint16_t *)SELECTMAP_CONFIG_REG); /* read config */
++ config |= (1 << SELECTMAP_CONFIG_CLK); /* IP in clock mode */
++ *((ushort *)SELECTMAP_CONFIG_REG) = (ushort)config; /* write config */
++
++ return cookie;
++}
++
++int
++fpga_spartan6_busy_fn ( int cookie )
++{
++ uint16_t status;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++// PRINTF ("%s:%d: DONE check %s", __FUNCTION__, __LINE__,
++// GPIO_READ(CFG_FPGA_DONE)?"high":"low");
++ status = *((volatile uint16_t *)SELECTMAP_STATUS_REG); /* read config */
++
++ return (((status&(1<<SELECTMAP_STATUS_BUSY))!=0)?0:1);
++}
++
++int
++fpga_spartan6_post_fn (int cookie)
++{
++ int config;
++ Xilinx_desc *desc = apf27_fpga_get_desc(cookie);
++
++ config = *((volatile uint16_t *)SELECTMAP_CONFIG_REG); /* read config */
++ config |= (1 << SELECTMAP_CONFIG_CLK); /* IP in clock mode */
++ *((ushort *)SELECTMAP_CONFIG_REG) = (ushort)config; /* write config */
++
++ return cookie;
++}
++
++
+ #endif /* CONFIG_FPGA */
+Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
+===================================================================
+--- u-boot-2010.03.orig/board/armadeus/apf27/fpga.h 2011-01-06 11:44:48.000000000 +0100
++++ u-boot-2010.03/board/armadeus/apf27/fpga.h 2011-01-06 11:44:54.000000000 +0100
+@@ -37,3 +37,20 @@
+ extern int fpga_abort_fn (int cookie);
+ extern int fpga_post_fn (int cookie);
+ extern int fpga_busy_fn (int cookie);
++
++#if defined(CONFIG_FPGA_SPARTAN6)
++extern int fpga_spartan6_check_fn(int ip_addr, int ip_id, int cookie);
++extern int fpga_spartan6_pre_fn (int cookie);
++extern int fpga_spartan6_pgm_fn (int assert_pgm, int flush, int cookie);
++extern int fpga_spartan6_cs_fn (int assert_cs, int flush, int cookie);
++extern int fpga_spartan6_init_fn (int cookie);
++extern int fpga_spartan6_done_fn (int cookie);
++extern int fpga_spartan6_clk_fn (int assert_clk, int flush, int cookie);
++extern int fpga_spartan6_wr_fn (int assert_write, int flush, int cookie);
++extern int fpga_spartan6_rdata_fn ( unsigned char *data, int cookie );
++extern int fpga_spartan6_wdata_fn ( unsigned char data, int cookie );
++extern int fpga_spartan6_abort_fn (int cookie);
++extern int fpga_spartan6_post_fn (int cookie);
++extern int fpga_spartan6_busy_fn (int cookie);
++#endif /* CONFIG_FPGA_SPARTAN3 */
++
+Index: u-boot-2010.03/include/xilinx.h
+===================================================================
+--- u-boot-2010.03.orig/include/xilinx.h 2011-01-06 11:44:59.000000000 +0100
++++ u-boot-2010.03/include/xilinx.h 2011-01-06 11:46:08.000000000 +0100
+@@ -77,6 +77,11 @@
+ typedef struct { /* typedef Xilinx_desc */
+ Xilinx_Family family; /* part type */
+ Xilinx_iface iface; /* interface type */
++ /* XXX:for second fpga configuration (throught first fpga) */
++ uint32_t fpga_offset; /* first fpga offset */
++ int ip_addr; /* Address of spartan_selectmap IP */
++ int ip_id; /* Idendifiant of spartan_selectmap IP */
++ /* end of XXX */
+ size_t size; /* bytes of data part can accept */
+ void *iface_fns; /* interface function table */
+ int cookie; /* implementation specific cookie */
hooks/post-receive
--
armadeus
|
