[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-209-g96c957b
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[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-209-g96c957b
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From: Fabien M <fa...@us...> - 2011-01-05 14:37:40
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 96c957b8b9b650b4fdf310465ff9b6057e7a3bfd
Author: Fabien Marteau <fab...@ar...>
Date: Wed Jan 5 15:37:10 2011 +0100
[FIRMWARE] Adding minimum spartan3 design used to configure sp_vision spartan6 fpga
-----------------------------------------------------------------------
Summary of changes:
firmware/sp_vision_config/README | 43 +++
.../bitstream/top_testconfig.bit} | Bin 149603 -> 149615 bytes
.../simulation/apf27_test_pkg.vhd} | 31 +-
.../imx27_wb16_wrapper/imx27_wb16_wrapper.vhd} | 68 ++--
.../imx27_wb16_wrapper00_mwb16_intercon.vhd | 102 ++++++
.../synthesis/rstgen_syscon}/rstgen_syscon.vhd | 0
.../spartan_select_map/spartan_selectmap.vhd | 211 +++++++++++
firmware/sp_vision_config/synthesis/testconfig.tcl | 21 ++
firmware/sp_vision_config/synthesis/testconfig.ucf | 69 ++++
.../sp_vision_config/synthesis/top_testconfig.vhd | 372 ++++++++++++++++++++
10 files changed, 871 insertions(+), 46 deletions(-)
create mode 100644 firmware/sp_vision_config/README
copy firmware/{wishbone_example/bin/wishbone_example_apf27_200k.bit => sp_vision_config/bitstream/top_testconfig.bit} (74%)
copy firmware/{wishbone_example/testbench/apf_test_pkg.vhd => sp_vision_config/simulation/apf27_test_pkg.vhd} (90%)
copy firmware/{wishbone_example/src/wishbone_wrapper.vhd => sp_vision_config/synthesis/imx27_wb16_wrapper/imx27_wb16_wrapper.vhd} (58%)
create mode 100644 firmware/sp_vision_config/synthesis/imx27_wb16_wrapper00_mwb16/imx27_wb16_wrapper00_mwb16_intercon.vhd
copy firmware/{wishbone_example/src => sp_vision_config/synthesis/rstgen_syscon}/rstgen_syscon.vhd (100%)
create mode 100644 firmware/sp_vision_config/synthesis/spartan_select_map/spartan_selectmap.vhd
create mode 100644 firmware/sp_vision_config/synthesis/testconfig.tcl
create mode 100644 firmware/sp_vision_config/synthesis/testconfig.ucf
create mode 100644 firmware/sp_vision_config/synthesis/top_testconfig.vhd
diff --git a/firmware/sp_vision_config/README b/firmware/sp_vision_config/README
new file mode 100644
index 0000000..f831609
--- /dev/null
+++ b/firmware/sp_vision_config/README
@@ -0,0 +1,43 @@
+sp_vision_config
+=======================
+
+This is a minimum design used to configure second fpga on sp_vision daugther
+board.
+This design is designed to configure a spartan6 with SelectMap Slave
+protocol.
+
+FPGA component
+--------------
+
+Output component is composed of four 16 bits registers:
+
+| offset | name | description |
+|:-----------|:-----------:|:--------------------------------------:|
+| 0x00 | ID | component identifiant |
+| 0x02 | CONFIG | configuration for control signals |
+| 0x04 | STATUS | control signals status |
+| 0x06 | DATA | bitstream 16bits data sent to spartan6 |
+
+* ID : unique number to identify component.
+
+* CONFIG : Drive control signals
+
+| 15 downto 5 | 4 | 3 | 2 | 1 | 0 |
+|:-----------:|:---:|:----:|:---:|:-------:|:-----:|
+| void | CLK | void |CSI_n|PROGRAM_n|RDWR_n |
+
+CLK flag is used to switch composant in configuration mode :
+- When CLK=1, component is in idle mode, CCLK output drive general clock and
+ all other output signals are High impedance.
+- When CLK=0, the component is in fpga configuration mode.
+
+* STATUS : read input signal from fpga
+
+| 15 downto 3 | 2 | 1 | 0 |
+|:-----------:|:----:|:--:|:----:|
+| void |INIT_n|BUSY|RDWR_n|
+
+* DATA : 16 bits data wrote for configuring FPGA.
+When a data is written in this register, the value is placed on data output
+port, and one cclk pulse is generated.
+
diff --git a/firmware/wishbone_example/bin/wishbone_example_apf27_200k.bit b/firmware/sp_vision_config/bitstream/top_testconfig.bit
similarity index 74%
copy from firmware/wishbone_example/bin/wishbone_example_apf27_200k.bit
copy to firmware/sp_vision_config/bitstream/top_testconfig.bit
index 25d1895..7592c17 100644
Binary files a/firmware/wishbone_example/bin/wishbone_example_apf27_200k.bit and b/firmware/sp_vision_config/bitstream/top_testconfig.bit differ
diff --git a/firmware/wishbone_example/testbench/apf_test_pkg.vhd b/firmware/sp_vision_config/simulation/apf27_test_pkg.vhd
similarity index 90%
copy from firmware/wishbone_example/testbench/apf_test_pkg.vhd
copy to firmware/sp_vision_config/simulation/apf27_test_pkg.vhd
index 70c460e..232cdbd 100644
--- a/firmware/wishbone_example/testbench/apf_test_pkg.vhd
+++ b/firmware/sp_vision_config/simulation/apf27_test_pkg.vhd
@@ -1,6 +1,6 @@
----------------------------------------------
--- Design Name : Test bench utils
--- File Name : apf_test_pkg.vhd
+-- Design Name : Test bench utils for apf27
+-- File Name : apf27_test_pkg.vhd
-- Function : Defines communication functions between imx and fpga
-- Author : Fabien Marteau <fab...@ar...>
-- Version : 1.00
@@ -25,7 +25,13 @@
library ieee;
use ieee.std_logic_1164.all;
-package apf_test_pkg is
+package apf27_test_pkg is
+
+ CONSTANT CS_MIN : time := 13.6 ns;
+ CONSTANT CLOCK_PERIOD : time := 7.5188 ns;
+ CONSTANT WE3 : time := 2.25 ns;
+ CONSTANT WE4 : time := 2.25 ns;
+
-- write procedures
-- Params :
-- address : Write address
@@ -74,9 +80,9 @@ procedure imx_read(
);
-end package apf_test_pkg;
+end package apf27_test_pkg;
-package body apf_test_pkg is
+package body apf27_test_pkg is
-- Write value from imx
@@ -130,23 +136,22 @@ procedure imx_read(
begin
-- Read value
wait until falling_edge(gls_clk);
- wait for 4 ns;
+ wait for WE3;
imx_address <= address(12 downto 1);
imx_cs_n <= '0';
imx_oe_n <= '0';
- if WSC <= 1 then
- wait until falling_edge(gls_clk);
- else
- for n in 1 to WSC loop
+ wait for CS_MIN; -- minimum chip select time
+ if WSC > 1 then
+ for n in 2 to WSC loop
wait until falling_edge(gls_clk);
end loop;
+ --wait for CLOCK_PERIOD*(WSC-1);
end if;
- wait until falling_edge(gls_clk);
+ wait for WE4;
value <= imx_data;
imx_cs_n <= '1';
imx_oe_n <= '1';
imx_address <= (others => 'Z');
- wait for 20 ns;
end procedure imx_read;
-end package body apf_test_pkg;
+end package body apf27_test_pkg;
diff --git a/firmware/wishbone_example/src/wishbone_wrapper.vhd b/firmware/sp_vision_config/synthesis/imx27_wb16_wrapper/imx27_wb16_wrapper.vhd
similarity index 58%
copy from firmware/wishbone_example/src/wishbone_wrapper.vhd
copy to firmware/sp_vision_config/synthesis/imx27_wb16_wrapper/imx27_wb16_wrapper.vhd
index d23110b..9f3aac2 100644
--- a/firmware/wishbone_example/src/wishbone_wrapper.vhd
+++ b/firmware/sp_vision_config/synthesis/imx27_wb16_wrapper/imx27_wb16_wrapper.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- File : wishbone_wrapper.vhd
+-- File : imx27_wb16_wrapper.vhd
-- Related files : (none)
--
-- Author(s) : Fabrice Mousset (fab...@la...)
@@ -23,32 +23,34 @@ library IEEE;
use IEEE.numeric_std.all;
-- ----------------------------------------------------------------------------
- Entity wishbone_wrapper is
+ Entity imx27_wb16_wrapper is
-- ----------------------------------------------------------------------------
port
(
-- i.MX Signals
- imx_address : in std_logic_vector(11 downto 0); -- LSB not used
+ imx_address : in std_logic_vector(11 downto 0);
imx_data : inout std_logic_vector(15 downto 0);
imx_cs_n : in std_logic;
imx_oe_n : in std_logic;
- imx_eb3_n : in std_logic;
+ imx_eb0_n : in std_logic;
+
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
+
-- Wishbone interface signals
wbm_address : out std_logic_vector(12 downto 0); -- Address bus
- wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
+ wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
wbm_strobe : out std_logic; -- Data Strobe
wbm_write : out std_logic; -- Write access
- wbm_ack : in std_logic ; -- acknowledge
+ wbm_ack : in std_logic; -- acknowledge
wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
-- ----------------------------------------------------------------------------
- Architecture RTL of wishbone_wrapper is
+ Architecture RTL of imx27_wb16_wrapper is
-- ----------------------------------------------------------------------------
signal write : std_logic;
@@ -59,32 +61,32 @@ signal address : std_logic_vector(12 downto 0);
begin
--- ----------------------------------------------------------------------------
--- External signals synchronization process
--- ----------------------------------------------------------------------------
-process(gls_clk, gls_reset)
-begin
- if(gls_reset='1') then
- write <= '0';
- read <= '0';
- strobe <= '0';
- writedata <= (others => '0');
- address <= (others => '0');
- elsif(rising_edge(gls_clk)) then
- strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb3_n);
- write <= not (imx_cs_n or imx_eb3_n);
- read <= not (imx_cs_n or imx_oe_n);
- address <= imx_address & '0';
- writedata <= imx_data;
- end if;
-end process;
-
-wbm_address <= address when (strobe = '1') else (others => '0');
-wbm_writedata <= writedata when (write = '1') else (others => '0');
-wbm_strobe <= strobe;
-wbm_write <= write;
-wbm_cycle <= strobe;
+ -- ----------------------------------------------------------------------------
+ -- External signals synchronization process
+ -- ----------------------------------------------------------------------------
+ process(gls_clk, gls_reset)
+ begin
+ if(gls_reset='1') then
+ write <= '0';
+ read <= '0';
+ strobe <= '0';
+ writedata <= (others => '0');
+ address <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb0_n);
+ write <= not (imx_cs_n or imx_eb0_n);
+ read <= not (imx_cs_n or imx_oe_n);
+ address <= imx_address & '0';
+ writedata <= imx_data;
+ end if;
+ end process;
+
+ wbm_address <= address when (strobe = '1') else (others => '0');
+ wbm_writedata <= writedata when (write = '1') else (others => '0');
+ wbm_strobe <= strobe;
+ wbm_write <= write;
+ wbm_cycle <= strobe;
-imx_data <= wbm_readdata when(read = '1' ) else (others => 'Z');
+ imx_data <= wbm_readdata when (read = '1') else (others => 'Z');
end architecture RTL;
diff --git a/firmware/sp_vision_config/synthesis/imx27_wb16_wrapper00_mwb16/imx27_wb16_wrapper00_mwb16_intercon.vhd b/firmware/sp_vision_config/synthesis/imx27_wb16_wrapper00_mwb16/imx27_wb16_wrapper00_mwb16_intercon.vhd
new file mode 100644
index 0000000..52e2ad0
--- /dev/null
+++ b/firmware/sp_vision_config/synthesis/imx27_wb16_wrapper00_mwb16/imx27_wb16_wrapper00_mwb16_intercon.vhd
@@ -0,0 +1,102 @@
+---------------------------------------------------------------------------
+-- Company : Automaticaly generated by POD
+-- Author(s) :
+--
+-- Creation Date : 2010-10-21
+-- File : imx27_wb16_wrapper00_mwb16.vhd
+--
+-- Abstract :
+-- Connect slaves to mwb16 from imx27_wb16_wrapper00
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+Entity imx27_wb16_wrapper00_mwb16 is
+ port
+ (
+
+ -- spartanconf_wbs connection
+ spartanconf_wbs_add : out std_logic_vector(1 downto 0);
+ spartanconf_wbs_writedata : out std_logic_vector(15 downto 0);
+ spartanconf_wbs_readdata : in std_logic_vector(15 downto 0);
+ spartanconf_wbs_strobe : out std_logic;
+ spartanconf_wbs_cycle : out std_logic;
+ spartanconf_wbs_write : out std_logic;
+ spartanconf_wbs_ack : in std_logic;
+
+ -- spartanconf_candr connection
+ spartanconf_clk : out std_logic;
+ spartanconf_reset : out std_logic;
+
+ -- imx27_wb16_wrapper00_mwb16 connection
+ imx27_wb16_wrapper00_wbm_address : in std_logic_vector(12 downto 0);
+ imx27_wb16_wrapper00_wbm_readdata : out std_logic_vector(15 downto 0);
+ imx27_wb16_wrapper00_wbm_writedata : in std_logic_vector(15 downto 0);
+ imx27_wb16_wrapper00_wbm_strobe : in std_logic;
+ imx27_wb16_wrapper00_wbm_write : in std_logic;
+ imx27_wb16_wrapper00_wbm_ack : out std_logic;
+ imx27_wb16_wrapper00_wbm_cycle : in std_logic;
+
+ -- imx27_wb16_wrapper00_candr connection
+ imx27_wb16_wrapper00_gls_reset : out std_logic;
+ imx27_wb16_wrapper00_gls_clk : out std_logic;
+
+ -- rstgen_syscon00_imx27_wb16_wrapper00 connection
+ rstgen_syscon00_gls_clk : in std_logic;
+ rstgen_syscon00_gls_reset : in std_logic
+ );
+end entity;
+
+architecture imx27_wb16_wrapper00_mwb16_1 of imx27_wb16_wrapper00_mwb16 is
+ signal spartanconf_wbs_cs : std_logic := '0' ;
+begin
+
+ -- Clock and Reset connection
+ spartanconf_clk <= rstgen_syscon00_gls_clk;
+ spartanconf_reset <= rstgen_syscon00_gls_reset;
+
+ imx27_wb16_wrapper00_gls_reset <= rstgen_syscon00_gls_reset;
+ imx27_wb16_wrapper00_gls_clk <= rstgen_syscon00_gls_clk;
+
+
+ -- Address decoding --
+ -----------------------
+ spartanconf_wbs_add <= imx27_wb16_wrapper00_wbm_address(2 downto 1);
+
+ decodeproc : process(rstgen_syscon00_gls_clk,rstgen_syscon00_gls_reset,imx27_wb16_wrapper00_wbm_address)
+ begin
+ if rstgen_syscon00_gls_reset='1' then
+ spartanconf_wbs_cs <= '0';
+ elsif rising_edge(rstgen_syscon00_gls_clk) then
+
+ if imx27_wb16_wrapper00_wbm_address(12 downto 3)="0000000000" and imx27_wb16_wrapper00_wbm_strobe='1' then
+ spartanconf_wbs_cs <= '1';
+ else
+ spartanconf_wbs_cs <= '0';
+ end if;
+
+ end if;
+ end process decodeproc;
+
+ -----------------------------
+ -- Control signals to slave
+ -----------------------------
+
+ -- for spartanconf
+ spartanconf_wbs_strobe <= (imx27_wb16_wrapper00_wbm_strobe and spartanconf_wbs_cs );
+ spartanconf_wbs_cycle <= (imx27_wb16_wrapper00_wbm_cycle and spartanconf_wbs_cs );
+ spartanconf_wbs_write <= (imx27_wb16_wrapper00_wbm_write and spartanconf_wbs_cs );
+ spartanconf_wbs_writedata <= imx27_wb16_wrapper00_wbm_writedata when (imx27_wb16_wrapper00_wbm_write and spartanconf_wbs_cs ) = '1' else (others => '0');
+
+
+ -------------------------------
+ -- Control signal for master --
+ -------------------------------
+ imx27_wb16_wrapper00_wbm_readdata <= spartanconf_wbs_readdata when spartanconf_wbs_cs='1' else
+ (others => '0');
+ imx27_wb16_wrapper00_wbm_ack <= (spartanconf_wbs_ack and spartanconf_wbs_cs);
+
+end architecture imx27_wb16_wrapper00_mwb16_1;
diff --git a/firmware/wishbone_example/src/rstgen_syscon.vhd b/firmware/sp_vision_config/synthesis/rstgen_syscon/rstgen_syscon.vhd
similarity index 100%
copy from firmware/wishbone_example/src/rstgen_syscon.vhd
copy to firmware/sp_vision_config/synthesis/rstgen_syscon/rstgen_syscon.vhd
diff --git a/firmware/sp_vision_config/synthesis/spartan_select_map/spartan_selectmap.vhd b/firmware/sp_vision_config/synthesis/spartan_select_map/spartan_selectmap.vhd
new file mode 100644
index 0000000..e2059db
--- /dev/null
+++ b/firmware/sp_vision_config/synthesis/spartan_select_map/spartan_selectmap.vhd
@@ -0,0 +1,211 @@
+---------------------------------------------------------------------------
+-- Company : ARMades Systems
+-- Author(s) : Fabien Marteau <fab...@ar...>
+--
+-- Creation Date : 05/01/2011
+-- File : spartan_select_map.vhd
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity spartan_select_map is
+---------------------------------------------------------------------------
+ generic(
+ id : natural := 1; -- identification register value
+ wb_size : natural := 16; -- Data port size for wishbone
+ clk_freq : natural := 100000 -- fpga clock speed
+ );
+ port
+ (
+ -- Syscon signals
+ reset : in std_logic ; -- reset
+ clk : in std_logic ; -- general clock
+ -- Wishbone signals
+ wbs_add : in std_logic_vector( 1 downto 0) ; -- address bus
+ wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
+ wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_cycle : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- selectMap port
+ selectmap_data : inout std_logic_vector( wb_size-1 downto 0);
+ selectmap_csi_n : inout std_logic ;
+ selectmap_rdwr_n : inout std_logic ;
+ selectmap_cclk : inout std_logic ;
+ selectmap_program_n : inout std_logic ;
+ selectmap_init_n : in std_logic ;
+ selectmap_busy : in std_logic ;
+ selectmap_done : in std_logic;
+
+ selectmap_spare1 : in std_logic;
+ selectmap_spare2 : in std_logic;
+ selectmap_spare3 : in std_logic
+ );
+end entity;
+
+---------------------------------------------------------------------------
+Architecture spartan_select_map_1 of spartan_select_map is
+---------------------------------------------------------------------------
+ -- usefull constant
+ constant ZERO : std_logic_vector(15 downto 0) := x"0000";
+ constant CLK_PULSE_LENGHT : natural := 200;
+
+ -- Registers addresses
+ constant ID_REG_ADDR : std_logic_vector( 1 downto 0) := "00";
+ constant CONFIG_REG_ADDR : std_logic_vector( 1 downto 0) := "01";
+ constant STATUS_REG_ADDR : std_logic_vector( 1 downto 0) := "10";
+ constant DATA_REG_ADDR : std_logic_vector( 1 downto 0) := "11";
+ -- Registers
+ signal config_reg : std_logic_vector( wb_size-1 downto 0);
+ signal status_reg : std_logic_vector( wb_size-1 downto 0);
+ signal data_reg : std_logic_vector( wb_size-1 downto 0);
+
+ -- internal ctrl signals
+ signal read_ack : std_logic ;
+ signal write_ack: std_logic ;
+
+ signal cclk_sig : std_logic ;
+ signal cclk_trig : std_logic ;
+
+ signal clk_out : std_logic ;
+
+ signal data_inverter : std_logic_vector( wb_size-1 downto 0);
+
+ constant COUNT_CST : natural := 2;
+begin
+
+ clk_out <= clk;
+
+ -- config_reg:
+ -- |15|14|13|12|11|10|9|8|7|6|5| 4 |3| 2 | 1 | 0 |
+ -- |X |X |X |X |X |X |X|X|X|X|X|CLK|X|CSI_n|PROGRAM_n|RDWR_n|
+ -- If CLK=1, system clock is routed on CCLK and all configuration output
+ -- are high Z
+ selectmap_rdwr_n <= config_reg(0) when config_reg(4) = '0' else 'Z';
+ selectmap_program_n <= config_reg(1) when config_reg(4) = '0' else 'Z';
+ selectmap_csi_n <= config_reg(2) when config_reg(4) = '0' else 'Z';
+ selectmap_cclk <= cclk_sig when config_reg(4) = '0' else clk_out;
+ data_inverter <= data_reg when config_reg(4) = '0' else (others => 'Z');
+
+ selectmap_data(0) <= data_inverter(7);
+ selectmap_data(1) <= data_inverter(6);
+ selectmap_data(2) <= data_inverter(5);
+ selectmap_data(3) <= data_inverter(4);
+ selectmap_data(4) <= data_inverter(3);
+ selectmap_data(5) <= data_inverter(2);
+ selectmap_data(6) <= data_inverter(1);
+ selectmap_data(7) <= data_inverter(0);
+
+ selectmap_data(8) <= data_inverter(15);
+ selectmap_data(9) <= data_inverter(14);
+ selectmap_data(10) <= data_inverter(13);
+ selectmap_data(11) <= data_inverter(12);
+ selectmap_data(12) <= data_inverter(11);
+ selectmap_data(13) <= data_inverter(10);
+ selectmap_data(14) <= data_inverter(9);
+ selectmap_data(15) <= data_inverter(8);
+
+ -- Status register
+ -- | 15 | 14 | 13 |12|11|10|9|8|7|6|5|4|3| 2 | 1 | 0 |
+ -- |spare1|spare2|spare3 |X |X |X |X|X|X|X|X|X|X|INIT_n|BUSY|DONE|
+ status_reg <= selectmap_spare1&selectmap_spare2&selectmap_spare3&ZERO(12 downto 3)&selectmap_init_n&selectmap_busy&selectmap_done;
+
+ -- read process
+ read_p : process (clk, reset)
+ begin
+ if reset = '1' then
+ wbs_readdata <= (others => '0');
+ elsif rising_edge(clk) then
+ if ( wbs_strobe and (not wbs_write) and wbs_cycle) = '1' then
+ read_ack <= '1';
+ case wbs_add is
+ when ID_REG_ADDR =>
+ wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
+ when CONFIG_REG_ADDR =>
+ wbs_readdata <= config_reg;
+ when STATUS_REG_ADDR =>
+ wbs_readdata <= status_reg;
+ when DATA_REG_ADDR =>
+ wbs_readdata <= data_reg;
+ when others =>
+ wbs_readdata <= ZERO;
+ end case;
+ else
+ read_ack <= '0';
+ wbs_readdata <= (others => '0');
+ end if;
+ end if;
+ end process read_p;
+
+ -- write process
+ write_p : process (clk, reset)
+ begin
+ if reset = '1' then
+ config_reg <= x"0007";
+ data_reg <= (others => '0');
+ elsif rising_edge(clk) then
+ write_ack <= '0';
+ if (wbs_strobe and wbs_write and wbs_cycle) = '1' then
+ write_ack <= '1';
+ case wbs_add is
+ when CONFIG_REG_ADDR =>
+ config_reg <= wbs_writedata;
+ data_reg <= data_reg;
+ when DATA_REG_ADDR =>
+ config_reg <= config_reg;
+ data_reg <= wbs_writedata;
+ when others =>
+ config_reg <= config_reg;
+ data_reg <= data_reg;
+ end case;
+ end if;
+ end if;
+ end process write_p;
+
+ -- CCLK trigger generator
+ cclk_p : process (clk, reset)
+ begin
+ if reset = '1' then
+ cclk_trig <= '0';
+ elsif rising_edge(clk) then
+ if wbs_add = DATA_REG_ADDR then
+ cclk_trig <= '1';
+ else
+ cclk_trig <= '0';
+ end if;
+ end if;
+ end process cclk_p;
+
+ cclk_gen : process (clk, reset)
+ variable counter : natural range 0 to (CLK_PULSE_LENGHT+1);
+ begin
+ if reset = '1' then
+ cclk_sig <= '0';
+ counter := 0;
+ elsif rising_edge(clk) then
+ if cclk_trig = '1' then
+ counter := 0;
+ cclk_sig <= '0';
+ elsif counter < (CLK_PULSE_LENGHT/2) then
+ counter := counter +1;
+ cclk_sig <= '0';
+ elsif counter < (CLK_PULSE_LENGHT) then
+ counter := counter +1;
+ cclk_sig <= '1';
+ else
+ cclk_sig <= '0';
+ end if;
+ end if;
+ end process cclk_gen;
+
+
+
+ wbs_ack <= read_ack or write_ack;
+
+end architecture spartan_select_map_1;
+
diff --git a/firmware/sp_vision_config/synthesis/testconfig.tcl b/firmware/sp_vision_config/synthesis/testconfig.tcl
new file mode 100644
index 0000000..4df3fec
--- /dev/null
+++ b/firmware/sp_vision_config/synthesis/testconfig.tcl
@@ -0,0 +1,21 @@
+# TCL script automaticaly generated by POD
+cd ../objs
+project new testconfig.ise
+# configure platform params
+project set family spartan3a
+project set device XC3S200A
+project set package FT256
+project set speed -4
+project set {Preferred Language} VHDL
+## add components sources file
+# add top level sources file
+xfile add ../synthesis/top_testconfig.vhd
+xfile add ../synthesis/imx27_wb16_wrapper/imx27_wb16_wrapper.vhd
+xfile add ../synthesis/rstgen_syscon/rstgen_syscon.vhd
+xfile add ../synthesis/imx27_wb16_wrapper00_mwb16/imx27_wb16_wrapper00_mwb16_intercon.vhd
+xfile add ../synthesis/spartan_select_map/spartan_selectmap.vhd
+# add constraint file
+xfile add ../synthesis/testconfig.ucf
+process run "Generate Programming File"
+process run "Generate Post-Synthesis Simulation Model"
+process run "Generate Post-Place & Route Simulation Model"
diff --git a/firmware/sp_vision_config/synthesis/testconfig.ucf b/firmware/sp_vision_config/synthesis/testconfig.ucf
new file mode 100644
index 0000000..d379ef0
--- /dev/null
+++ b/firmware/sp_vision_config/synthesis/testconfig.ucf
@@ -0,0 +1,69 @@
+# Constraint file, automaticaly generated by pod
+NET "imx27_wb16_wrapper00_imx_cs_n" LOC="P10" | IOSTANDARD=LVCMOS18;# CS5N
+
+NET "imx27_wb16_wrapper00_imx_data<0>" LOC="T5" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA0
+NET "imx27_wb16_wrapper00_imx_data<1>" LOC="T6" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA1
+NET "imx27_wb16_wrapper00_imx_data<2>" LOC="P7" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA2
+NET "imx27_wb16_wrapper00_imx_data<3>" LOC="N8" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA3
+NET "imx27_wb16_wrapper00_imx_data<4>" LOC="P12" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA4
+NET "imx27_wb16_wrapper00_imx_data<5>" LOC="T13" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA5
+NET "imx27_wb16_wrapper00_imx_data<6>" LOC="R13" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA6
+NET "imx27_wb16_wrapper00_imx_data<7>" LOC="T14" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA7
+NET "imx27_wb16_wrapper00_imx_data<8>" LOC="P5" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA8
+NET "imx27_wb16_wrapper00_imx_data<9>" LOC="N6" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA9
+NET "imx27_wb16_wrapper00_imx_data<10>" LOC="T3" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA10
+NET "imx27_wb16_wrapper00_imx_data<11>" LOC="T11" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA11
+NET "imx27_wb16_wrapper00_imx_data<12>" LOC="T4" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA12
+NET "imx27_wb16_wrapper00_imx_data<13>" LOC="R5" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA13
+NET "imx27_wb16_wrapper00_imx_data<14>" LOC="M10" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA14
+NET "imx27_wb16_wrapper00_imx_data<15>" LOC="T10" | IOSTANDARD=LVCMOS18 | DRIVE=8;# DATA15
+
+NET "rstgen_syscon00_ext_clk" LOC="N9" | IOSTANDARD=LVCMOS18;# CLK0
+NET "rstgen_syscon00_ext_clk" TNM_NET = "rstgen_syscon00_ext_clk";
+TIMESPEC "TS_rstgen_syscon00_ext_clk" = PERIOD "rstgen_syscon00_ext_clk" 10 ns HIGH 50 %;
+
+NET "imx27_wb16_wrapper00_imx_eb0_n" LOC="P9" | IOSTANDARD=LVCMOS18;# EB0N
+NET "imx27_wb16_wrapper00_imx_oe_n" LOC="R9" | IOSTANDARD=LVCMOS18;# OEN
+
+NET "imx27_wb16_wrapper00_imx_address<0>" LOC="N5" | IOSTANDARD=LVCMOS18; # ADDR1
+NET "imx27_wb16_wrapper00_imx_address<1>" LOC="L7" | IOSTANDARD=LVCMOS18; # ADDR2
+NET "imx27_wb16_wrapper00_imx_address<2>" LOC="M7" | IOSTANDARD=LVCMOS18; # ADDR3
+NET "imx27_wb16_wrapper00_imx_address<3>" LOC="M8" | IOSTANDARD=LVCMOS18; # ADDR4
+NET "imx27_wb16_wrapper00_imx_address<4>" LOC="L8" | IOSTANDARD=LVCMOS18; # ADDR5
+NET "imx27_wb16_wrapper00_imx_address<5>" LOC="L9" | IOSTANDARD=LVCMOS18; # ADDR6
+NET "imx27_wb16_wrapper00_imx_address<6>" LOC="L10" | IOSTANDARD=LVCMOS18; # ADDR7
+NET "imx27_wb16_wrapper00_imx_address<7>" LOC="M11" | IOSTANDARD=LVCMOS18; # ADDR8
+NET "imx27_wb16_wrapper00_imx_address<8>" LOC="P11" | IOSTANDARD=LVCMOS18; # ADDR9
+NET "imx27_wb16_wrapper00_imx_address<9>" LOC="N11" | IOSTANDARD=LVCMOS18; # ADDR10
+NET "imx27_wb16_wrapper00_imx_address<10>" LOC="N12" | IOSTANDARD=LVCMOS18; # ADDR11
+NET "imx27_wb16_wrapper00_imx_address<11>" LOC="P13" | IOSTANDARD=LVCMOS18; # ADDR12
+
+NET "spartanconf_selectmap_data<1>" LOC="D13" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L01P_0
+NET "spartanconf_selectmap_data<0>" LOC="C13" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L01N_0
+NET "spartanconf_selectmap_data<8>" LOC="B15" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L02P_0
+NET "spartanconf_selectmap_data<9>" LOC="B14" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L02N_0
+NET "spartanconf_selectmap_data<6>" LOC="A14" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L04P_0
+NET "spartanconf_selectmap_data<7>" LOC="A13" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L04N_0
+NET "spartanconf_selectmap_data<2>" LOC="C9" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L10P_0
+NET "spartanconf_selectmap_data<3>" LOC="A9" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L10N_0
+NET "spartanconf_selectmap_data<11>" LOC="A8" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L12P_0
+NET "spartanconf_selectmap_data<10>" LOC="B8" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L12N_0
+NET "spartanconf_selectmap_data<4>" LOC="B10" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L08P_0
+NET "spartanconf_selectmap_data<5>" LOC="A10" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L08N_0
+NET "spartanconf_selectmap_data<13>" LOC="D7" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L16P_0
+NET "spartanconf_selectmap_data<12>" LOC="C6" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L16N_0
+NET "spartanconf_selectmap_data<15>" LOC="A4" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L18P_0
+NET "spartanconf_selectmap_data<14>" LOC="B4" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L18N_0
+NET "spartanconf_selectmap_busy" LOC="B3" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L19N_0
+NET "spartanconf_selectmap_init_n" LOC="E14" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L20P_1
+NET "spartanconf_selectmap_csi_n" LOC="F13" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L20N_1
+NET "spartanconf_selectmap_done" LOC="D16" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L22P_1
+NET "spartanconf_selectmap_cclk" LOC="D15" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L22N_1
+NET "spartanconf_selectmap_rdwr_n" LOC="E13" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L23P_1
+NET "spartanconf_selectmap_program_n" LOC="D14" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L23N_1
+
+NET "spartanconf_selectmap_spare1" LOC="C2" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L01P_3
+NET "spartanconf_selectmap_spare2" LOC="D4" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L02P_3
+NET "spartanconf_selectmap_spare3" LOC="D1" | IOSTANDARD=LVCMOS18 | DRIVE=8; # IO_L03P_3
+
+#end
diff --git a/firmware/sp_vision_config/synthesis/top_testconfig.vhd b/firmware/sp_vision_config/synthesis/top_testconfig.vhd
new file mode 100644
index 0000000..d93df01
--- /dev/null
+++ b/firmware/sp_vision_config/synthesis/top_testconfig.vhd
@@ -0,0 +1,372 @@
+---------------------------------------------------------------------------
+-- Company : Automaticaly generated by POD
+-- Author(s) :
+--
+-- Creation Date : 2010-10-21
+-- File : Top_testconfig.vhd
+--
+-- Abstract :
+-- insert a description here
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+entity top_testconfig is
+
+ port
+ (
+ -- imx27_wb16_wrapper00-eim
+ imx27_wb16_wrapper00_imx_cs_n : in std_logic;
+ -- imx27_wb16_wrapper00-eim
+ imx27_wb16_wrapper00_imx_data : inout std_logic_vector(15 downto 0);
+ -- rstgen_syscon00-clk_ext
+ rstgen_syscon00_ext_clk : in std_logic;
+ -- imx27_wb16_wrapper00-eim
+ imx27_wb16_wrapper00_imx_eb0_n : in std_logic;
+ -- imx27_wb16_wrapper00-eim
+ imx27_wb16_wrapper00_imx_oe_n : in std_logic;
+ -- imx27_wb16_wrapper00-eim
+ imx27_wb16_wrapper00_imx_address : in std_logic_vector(11 downto 0);
+ -- spartanconf-selectmap
+ spartanconf_selectmap_data : inout std_logic_vector(15 downto 0);
+ -- spartanconf-selectmap
+ spartanconf_selectmap_busy : in std_logic;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_init_n : in std_logic;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_csi_n : inout std_logic;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_done : in std_logic;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_cclk : inout std_logic;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_rdwr_n : inout std_logic;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_program_n : inout std_logic;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_spare1 : in std_logic ;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_spare2 : in std_logic ;
+ -- spartanconf-selectmap
+ spartanconf_selectmap_spare3 : in std_logic
+
+ );
+end entity top_testconfig;
+
+architecture top_testconfig_1 of top_testconfig is
+ -------------------------
+ -- declare components --
+ -------------------------
+
+
+ component imx27_wb16_wrapper00_mwb16
+ port (
+ -- spartanconf_wbs
+ spartanconf_wbs_add : out std_logic_vector(1 downto 0);
+ spartanconf_wbs_writedata : out std_logic_vector(15 downto 0);
+ spartanconf_wbs_readdata : in std_logic_vector(15 downto 0);
+ spartanconf_wbs_strobe : out std_logic;
+ spartanconf_wbs_cycle : out std_logic;
+ spartanconf_wbs_write : out std_logic;
+ spartanconf_wbs_ack : in std_logic;
+ -- spartanconf_candr
+ spartanconf_clk : out std_logic;
+ spartanconf_reset : out std_logic;
+ -- imx27_wb16_wrapper00_mwb16
+ imx27_wb16_wrapper00_wbm_address : in std_logic_vector(12 downto 0);
+ imx27_wb16_wrapper00_wbm_readdata : out std_logic_vector(15 downto 0);
+ imx27_wb16_wrapper00_wbm_writedata : in std_logic_vector(15 downto 0);
+ imx27_wb16_wrapper00_wbm_strobe : in std_logic;
+ imx27_wb16_wrapper00_wbm_write : in std_logic;
+ imx27_wb16_wrapper00_wbm_ack : out std_logic;
+ imx27_wb16_wrapper00_wbm_cycle : in std_logic;
+ -- imx27_wb16_wrapper00_candr
+ imx27_wb16_wrapper00_gls_reset : out std_logic;
+ imx27_wb16_wrapper00_gls_clk : out std_logic;
+ -- rstgen_syscon00_imx27_wb16_wrapper00
+ rstgen_syscon00_gls_clk : in std_logic;
+ rstgen_syscon00_gls_reset : in std_logic
+ );
+ end component;
+
+ component spartan_select_map
+ generic(
+ id : natural := 1;
+ wb_size : natural := 16;
+ clk_freq : natural := 100000
+ );
+ port (
+ -- candr
+ clk : in std_logic;
+ reset : in std_logic;
+ -- wbs
+ wbs_add : in std_logic_vector(1 downto 0);
+ wbs_writedata : in std_logic_vector(15 downto 0);
+ wbs_readdata : out std_logic_vector(15 downto 0);
+ wbs_strobe : in std_logic;
+ wbs_cycle : in std_logic;
+ wbs_write : in std_logic;
+ wbs_ack : out std_logic;
+ -- selectmap
+ selectmap_data : inout std_logic_vector(15 downto 0);
+ selectmap_csi_n : inout std_logic;
+ selectmap_rdwr_n : inout std_logic;
+ selectmap_cclk : inout std_logic;
+ selectmap_program_n : inout std_logic;
+ selectmap_init_n: in std_logic;
+ selectmap_busy : in std_logic;
+ selectmap_done : in std_logic;
+ selectmap_spare1: in std_logic;
+ selectmap_spare2: in std_logic;
+ selectmap_spare3: in std_logic
+ );
+ end component;
+
+ component imx27_wb16_wrapper
+ port (
+ -- eim
+ imx_address : in std_logic_vector(11 downto 0);
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_oe_n : in std_logic;
+ imx_eb0_n : in std_logic;
+ -- candr
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
+ -- mwb16
+ wbm_address : out std_logic_vector(12 downto 0);
+ wbm_readdata : in std_logic_vector(15 downto 0);
+ wbm_writedata : out std_logic_vector(15 downto 0);
+ wbm_strobe : out std_logic;
+ wbm_write : out std_logic;
+ wbm_ack : in std_logic;
+ wbm_cycle : out std_logic
+ );
+ end component;
+
+ component rstgen_syscon
+ port (
+ -- candr
+ gls_clk : out std_logic;
+ gls_reset : out std_logic;
+ -- clk_ext
+ ext_clk : in std_logic
+ );
+ end component;
+ -------------------------
+ -- Signals declaration
+ -------------------------
+
+ -- imx27_wb16_wrapper00
+ -- eim
+ -- candr
+ signal imx27_wb16_wrapper00_gls_reset : std_logic;
+ signal imx27_wb16_wrapper00_gls_clk : std_logic;
+ -- mwb16
+ signal imx27_wb16_wrapper00_wbm_address : std_logic_vector(12 downto 0);
+ signal imx27_wb16_wrapper00_wbm_readdata : std_logic_vector(15 downto 0);
+ signal imx27_wb16_wrapper00_wbm_writedata : std_logic_vector(15 downto 0);
+ signal imx27_wb16_wrapper00_wbm_strobe : std_logic;
+ signal imx27_wb16_wrapper00_wbm_write : std_logic;
+ signal imx27_wb16_wrapper00_wbm_ack : std_logic;
+ signal imx27_wb16_wrapper00_wbm_cycle : std_logic;
+
+ -- rstgen_syscon00
+ -- candr
+ signal rstgen_syscon00_gls_clk : std_logic;
+ signal rstgen_syscon00_gls_reset : std_logic;
+ -- clk_ext
+
+ -- spartanconf
+ -- candr
+ signal spartanconf_clk : std_logic;
+ signal spartanconf_reset : std_logic;
+ -- wbs
+ signal spartanconf_wbs_add : std_logic_vector(1 downto 0);
+ signal spartanconf_wbs_writedata : std_logic_vector(15 downto 0);
+ signal spartanconf_wbs_readdata : std_logic_vector(15 downto 0);
+ signal spartanconf_wbs_strobe : std_logic;
+ signal spartanconf_wbs_cycle : std_logic;
+ signal spartanconf_wbs_write : std_logic;
+ signal spartanconf_wbs_ack : std_logic;
+ -- selectmap
+
+ -- imx27_wb16_wrapper00_mwb16_intercon
+ -- spartanconf_wbs
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_add : std_logic_vector(1 downto 0);
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_writedata : std_logic_vector(15 downto 0);
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_readdata : std_logic_vector(15 downto 0);
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_strobe : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_cycle : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_write : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_ack : std_logic;
+ -- spartanconf_candr
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_clk : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_spartanconf_reset : std_logic;
+ -- imx27_wb16_wrapper00_mwb16
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_address : std_logic_vector(12 downto 0);
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_readdata : std_logic_vector(15 downto 0);
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_writedata : std_logic_vector(15 downto 0);
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_strobe : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_write : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_ack : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_cycle : std_logic;
+ -- imx27_wb16_wrapper00_candr
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_gls_reset : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_gls_clk : std_logic;
+ -- rstgen_syscon00_imx27_wb16_wrapper00
+ signal imx27_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_clk : std_logic;
+ signal imx27_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_reset : std_logic;
+
+ -- void pins
+
+begin
+
+ -------------------
+ -- Set forces --
+ -------------------
+
+ -------------------------
+ -- declare instances
+ -------------------------
+
+ imx27_wb16_wrapper00 : imx27_wb16_wrapper
+ port map (
+ -- eim
+ imx_address => imx27_wb16_wrapper00_imx_address,
+ imx_data => imx27_wb16_wrapper00_imx_data,
+ imx_cs_n => imx27_wb16_wrapper00_imx_cs_n,
+ imx_oe_n => imx27_wb16_wrapper00_imx_oe_n,
+ imx_eb0_n => imx27_wb16_wrapper00_imx_eb0_n,
+ -- candr
+ gls_reset => imx27_wb16_wrapper00_gls_reset,
+ gls_clk => imx27_wb16_wrapper00_gls_clk,
+ -- mwb16
+ wbm_address => imx27_wb16_wrapper00_wbm_address,
+ wbm_readdata => imx27_wb16_wrapper00_wbm_readdata,
+ wbm_writedata => imx27_wb16_wrapper00_wbm_writedata,
+ wbm_strobe => imx27_wb16_wrapper00_wbm_strobe,
+ wbm_write => imx27_wb16_wrapper00_wbm_write,
+ wbm_ack => imx27_wb16_wrapper00_wbm_ack,
+ wbm_cycle => imx27_wb16_wrapper00_wbm_cycle
+ );
+
+ rstgen_syscon00 : rstgen_syscon
+ port map (
+ -- candr
+ gls_clk => rstgen_syscon00_gls_clk,
+ gls_reset => rstgen_syscon00_gls_reset,
+ -- clk_ext
+ ext_clk => rstgen_syscon00_ext_clk
+ );
+
+ spartanconf : spartan_select_map
+ generic map (
+ id => 1,
+ wb_size => 16,
+ clk_freq => 100000
+ )
+ port map (
+ -- candr
+ clk => spartanconf_clk,
+ reset => spartanconf_reset,
+ -- wbs
+ wbs_add => spartanconf_wbs_add,
+ wbs_writedata => spartanconf_wbs_writedata,
+ wbs_readdata => spartanconf_wbs_readdata,
+ wbs_strobe => spartanconf_wbs_strobe,
+ wbs_cycle => spartanconf_wbs_cycle,
+ wbs_write => spartanconf_wbs_write,
+ wbs_ack => spartanconf_wbs_ack,
+ -- selectmap
+ selectmap_data => spartanconf_selectmap_data,
+ selectmap_csi_n => spartanconf_selectmap_csi_n,
+ selectmap_rdwr_n => spartanconf_selectmap_rdwr_n,
+ selectmap_cclk => spartanconf_selectmap_cclk,
+ selectmap_program_n => spartanconf_selectmap_program_n,
+ selectmap_init_n => spartanconf_selectmap_init_n,
+ selectmap_busy => spartanconf_selectmap_busy,
+ selectmap_done => spartanconf_selectmap_done,
+ selectmap_spare1 => spartanconf_selectmap_spare1,
+ selectmap_spare2 => spartanconf_selectmap_spare2,
+ selectmap_spare3 => spartanconf_selectmap_spare3
+ );
+
+ imx27_wb16_wrapper00_mwb16_intercon : imx27_wb16_wrapper00_mwb16
+ port map (
+ -- spartanconf_wbs
+ spartanconf_wbs_add => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_add,
+ spartanconf_wbs_writedata => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_writedata,
+ spartanconf_wbs_readdata => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_readdata,
+ spartanconf_wbs_strobe => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_strobe,
+ spartanconf_wbs_cycle => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_cycle,
+ spartanconf_wbs_write => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_write,
+ spartanconf_wbs_ack => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_ack,
+ -- spartanconf_candr
+ spartanconf_clk => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_clk,
+ spartanconf_reset => imx27_wb16_wrapper00_mwb16_intercon_spartanconf_reset,
+ -- imx27_wb16_wrapper00_mwb16
+ imx27_wb16_wrapper00_wbm_address => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_address,
+ imx27_wb16_wrapper00_wbm_readdata => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_readdata,
+ imx27_wb16_wrapper00_wbm_writedata => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_writedata,
+ imx27_wb16_wrapper00_wbm_strobe => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_strobe,
+ imx27_wb16_wrapper00_wbm_write => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_write,
+ imx27_wb16_wrapper00_wbm_ack => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_ack,
+ imx27_wb16_wrapper00_wbm_cycle => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_cycle,
+ -- imx27_wb16_wrapper00_candr
+ imx27_wb16_wrapper00_gls_reset => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_gls_reset,
+ imx27_wb16_wrapper00_gls_clk => imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_gls_clk,
+ -- rstgen_syscon00_imx27_wb16_wrapper00
+ rstgen_syscon00_gls_clk => imx27_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_clk,
+ rstgen_syscon00_gls_reset => imx27_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_reset
+ );
+
+ ---------------------------
+ -- instances connections --
+ ---------------------------
+
+ -- connect imx27_wb16_wrapper00
+ -- eim
+ -- candr
+ imx27_wb16_wrapper00_gls_reset <= imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_gls_reset;
+ imx27_wb16_wrapper00_gls_clk <= imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_gls_clk;
+ -- mwb16
+ imx27_wb16_wrapper00_wbm_readdata <= imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_readdata;
+ imx27_wb16_wrapper00_wbm_ack <= imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_ack;
+
+ -- connect rstgen_syscon00
+ -- candr
+ -- clk_ext
+
+ -- connect spartanconf
+ -- candr
+ spartanconf_clk <= imx27_wb16_wrapper00_mwb16_intercon_spartanconf_clk;
+ spartanconf_reset <= imx27_wb16_wrapper00_mwb16_intercon_spartanconf_reset;
+ -- wbs
+ spartanconf_wbs_add <= imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_add;
+ spartanconf_wbs_writedata <= imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_writedata;
+ spartanconf_wbs_strobe <= imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_strobe;
+ spartanconf_wbs_cycle <= imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_cycle;
+ spartanconf_wbs_write <= imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_write;
+ -- selectmap
+
+ -- connect imx27_wb16_wrapper00_mwb16_intercon
+ -- spartanconf_wbs
+ imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_readdata <= spartanconf_wbs_readdata;
+ imx27_wb16_wrapper00_mwb16_intercon_spartanconf_wbs_ack <= spartanconf_wbs_ack;
+ -- spartanconf_candr
+ -- imx27_wb16_wrapper00_mwb16
+ imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_address <= imx27_wb16_wrapper00_wbm_address;
+ imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_writedata <= imx27_wb16_wrapper00_wbm_writedata;
+ imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_strobe <= imx27_wb16_wrapper00_wbm_strobe;
+ imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_write <= imx27_wb16_wrapper00_wbm_write;
+ imx27_wb16_wrapper00_mwb16_intercon_imx27_wb16_wrapper00_wbm_cycle <= imx27_wb16_wrapper00_wbm_cycle;
+ -- imx27_wb16_wrapper00_candr
+ -- rstgen_syscon00_imx27_wb16_wrapper00
+ imx27_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_clk <= rstgen_syscon00_gls_clk;
+ imx27_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_reset <= rstgen_syscon00_gls_reset;
+
+end architecture top_testconfig_1;
hooks/post-receive
--
armadeus
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