[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-178-g4d6a3c3

[Fabien M <fa...@us...>]

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- Log -----------------------------------------------------------------
commit 4d6a3c36c47b62b77ba893b4174e97082c55fa0e
Author: Fabien Marteau <fab...@ar...>
Date:   Tue Dec 21 13:58:33 2010 +0100

    [u-boot] update apf51.h for weim registers configuration

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf51/apf51-u-boot-2010.03.h   |  110 ++++++++++++++++++++
 1 files changed, 110 insertions(+), 0 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
index a428a38..34d6fc3 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
@@ -591,6 +591,116 @@
 #define CONFIG_SYS_FPGA_DONE	MX51_PIN_CSI2_D13
 #define CONFIG_SYS_FPGA_SUSPEND MX51_PIN_DISPB2_SER_DIO
 
+#define	CONFIG_FPGA_GCR1_VALUE	0x019100bf
+#define	CONFIG_FPGA_GCR2_VALUE	0x00000000
+                                           
+#define	CONFIG_FPGA_RCR1_VALUE	0x04000010
+#define	CONFIG_FPGA_RCR2_VALUE	0x00000000
+                                           
+#define	CONFIG_FPGA_WCR1_VALUE	0x03000008
+#define	CONFIG_FPGA_WCR2_VALUE	0x00000000
+
+
+/*-----------------------------------------------------------------------
+ * WEIM - EIM
+ */
+/* Addresses */
+#define CONFIG_WCR_ADDR		(WEIM_BASE_ADDR + 0X90)
+#define CONFIG_WIAR_ADDR	(WEIM_BASE_ADDR + 0X94)
+#define CONFIG_EAR_ADDR		(WEIM_BASE_ADDR + 0x98)
+
+#define CONFIG_CS1GCR1_ADDR	(WEIM_BASE_ADDR + 0x18)
+#define CONFIG_CS2GCR1_ADDR	(WEIM_BASE_ADDR + 0x30)
+#define CONFIG_CS3GCR1_ADDR	(WEIM_BASE_ADDR + 0x48)
+#define CONFIG_CS4GCR1_ADDR	(WEIM_BASE_ADDR + 0x60)
+#define CONFIG_CS5GCR1_ADDR	(WEIM_BASE_ADDR + 0x78)
+
+#define CONFIG_CS1GCR2_ADDR	(WEIM_BASE_ADDR + 0x1C)
+#define CONFIG_CS2GCR2_ADDR	(WEIM_BASE_ADDR + 0x34)
+#define CONFIG_CS3GCR2_ADDR	(WEIM_BASE_ADDR + 0x4C)
+#define CONFIG_CS4GCR2_ADDR	(WEIM_BASE_ADDR + 0x64)
+#define CONFIG_CS5GCR2_ADDR	(WEIM_BASE_ADDR + 0x7C)
+
+#define CONFIG_CS1RCR1_ADDR	(WEIM_BASE_ADDR + 0x20)
+#define CONFIG_CS2RCR1_ADDR	(WEIM_BASE_ADDR + 0x38)
+#define CONFIG_CS3RCR1_ADDR	(WEIM_BASE_ADDR + 0x50)
+#define CONFIG_CS4RCR1_ADDR	(WEIM_BASE_ADDR + 0x68)
+#define CONFIG_CS5RCR1_ADDR	(WEIM_BASE_ADDR + 0x80)
+
+#define CONFIG_CS1RCR2_ADDR	(WEIM_BASE_ADDR + 0x24)
+#define CONFIG_CS2RCR2_ADDR	(WEIM_BASE_ADDR + 0x3C)
+#define CONFIG_CS3RCR2_ADDR	(WEIM_BASE_ADDR + 0x54)
+#define CONFIG_CS4RCR2_ADDR	(WEIM_BASE_ADDR + 0x6C)
+#define CONFIG_CS5RCR2_ADDR	(WEIM_BASE_ADDR + 0x84)
+
+#define CONFIG_CS1WCR1_ADDR	(WEIM_BASE_ADDR + 0x28)
+#define CONFIG_CS2WCR1_ADDR	(WEIM_BASE_ADDR + 0x40)
+#define CONFIG_CS3WCR1_ADDR	(WEIM_BASE_ADDR + 0x58)
+#define CONFIG_CS4WCR1_ADDR	(WEIM_BASE_ADDR + 0x70)
+#define CONFIG_CS5WCR1_ADDR	(WEIM_BASE_ADDR + 0x88)
+
+#define CONFIG_CS1WCR2_ADDR	(WEIM_BASE_ADDR + 0x2C)
+#define CONFIG_CS2WCR2_ADDR	(WEIM_BASE_ADDR + 0x44)
+#define CONFIG_CS3WCR2_ADDR	(WEIM_BASE_ADDR + 0x5C)
+#define CONFIG_CS4WCR2_ADDR	(WEIM_BASE_ADDR + 0x74)
+#define CONFIG_CS5WCR2_ADDR	(WEIM_BASE_ADDR + 0x8C)
+
+/* Values */
+  /* force BCLK free run */
+#define CONFIG_WCR_VALUE	0x00000021
+#define CONFIG_WIAR_VALUE	0x00000010
+
+/* CS1 */
+#define CONFIG_CS1GCR1_VALUE	CONFIG_FPGA_GCR1_VALUE
+#define CONFIG_CS1GCR2_VALUE	CONFIG_FPGA_GCR2_VALUE
+
+#define CONFIG_CS1RCR1_VALUE	CONFIG_FPGA_RCR1_VALUE
+#define CONFIG_CS1RCR2_VALUE	CONFIG_FPGA_RCR2_VALUE
+
+#define CONFIG_CS1WCR1_VALUE	CONFIG_FPGA_WCR1_VALUE
+#define CONFIG_CS1WCR2_VALUE	CONFIG_FPGA_WCR2_VALUE
+
+/* CS2 */
+#define CONFIG_CS2GCR1_VALUE	0x00010080
+#define CONFIG_CS2GCR2_VALUE	0x00000000
+
+#define CONFIG_CS2RCR1_VALUE	0x00000000
+#define CONFIG_CS2RCR2_VALUE	0x00000000
+
+#define CONFIG_CS2WCR1_VALUE	0x00000000
+#define CONFIG_CS2WCR2_VALUE	0x00000000
+
+/* CS3 */
+#define CONFIG_CS3GCR1_VALUE	0x00010080
+#define CONFIG_CS3GCR2_VALUE	0x00000000
+
+#define CONFIG_CS3RCR1_VALUE	0x00000000
+#define CONFIG_CS3RCR2_VALUE	0x00000000
+
+#define CONFIG_CS3WCR1_VALUE	0x00000000
+#define CONFIG_CS3WCR2_VALUE	0x00000000
+
+/* CS4 */
+#define CONFIG_CS4GCR1_VALUE	0x00010080
+#define CONFIG_CS4GCR2_VALUE	0x00000000
+
+#define CONFIG_CS4RCR1_VALUE	0x00000000
+#define CONFIG_CS4RCR2_VALUE	0x00000000
+
+#define CONFIG_CS4WCR1_VALUE	0x00000000
+#define CONFIG_CS4WCR2_VALUE	0x00000000
+
+/* CS5 */
+#define CONFIG_CS5GCR1_VALUE	0x00010080
+#define CONFIG_CS5GCR2_VALUE	0x00000000
+
+#define CONFIG_CS5RCR1_VALUE	0x00000000
+#define CONFIG_CS5RCR2_VALUE	0x00000000
+
+#define CONFIG_CS5WCR1_VALUE	0x00000000
+#define CONFIG_CS5WCR2_VALUE	0x00000000
+
+
 /**
  * I2C Configs TODO TODO TODO TODO
  */


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