[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-144-g3438a26
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[Armadeus-commitlog] armadeus branch, master, updated. release-3.3-144-g3438a26
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From: Nicolas <th...@us...> - 2010-11-26 10:29:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 3438a26981680f297da668258c5072441cb2c6b6 (commit)
from a9b0e585dcbf3dc6811b43352d13de9377f7b5d3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 3438a26981680f297da668258c5072441cb2c6b6
Author: nicolas colombain <nic...@ar...>
Date: Fri Nov 26 11:28:12 2010 +0100
[U-BOOT] add fpga support
-----------------------------------------------------------------------
Summary of changes:
.../target/u-boot/u-boot-2010.03-401-apf51.patch | 539 +++++++++++++++++---
1 files changed, 465 insertions(+), 74 deletions(-)
diff --git a/buildroot/target/u-boot/u-boot-2010.03-401-apf51.patch b/buildroot/target/u-boot/u-boot-2010.03-401-apf51.patch
index 376a5b6..623ca70 100644
--- a/buildroot/target/u-boot/u-boot-2010.03-401-apf51.patch
+++ b/buildroot/target/u-boot/u-boot-2010.03-401-apf51.patch
@@ -1,7 +1,7 @@
diff -purN u-boot-2010.03-ref/board/armadeus/apf51/apf51.c u-boot-2010.03/board/armadeus/apf51/apf51.c
--- u-boot-2010.03-ref/board/armadeus/apf51/apf51.c 1970-01-01 01:00:00.000000000 +0100
+++ u-boot-2010.03/board/armadeus/apf51/apf51.c 2010-11-10 00:45:59.000000000 +0100
-@@ -0,0 +1,988 @@
+@@ -0,0 +1,1071 @@
+/*
+ * (C) Copyright 2010 Eric Jarrige, Armadeus Project
+ *
@@ -31,18 +31,45 @@ diff -purN u-boot-2010.03-ref/board/armadeus/apf51/apf51.c u-boot-2010.03/board/
+#include <asm/arch/asm-offsets.h>
+#include <asm/arch/mx51_pins.h>
+#include <asm/arch/iomux.h>
-+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <i2c.h>
+//#include <asm/arch/imx_spi.h>
+//#include <asm/arch/gpio.h>
+#include <asm/arch/mxc_nand.h>
++#include "fpga.h"
++
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+unsigned long boot_verb = 0;
+
++/*
++static int read_firmware (size_t offset, size_t end, u_char * buf)
++{
++ size_t amount_loaded = 0;
++ size_t blocksize;
++
++ u_char *char_ptr;
++
++ blocksize = nand_info[0].erasesize;
++
++ while (offset < end) {
++ if (nand_block_isbad(&nand_info[0], offset)) {
++ offset += blocksize;
++ } else {
++ char_ptr = &buf[amount_loaded];
++ if (nand_read(&nand_info[0], offset, &blocksize, char_ptr))
++ return 1;
++ offset += blocksize;
++ amount_loaded += blocksize;
++ }
++ }
++
++ return amount_loaded;
++}
++*/
++
+u32 get_board_rev(void)
+{
+ return system_rev;
@@ -334,6 +361,89 @@ diff -purN u-boot-2010.03-ref/board/armadeus/apf51/apf51.c u-boot-2010.03/board/
+ mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT0);
+}
+
++void setup_misc(void)
++{
++ /*
++ * Configure iomux for misc interfaces
++ */
++#define GPIO_PAD_CFG (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | \
++ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | \
++ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST)
++
++ /* pwm 1 & 2 */
++ mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
++ mxc_iomux_set_pad(MX51_PIN_GPIO1_2, GPIO_PAD_CFG);
++
++ mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT1);
++ mxc_iomux_set_pad(MX51_PIN_GPIO1_3, GPIO_PAD_CFG);
++
++ /* touch detect# */
++ mxc_request_iomux(MX51_PIN_GPIO1_4, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_GPIO1_4, GPIO_PAD_CFG);
++
++ /* clko */
++ mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT5);
++ mxc_iomux_set_pad(MX51_PIN_GPIO1_5, GPIO_PAD_CFG);
++
++ /* touch eoc# */
++ mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
++ mxc_iomux_set_pad(MX51_PIN_GPIO1_6, GPIO_PAD_CFG);
++
++ /* PMIC IRQ */
++ mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
++
++ /* FEC PHY RST# */
++ mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT4);
++ mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, GPIO_PAD_CFG);
++
++ /* USBHOST RST# */
++ mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
++ mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, GPIO_PAD_CFG);
++
++ /* PMIC SLEEP# */
++ mxc_request_iomux(MX51_PIN_DISPB2_SER_CLK, IOMUX_CONFIG_ALT4);
++ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_CLK, GPIO_PAD_CFG);
++
++ /* PMIC OFF# */
++ mxc_request_iomux(MX51_PIN_DISPB2_SER_RS, IOMUX_CONFIG_ALT4);
++ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_RS, GPIO_PAD_CFG);
++}
++
++void setup_fpga(void)
++{
++ /* FPGA PWR */
++ mxc_request_iomux(CONFIG_SYS_FPGA_PWR, IOMUX_CONFIG_ALT4);
++ mxc_iomux_set_pad(CONFIG_SYS_FPGA_PWR, GPIO_PAD_CFG);
++
++ /* FPGA SUSPEND */
++ mxc_request_iomux(CONFIG_SYS_FPGA_SUSPEND, IOMUX_CONFIG_ALT4);
++ mxc_iomux_set_pad(CONFIG_SYS_FPGA_SUSPEND, GPIO_PAD_CFG);
++
++ /* FPGA PROG */
++ mxc_request_iomux(CONFIG_SYS_FPGA_PRG, IOMUX_CONFIG_ALT3);
++ mxc_iomux_set_pad(CONFIG_SYS_FPGA_PRG, GPIO_PAD_CFG);
++
++ /* FPGA DONE */
++ mxc_request_iomux(CONFIG_SYS_FPGA_DONE, IOMUX_CONFIG_ALT3);
++ mxc_iomux_set_pad(CONFIG_SYS_FPGA_DONE, GPIO_PAD_CFG);
++
++ /* FPGA INIT# */
++ mxc_request_iomux(CONFIG_SYS_FPGA_INIT, IOMUX_CONFIG_ALT3);
++ mxc_iomux_set_pad(CONFIG_SYS_FPGA_INIT, GPIO_PAD_CFG);
++
++ #define CS1GCR1 0x18
++ #define CS1WCR1 0x28
++ #define WCR 0x90
++
++ /* set 16bits bus size, muxed synchronous mode */
++ __REG(WEIM_BASE_ADDR + CS1GCR1) = 0x019100bf;
++ /* adjust CS1 timings */
++ __REG(WEIM_BASE_ADDR + CS1WCR1) = 0x01000008; /* full speed write */
++
++ /* force BCLK free run */
++ __REG(WEIM_BASE_ADDR + WCR) = 0x00000021;
++}
++
+void setup_display(void)
+{
+ /*
@@ -472,79 +582,13 @@ diff -purN u-boot-2010.03-ref/board/armadeus/apf51/apf51.c u-boot-2010.03/board/
+ __REG(baddr + GPIO_DR) &= ~(1 << gpio_off);
+}
+
-+void setup_misc(void)
++int imx_gpio_pin_get(unsigned int pin)
+{
-+ /*
-+ * Configure iomux for misc interfaces
-+ */
-+#define GPIO_PAD_CFG (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | \
-+ PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | \
-+ PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST)
-+
-+ /* pwm 1 & 2 */
-+ mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1);
-+ mxc_iomux_set_pad(MX51_PIN_GPIO1_2, GPIO_PAD_CFG);
-+
-+ mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT1);
-+ mxc_iomux_set_pad(MX51_PIN_GPIO1_3, GPIO_PAD_CFG);
-+
-+ /* touch detect# */
-+ mxc_request_iomux(MX51_PIN_GPIO1_4, IOMUX_CONFIG_ALT0);
-+ mxc_iomux_set_pad(MX51_PIN_GPIO1_4, GPIO_PAD_CFG);
-+
-+ /* clko */
-+ mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT5);
-+ mxc_iomux_set_pad(MX51_PIN_GPIO1_5, GPIO_PAD_CFG);
-+
-+ /* touch eoc# */
-+ mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0);
-+ mxc_iomux_set_pad(MX51_PIN_GPIO1_6, GPIO_PAD_CFG);
-+
-+ /* PMIC IRQ */
-+ mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0);
-+
-+ /* FPGA PWR */
-+ mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4);
-+ mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, GPIO_PAD_CFG);
-+
-+ /* FEC PHY RST# */
-+ mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT4);
-+ mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, GPIO_PAD_CFG);
-+ /* Ethernet PHY Reset in */
-+ imx_gpio_pin_set(CONFIG_SYS_PHY_RESET_GPIO,0); /* MX51_PIN_DI1_PIN11 */
-+ imx_gpio_pin_cfg_dir(CONFIG_SYS_PHY_RESET_GPIO, 1);
-+
-+ /* USBHOST RST# */
-+ mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
-+ mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, GPIO_PAD_CFG);
-+
-+ /* PMIC SLEEP# */
-+ mxc_request_iomux(MX51_PIN_DISPB2_SER_CLK, IOMUX_CONFIG_ALT4);
-+ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_CLK, GPIO_PAD_CFG);
-+
-+ /* FPGA SUSPEND */
-+ mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
-+ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, GPIO_PAD_CFG);
-+
-+ /* PMIC OFF# */
-+ mxc_request_iomux(MX51_PIN_DISPB2_SER_RS, IOMUX_CONFIG_ALT4);
-+ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_RS, GPIO_PAD_CFG);
-+
-+ /* FPGA PROG */
-+ mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
-+ mxc_iomux_set_pad(MX51_PIN_CSI2_D12, GPIO_PAD_CFG);
-+
-+ /* FPGA DONE */
-+ mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
-+ mxc_iomux_set_pad(MX51_PIN_CSI2_D13, GPIO_PAD_CFG);
-+
-+ /* FPGA INIT# */
-+ mxc_request_iomux(MX51_PIN_CSI2_D18, IOMUX_CONFIG_ALT3);
-+ mxc_iomux_set_pad(MX51_PIN_CSI2_D18, GPIO_PAD_CFG);
-+
-+ /* Ethernet PHY Reset out */
-+ imx_gpio_pin_set(CONFIG_SYS_PHY_RESET_GPIO,1);
++ u32 gpio_num = IOMUX_TO_GPIO(pin);
++ u32 gpio_off = GPIO_TO_INDEX(gpio_num);
++ u32 baddr = PORT_BADDR(GPIO_TO_PORT(gpio_num));
+
++ return (__REG(baddr + GPIO_PSR) >> gpio_off) & 1;
+}
+
+
@@ -587,6 +631,11 @@ diff -purN u-boot-2010.03-ref/board/armadeus/apf51/apf51.c u-boot-2010.03/board/
+#define CFG_FEC_PAD (PAD_CTL_DRV_MEDIUM | PAD_CTL_PUE_KEEPER | \
+ PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_VOT_HIGH)
+
++ /* Ethernet PHY Reset */
++ imx_gpio_pin_set(CONFIG_SYS_PHY_RESET_GPIO,0);
++ imx_gpio_pin_cfg_dir(CONFIG_SYS_PHY_RESET_GPIO, 1);
++ imx_gpio_pin_set(CONFIG_SYS_PHY_RESET_GPIO,1);
++
+ /* FEC TX_ER muxed with DI_GP3 */
+ mxc_request_iomux(MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX51_PIN_DI_GP3, CFG_FEC_PAD);
@@ -800,9 +849,43 @@ diff -purN u-boot-2010.03-ref/board/armadeus/apf51/apf51.c u-boot-2010.03/board/
+ setup_eim();
+ setup_csi();
+ setup_keypad();
++#ifdef CONFIG_FPGA
++ setup_fpga();
++#endif
+ return 0;
+}
+
++/*
++ * Miscellaneous intialization
++ */
++int
++misc_init_r (void)
++{
++ char *s;
++ u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
++ size_t end = 0;
++ size_t size = 0;
++ size_t offset = -1;
++ char *autoload = getenv ("firmware_autoload");
++
++#if defined(CONFIG_FPGA)
++ /* init and download fpga */
++/* if (( autoload ) && (0 == strcmp(autoload, "1"))) {
++ if ((s = getenv("firmware_offset")) != NULL) {
++ offset = simple_strtoul(s, NULL, 16);
++ }
++ if ((s = getenv("firmware_len")) != NULL) {
++ end = offset + simple_strtoul(s, NULL, 16);
++ }
++ if ((-1 != offset) && (offset != end)) {
++ size = read_firmware (offset, end, firmware_buffer);
++ }
++ }*/
++ APF51_init_fpga (firmware_buffer, size);
++#endif
++
++ return 0;
++}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
@@ -1026,7 +1109,7 @@ diff -purN u-boot-2010.03-ref/board/armadeus/apf51/Makefile u-boot-2010.03/board
+
+LIB = $(obj)lib$(BOARD).a
+
-+COBJS := apf51.o
++COBJS := apf51.o fpga.o
+SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
@@ -1172,3 +1255,311 @@ diff -purN u-boot-2010.03-ref/Makefile u-boot-2010.03/Makefile
at91cap9adk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91cap9adk atmel at91
+diff -purN u-boot-2010.03-ref/board/armadeus/apf51/fpga.h u-boot-2010.03/board/armadeus/apf51/fpga.h
+--- u-boot-2010.03-ref/board/armadeus/apf51/fpga.h 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2010.03/board/armadeus/apf51/fpga.h 2010-09-16 22:10:12.000000000 +0200
+@@ -0,0 +1,39 @@
++/*
++ * (C) Copyright 2002-2010
++ * Eric Jarrige <eri...@ar...>
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++extern int APF51_init_fpga (u_char * buffer, size_t size);
++
++extern int fpga_pre_fn (int cookie);
++extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
++extern int fpga_cs_fn (int assert_cs, int flush, int cookie);
++extern int fpga_init_fn (int cookie);
++extern int fpga_done_fn (int cookie);
++extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn (int assert_write, int flush, int cookie);
++extern int fpga_rdata_fn ( unsigned char *data, int cookie );
++extern int fpga_wdata_fn ( unsigned char data, int cookie );
++extern int fpga_abort_fn (int cookie);
++extern int fpga_post_fn (int cookie);
++extern int fpga_busy_fn (int cookie);
+diff -purN u-boot-2010.03-ref/board/armadeus/apf51/fpga.c u-boot-2010.03/board/armadeus/apf51/fpga.c
+--- u-boot-2010.03-ref/board/armadeus/apf51/fpga.c 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2010.03/board/armadeus/apf51/fpga.c 2010-09-16 22:10:12.000000000 +0200
+@@ -0,0 +1,261 @@
++ /*
++ * (C) Copyright 2002-2010
++ * Nicolas Colombain <nic...@ar...>
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++ #include <common.h>
++
++ #if defined(CONFIG_FPGA)
++
++ #include <asm/arch/imx-regs.h>
++ #include <asm/arch/asm-offsets.h>
++ #include <asm/io.h>
++ #include <command.h>
++ #include <config.h>
++ #include <asm/arch/iomux.h>
++ #include "fpga.h"
++ #include <spartan3.h>
++
++ #ifdef FPGA_DEBUG
++ #define PRINTF(fmt,args...) printf (fmt ,##args)
++ #else
++ #define PRINTF(fmt,args...)
++ #endif
++
++ extern void imx_gpio_pin_set(unsigned int pin, int value);
++ extern void imx_gpio_pin_cfg_dir(unsigned int pin, int dir);
++ extern int imx_gpio_pin_get(unsigned int pin);
++
++ u32 temp_clk; /* use to restore the emi_clk_sel after donwload */
++
++ /* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 6 :) code is compatible.
++ * Just take care about the file size
++ */
++ Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
++ fpga_pre_fn,
++ fpga_pgm_fn,
++ fpga_init_fn,
++ NULL,
++ fpga_done_fn,
++ fpga_clk_fn,
++ fpga_cs_fn,
++ fpga_wr_fn,
++ fpga_rdata_fn,
++ fpga_wdata_fn,
++ fpga_busy_fn,
++ fpga_abort_fn,
++ fpga_post_fn,
++ };
++
++ Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++ {Xilinx_Spartan3,
++ slave_parallel,
++ 3713568l/8,
++ (void *) &fpga_fns,
++ 0}
++ };
++
++ /*
++ *
++ */
++ int
++ fpga_pre_fn (int cookie)
++ {
++ #define EMI_CLK_SEL 1<<26
++
++ /* change emi_clk_sel to ensure blck smaller than 50MHz */
++ temp_clk = __REG(CCM_BASE_ADDR + CLKCTL_CBCDR);
++ __REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk | EMI_CLK_SEL;
++
++ /* FPGA PROG */
++ imx_gpio_pin_set(CONFIG_SYS_FPGA_PRG, 1);
++ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_PRG, 1);
++
++ /* FPGA PWR */
++ imx_gpio_pin_set(CONFIG_SYS_FPGA_PWR, 1);
++ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_PWR, 1);
++
++ printf("Enable fpga power\n");
++
++ /* FPGA SUSPEND */
++ imx_gpio_pin_set(CONFIG_SYS_FPGA_SUSPEND, 1);
++ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_SUSPEND, 1);
++
++ /* FPGA DONE */
++ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_DONE, 0);
++
++ /* FPGA INIT# */
++ imx_gpio_pin_cfg_dir(CONFIG_SYS_FPGA_INIT, 0);
++
++ return cookie;
++ }
++
++ /*
++ * Set the FPGA's active-low program line to the specified level
++ */
++ int
++ fpga_pgm_fn (int assert, int flush, int cookie)
++ {
++ PRINTF ("%s:%d: FPGA PROGRAM %s\n", __FUNCTION__, __LINE__,
++ assert?"high":"low");
++ imx_gpio_pin_set( CONFIG_SYS_FPGA_PRG, !assert);
++ return assert;
++ }
++
++ /*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++ int
++ fpga_clk_fn (int assert_clk, int flush, int cookie)
++ {
++ return assert_clk;
++ }
++
++ /*
++ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
++ * asserted (low).
++ */
++ int
++ fpga_init_fn (int cookie)
++ {
++ int value;
++ PRINTF ("%s:%d: INIT check... \n", __FUNCTION__, __LINE__);
++ value = imx_gpio_pin_get(CONFIG_SYS_FPGA_INIT);
++ PRINTF ("init value read %x\n",value);
++ if (value)
++ return 0;
++ return 1;
++ }
++
++ /*
++ * Test the state of the active-high FPGA DONE pin
++ */
++ int
++ fpga_done_fn (int cookie)
++ {
++ int value;
++ value = imx_gpio_pin_get(CONFIG_SYS_FPGA_DONE);
++ PRINTF ("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
++ value?"high":"low");
++ return(value?FPGA_SUCCESS:FPGA_FAIL);
++ }
++
++ /*
++ * Set the FPGA's wr line to the specified level
++ */
++ int
++ fpga_wr_fn (int assert_write, int flush, int cookie)
++ {
++ return assert_write;
++ }
++
++ int
++ fpga_cs_fn (int assert_cs, int flush, int cookie)
++ {
++ return assert_cs;
++ }
++
++ int
++ fpga_rdata_fn ( unsigned char *data, int cookie )
++ {
++ PRINTF ("%s:%d: FPGA READ DATA %02X \n", __FUNCTION__, __LINE__,
++ *((char*)CONFIG_SYS_FPGA_RDATA));
++ *data = (unsigned char)((*((unsigned short*)CONFIG_SYS_FPGA_RDATA))&0x00FF);
++ return *data;
++ }
++
++ int
++ fpga_wdata_fn ( unsigned char data, int cookie )
++ {
++ PRINTF ("%s:%d: FPGA WRITE DATA %02X \n", __FUNCTION__, __LINE__,
++ data);
++ static u32 temp;
++ static u32 index = 0;
++
++ switch( index++ ){
++ case 0: temp = data << 8; break;
++ case 1: temp = temp + data; break;
++ case 2: temp = temp + (data << 24); break;
++ default:
++ *((volatile unsigned long*)CONFIG_SYS_FPGA_WDATA) = temp + (data << 16);
++ index = 0;
++ break;
++ }
++
++ return data;
++ }
++
++ int
++ fpga_abort_fn ( int cookie )
++ {
++ return cookie;
++ }
++
++
++ int
++ fpga_busy_fn ( int cookie )
++ {
++ return 1;
++ }
++
++ int
++ fpga_post_fn (int cookie)
++ {
++ PRINTF ("%s:%d: FPGA POST \n", __FUNCTION__, __LINE__);
++ /* restore emi_clk_sel */
++ __REG(CCM_BASE_ADDR + CLKCTL_CBCDR) = temp_clk;
++
++ return cookie;
++ }
++
++ /*
++ * Initialize the fpga. Return 1 on success, 0 on failure.
++ */
++ int
++ APF51_init_fpga (u_char * buffer, size_t size)
++ {
++ char *autoload = getenv ("firmware_autoload");
++
++ int i,lout=0;
++
++ fpga_init();
++
++ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++ PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
++ fpga_add (fpga_xilinx, &fpga[i]);
++ }
++
++ if ((size >= fpga[0].size) && ( autoload ) && (0 == strcmp(autoload, "1"))) {
++ if (FPGA_SUCCESS != fpga_load( 0, (void *)buffer, size )) {
++ lout = 1;
++ printf("Firmware download failed!\n");
++ }
++ else
++ printf("Firmware successfully programmed\n");
++ }
++ return lout;
++ }
++
++ #endif /* CONFIG_FPGA */
hooks/post-receive
--
armadeus
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