[Armadeus-commitlog] SF.net SVN: armadeus:[1236] trunk/firmware/BRAMTest
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[Armadeus-commitlog] SF.net SVN: armadeus:[1236] trunk/firmware/BRAMTest
|
From: <Fa...@us...> - 2009-04-22 11:49:20
|
Revision: 1236
http://armadeus.svn.sourceforge.net/armadeus/?rev=1236&view=rev
Author: FabM
Date: 2009-04-22 11:49:17 +0000 (Wed, 22 Apr 2009)
Log Message:
-----------
[FIRMWARE] cleaning BRAMTest
Added Paths:
-----------
trunk/firmware/BRAMTest/bin/
trunk/firmware/BRAMTest/bin/BRAMTEST_APF27_200k.bit
trunk/firmware/BRAMTest/bin/BRAMTEST_APF9328_200k.bit
trunk/firmware/BRAMTest/src/
trunk/firmware/BRAMTest/src/BRAMTest.vhdl
trunk/firmware/BRAMTest/src/BRAMTest_APF27.ucf
trunk/firmware/BRAMTest/src/BRAMTest_APF9328.ucf
Removed Paths:
-------------
trunk/firmware/BRAMTest/BRAMTest.ucf
trunk/firmware/BRAMTest/BRAMTest.vhdl
trunk/firmware/BRAMTest/BRAMTest_APF.ucf
trunk/firmware/BRAMTest/BRAMtest.ise
trunk/firmware/BRAMTest/bramtest_top.bin
trunk/firmware/BRAMTest/bramtest_top_APF.bin
Deleted: trunk/firmware/BRAMTest/BRAMTest.ucf
===================================================================
--- trunk/firmware/BRAMTest/BRAMTest.ucf 2009-04-22 09:09:35 UTC (rev 1235)
+++ trunk/firmware/BRAMTest/BRAMTest.ucf 2009-04-22 11:49:17 UTC (rev 1236)
@@ -1,72 +0,0 @@
-NET "AddrxDI<10>" LOC = "P33";
-NET "AddrxDI<11>" LOC = "P35";
-NET "AddrxDI<12>" LOC = "P36";
-NET "User<0>" LOC = "P92" ;
-NET "User<1>" LOC = "P93" ;
-NET "User<2>" LOC = "P95" ;
-NET "User<3>" LOC = "P96" ;
-NET "User<4>" LOC = "P97" ;
-NET "User<5>" LOC = "P98" ;
-NET "User<6>" LOC = "P99" ;
-NET "User<7>" LOC = "P100" ;
-NET "User<8>" LOC = "P102" ;
-NET "User<9>" LOC = "P103" ;
-NET "User<10>" LOC = "P104" ;
-NET "User<11>" LOC = "P105" ;
-NET "User<12>" LOC = "P107" ;
-NET "User<13>" LOC = "P108" ;
-NET "User<14>" LOC = "P112" ;
-NET "User<15>" LOC = "P113" ;
-NET "User<16>" LOC = "P116" ;
-NET "User<17>" LOC = "P118" ;
-NET "User<18>" LOC = "P119" ;
-NET "User<19>" LOC = "P122" ;
-#NET "ResetxRB" LOC = "P123" ;
-NET "ClkxCI" TNM_NET = "ClkxCI";
-TIMESPEC "TS_ClkxCI" = PERIOD "ClkxCI" 10 ns HIGH 50 %;
-
-#PACE: Start of Constraints generated by PACE
-
-#PACE: Start of PACE I/O Pin Assignments
-NET "AddrxDI<0>" LOC = "P21" ;
-NET "AddrxDI<1>" LOC = "P23" ;
-NET "AddrxDI<2>" LOC = "P24" ;
-NET "AddrxDI<3>" LOC = "P25" ;
-NET "AddrxDI<4>" LOC = "P26" ;
-NET "AddrxDI<5>" LOC = "P27" ;
-NET "AddrxDI<6>" LOC = "P28" ;
-NET "AddrxDI<7>" LOC = "P30" ;
-NET "AddrxDI<8>" LOC = "P31" ;
-NET "AddrxDI<9>" LOC = "P32" ;
-NET "ClkxCI" LOC = "P55" ;
-NET "CSxBI" LOC = "P44" ;
-NET "DataxD<0>" LOC = "P1" ;
-NET "DataxD<10>" LOC = "P13" ;
-NET "DataxD<11>" LOC = "P14" ;
-NET "DataxD<12>" LOC = "P15" ;
-NET "DataxD<13>" LOC = "P17" ;
-NET "DataxD<14>" LOC = "P18" ;
-NET "DataxD<15>" LOC = "P20" ;
-NET "DataxD<1>" LOC = "P2" ;
-NET "DataxD<2>" LOC = "P4" ;
-NET "DataxD<3>" LOC = "P5" ;
-NET "DataxD<4>" LOC = "P6" ;
-NET "DataxD<5>" LOC = "P7" ;
-NET "DataxD<6>" LOC = "P8" ;
-NET "DataxD<7>" LOC = "P10" ;
-NET "DataxD<8>" LOC = "P11" ;
-NET "DataxD<9>" LOC = "P12" ;
-NET "WRxBI" LOC = "P46" ;
-NET "RDxBI" LOC = "P47" ;
-NET "IOL30P4" LOC = "P59" ;
-NET "IOL30N4" LOC = "P60" ;
-NET "IOL27P4" LOC = "P63" ;
-NET "IOL01P4_VRN4" LOC = "P68" ;
-NET "IOL01N4_VRN4" LOC = "P69" ;
-NET "IO_VREF4" LOC = "P70" ;
-
-#PACE: Start of PACE Area Constraints
-
-#PACE: Start of PACE Prohibit Constraints
-
-#PACE: End of Constraints generated by PACE
Deleted: trunk/firmware/BRAMTest/BRAMTest.vhdl
===================================================================
--- trunk/firmware/BRAMTest/BRAMTest.vhdl 2009-04-22 09:09:35 UTC (rev 1235)
+++ trunk/firmware/BRAMTest/BRAMTest.vhdl 2009-04-22 11:49:17 UTC (rev 1236)
@@ -1,156 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: Armadeus Project
--- Engineer: michael lerjen
---
--- Create Date: 22:04:02 04/12/2006
--- Design Name:
--- Module Name:
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library UNISIM;
-use UNISIM.VComponents.all;
-
-entity BRAMTest_Top is -- this is the top
- Port (
- DataxD : inout std_logic_vector(15 downto 0);
- AddrxDI : in std_logic_vector(12 downto 0);
- CSxBI : in std_logic;
- WRxBI : in std_logic;
- RDxBI : in std_logic;
- ClkxCI : in std_logic
- --ResetxRB : in std_logic
- );
-end BRAMTest_Top;
-
-
-
-architecture hierarchical of BRAMTest_Top is
- signal DataOutRAMxD : std_logic_vector(15 downto 0);
- signal CSBRAM : std_logic := '0';
- signal WRBRAM : std_logic := '0';
- signal CLKBRAM : std_logic := '0';
-
-begin
-
-
- -- RAMB16_S18: Virtex-II/II-Pro, Spartan-3 1k x 16 + 2 Parity bits Single-Port RAM
- -- Xilinx HDL Language Template version 6.3.1i
-
- RAMB16_S18_inst : RAMB16_S18
- generic map (
- INIT => X"00000", -- Value of output RAM registers at startup
- SRVAL => X"00000", -- Ouput value upon SSR assertion
- WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- INIT_00 => X"cacaacac000000000000000000000000000000000000000000000000acaccaca",
- INIT_01 => X"cccc00000000000000000000000000000000000000000000000000000000aaaa",
- INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DO => DataOutRAMxD, -- 16-bit Data Output
- DOP => open, -- 2-bit parity Output
- ADDR => AddrxDI(10 downto 1), -- 10-bit Address Input
- CLK => CLKBRAM, -- Clock
- DI => DataxD, -- 16-bit Data Input
- DIP => "00", -- 2-bit parity Input
- EN => CSBRAM , -- RAM Enable Input
- SSR => '0', -- Synchronous Set/Reset Input
- WE => WRBRAM -- Write Enable Input
- );
-
- OutputEnable: process (DataOutRAMxD, CSxBI, RDxBI)
- begin
- if (CSxBI = '0' and RDxBI = '0') then -- fix me
- DataxD <= DataOutRAMxD;
- else
- DataxD <= (others => 'Z'); --
- end if;
- end process OutputEnable;
-
- CSBRAM <= not CSxBI;
- WRBRAM <= not WRxBI;
- CLKBRAM <= ClkxCI;
--- End of RAMB16_S18_inst instantiation
-end hierarchical;
Deleted: trunk/firmware/BRAMTest/BRAMTest_APF.ucf
===================================================================
--- trunk/firmware/BRAMTest/BRAMTest_APF.ucf 2009-04-22 09:09:35 UTC (rev 1235)
+++ trunk/firmware/BRAMTest/BRAMTest_APF.ucf 2009-04-22 11:49:17 UTC (rev 1236)
@@ -1,40 +0,0 @@
-# Constraint file for BRAMTest
-NET "ClkxCI" TNM_NET = "ClkxCI";
-TIMESPEC "TS_ClkxCI" = PERIOD "ClkxCI" 10 ns HIGH 50 %;
-
-NET "DataxD<0>" LOC = "P1" ;
-NET "DataxD<1>" LOC = "P2" ;
-NET "DataxD<2>" LOC = "P4" ;
-NET "DataxD<3>" LOC = "P5" ;
-NET "DataxD<4>" LOC = "P6" ;
-NET "DataxD<5>" LOC = "P7" ;
-NET "DataxD<6>" LOC = "P8" ;
-NET "DataxD<7>" LOC = "P10" ;
-NET "DataxD<8>" LOC = "P11" ;
-NET "DataxD<9>" LOC = "P12" ;
-NET "DataxD<10>" LOC = "P13" ;
-NET "DataxD<11>" LOC = "P14" ;
-NET "DataxD<12>" LOC = "P15" ;
-NET "DataxD<13>" LOC = "P17" ;
-NET "DataxD<14>" LOC = "P18" ;
-NET "DataxD<15>" LOC = "P20" ;
-
-NET "AddrxDI<0>" LOC = "P21" ;
-NET "AddrxDI<1>" LOC = "P23" ;
-NET "AddrxDI<2>" LOC = "P24" ;
-NET "AddrxDI<3>" LOC = "P25" ;
-NET "AddrxDI<4>" LOC = "P26" ;
-NET "AddrxDI<5>" LOC = "P27" ;
-NET "AddrxDI<6>" LOC = "P28" ;
-NET "AddrxDI<7>" LOC = "P30" ;
-NET "AddrxDI<8>" LOC = "P31" ;
-NET "AddrxDI<9>" LOC = "P32" ;
-NET "AddrxDI<10>" LOC = "P33" ;
-NET "AddrxDI<11>" LOC = "P35" ;
-NET "AddrxDI<12>" LOC = "P36" ;
-
-NET "ClkxCI" LOC = "P55" ;
-NET "CSxBI" LOC = "P59" ;
-NET "WRxBI" LOC = "P60" ;
-NET "RDxBI" LOC = "P63" ;
-#end
Deleted: trunk/firmware/BRAMTest/BRAMtest.ise
===================================================================
(Binary files differ)
Added: trunk/firmware/BRAMTest/bin/BRAMTEST_APF27_200k.bit
===================================================================
(Binary files differ)
Property changes on: trunk/firmware/BRAMTest/bin/BRAMTEST_APF27_200k.bit
___________________________________________________________________
Added: svn:mime-type
+ application/octet-stream
Added: trunk/firmware/BRAMTest/bin/BRAMTEST_APF9328_200k.bit
===================================================================
(Binary files differ)
Property changes on: trunk/firmware/BRAMTest/bin/BRAMTEST_APF9328_200k.bit
___________________________________________________________________
Added: svn:mime-type
+ application/octet-stream
Deleted: trunk/firmware/BRAMTest/bramtest_top.bin
===================================================================
(Binary files differ)
Deleted: trunk/firmware/BRAMTest/bramtest_top_APF.bin
===================================================================
(Binary files differ)
Copied: trunk/firmware/BRAMTest/src/BRAMTest.vhdl (from rev 1233, trunk/firmware/BRAMTest/BRAMTest.vhdl)
===================================================================
--- trunk/firmware/BRAMTest/src/BRAMTest.vhdl (rev 0)
+++ trunk/firmware/BRAMTest/src/BRAMTest.vhdl 2009-04-22 11:49:17 UTC (rev 1236)
@@ -0,0 +1,156 @@
+----------------------------------------------------------------------------------
+-- Company: Armadeus Project
+-- Engineer: michael lerjen
+--
+-- Create Date: 22:04:02 04/12/2006
+-- Design Name:
+-- Module Name:
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.02 - suppressing warning
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity BRAMTest_Top is -- this is the top
+ Port (
+ DataxD : inout std_logic_vector(15 downto 0);
+ AddrxDI : in std_logic_vector(10 downto 1);
+ CSxBI : in std_logic;
+ WRxBI : in std_logic;
+ RDxBI : in std_logic;
+ ClkxCI : in std_logic
+ );
+end BRAMTest_Top;
+
+
+
+architecture hierarchical of BRAMTest_Top is
+ signal DataOutRAMxD : std_logic_vector(15 downto 0);
+ signal CSBRAM : std_logic := '0';
+ signal WRBRAM : std_logic := '0';
+ signal CLKBRAM : std_logic := '0';
+
+begin
+
+
+ -- RAMB16_S18: Virtex-II/II-Pro, Spartan-3 1k x 16 + 2 Parity bits Single-Port RAM
+ -- Xilinx HDL Language Template version 6.3.1i
+
+ RAMB16_S18_inst : RAMB16_S18
+ generic map (
+ INIT => X"00000", -- Value of output RAM registers at startup
+ SRVAL => X"00000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ INIT_00 => X"cacaacac000000000000000000000000000000000000000000000000acaccaca",
+ INIT_01 => X"cccc00000000000000000000000000000000000000000000000000000000aaaa",
+ INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => DataOutRAMxD, -- 16-bit Data Output
+ DOP => open, -- 2-bit parity Output
+ ADDR => AddrxDI(10 downto 1), -- 10-bit Address Input
+ CLK => CLKBRAM, -- Clock
+ DI => DataxD, -- 16-bit Data Input
+ DIP => "00", -- 2-bit parity Input
+ EN => CSBRAM , -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => WRBRAM -- Write Enable Input
+ );
+
+ OutputEnable: process (DataOutRAMxD, CSxBI, RDxBI)
+ begin
+ if (CSxBI = '0' and RDxBI = '0') then -- fix me
+ DataxD <= DataOutRAMxD;
+ else
+ DataxD <= (others => 'Z'); --
+ end if;
+ end process OutputEnable;
+
+ CSBRAM <= not CSxBI;
+ WRBRAM <= not WRxBI;
+ CLKBRAM <= ClkxCI;
+-- End of RAMB16_S18_inst instantiation
+end hierarchical;
Added: trunk/firmware/BRAMTest/src/BRAMTest_APF27.ucf
===================================================================
--- trunk/firmware/BRAMTest/src/BRAMTest_APF27.ucf (rev 0)
+++ trunk/firmware/BRAMTest/src/BRAMTest_APF27.ucf 2009-04-22 11:49:17 UTC (rev 1236)
@@ -0,0 +1,43 @@
+# Constraint file for BRAMTest
+NET "ClkxCI" TNM_NET = "ClkxCI";
+TIMESPEC "TS_ClkxCI" = PERIOD "ClkxCI" 10 ns HIGH 50 %;
+NET "ClkxCI" LOC="N9" | IOSTANDARD=LVCMOS18;# CLK0
+
+# data bus
+NET "DataxD<0>" LOC="T5" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA0
+NET "DataxD<1>" LOC="T6" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA1
+NET "DataxD<2>" LOC="P7" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA2
+NET "DataxD<3>" LOC="N8" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA3
+NET "DataxD<4>" LOC="P12"| DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA4
+NET "DataxD<5>" LOC="T13"| DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA5
+NET "DataxD<6>" LOC="R13"| DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA6
+NET "DataxD<7>" LOC="T14"| DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA7
+NET "DataxD<8>" LOC="P5" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA8
+NET "DataxD<9>" LOC="N6" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA9
+NET "DataxD<10>" LOC="T3" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA10
+NET "DataxD<11>" LOC="T11"| DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA11
+NET "DataxD<12>" LOC="T4" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA12
+NET "DataxD<13>" LOC="R5" | DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA13
+NET "DataxD<14>" LOC="M10"| DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA14
+NET "DataxD<15>" LOC="T10"| DRIVE=8 | IOSTANDARD=LVCMOS18; # DATA15
+
+# address bus
+NET "AddrxDI<1>" LOC="N5" | IOSTANDARD=LVCMOS18; # ADDR1
+NET "AddrxDI<2>" LOC="L7" | IOSTANDARD=LVCMOS18; # ADDR2
+NET "AddrxDI<3>" LOC="M7" | IOSTANDARD=LVCMOS18; # ADDR3
+NET "AddrxDI<4>" LOC="M8" | IOSTANDARD=LVCMOS18; # ADDR4
+NET "AddrxDI<5>" LOC="L8" | IOSTANDARD=LVCMOS18; # ADDR5
+NET "AddrxDI<6>" LOC="L9" | IOSTANDARD=LVCMOS18; # ADDR6
+NET "AddrxDI<7>" LOC="L10"| IOSTANDARD=LVCMOS18; # ADDR7
+NET "AddrxDI<8>" LOC="M11"| IOSTANDARD=LVCMOS18; # ADDR8
+NET "AddrxDI<9>" LOC="P11"| IOSTANDARD=LVCMOS18; # ADDR9
+NET "AddrxDI<10>" LOC="N11"| IOSTANDARD=LVCMOS18; # ADDR10
+# not used for BRAMTest
+#NET "AddrxDI<11>" LOC="N12"| IOSTANDARD=LVCMOS18; # ADDR11
+#NET "AddrxDI<12>" LOC="P13"| IOSTANDARD=LVCMOS18; # ADDR12
+
+# controls signals
+NET "CSxBI" LOC="P10"| IOSTANDARD=LVCMOS18; # CS5N
+NET "WRxBI" LOC="P9" | IOSTANDARD=LVCMOS18; # EB0N
+NET "RDxBI" LOC="R9" | IOSTANDARD=LVCMOS18; # OEN
+#end
Added: trunk/firmware/BRAMTest/src/BRAMTest_APF9328.ucf
===================================================================
--- trunk/firmware/BRAMTest/src/BRAMTest_APF9328.ucf (rev 0)
+++ trunk/firmware/BRAMTest/src/BRAMTest_APF9328.ucf 2009-04-22 11:49:17 UTC (rev 1236)
@@ -0,0 +1,44 @@
+# Clock
+NET "ClkxCI" TNM_NET = "ClkxCI";
+TIMESPEC "TS_ClkxCI" = PERIOD "ClkxCI" 10 ns HIGH 50 %;
+NET "ClkxCI" LOC = "P55" ;
+
+#address bus
+NET "AddrxDI<1>" LOC = "P23" ;
+NET "AddrxDI<2>" LOC = "P24" ;
+NET "AddrxDI<3>" LOC = "P25" ;
+NET "AddrxDI<4>" LOC = "P26" ;
+NET "AddrxDI<5>" LOC = "P27" ;
+NET "AddrxDI<6>" LOC = "P28" ;
+NET "AddrxDI<7>" LOC = "P30" ;
+NET "AddrxDI<8>" LOC = "P31" ;
+NET "AddrxDI<9>" LOC = "P32" ;
+NET "AddrxDI<10>" LOC = "P33";
+# not used for BRAMTest
+#NET "AddrxDI<0>" LOC = "P21";
+#NET "AddrxDI<11>" LOC = "P35";
+#NET "AddrxDI<12>" LOC = "P36";
+
+# data bus
+NET "DataxD<0>" LOC = "P1" ;
+NET "DataxD<1>" LOC = "P2" ;
+NET "DataxD<2>" LOC = "P4" ;
+NET "DataxD<3>" LOC = "P5" ;
+NET "DataxD<4>" LOC = "P6" ;
+NET "DataxD<5>" LOC = "P7" ;
+NET "DataxD<6>" LOC = "P8" ;
+NET "DataxD<7>" LOC = "P10" ;
+NET "DataxD<8>" LOC = "P11" ;
+NET "DataxD<9>" LOC = "P12" ;
+NET "DataxD<10>" LOC = "P13" ;
+NET "DataxD<11>" LOC = "P14" ;
+NET "DataxD<12>" LOC = "P15" ;
+NET "DataxD<13>" LOC = "P17" ;
+NET "DataxD<14>" LOC = "P18" ;
+NET "DataxD<15>" LOC = "P20" ;
+
+# controls signals
+NET "CSxBI" LOC = "P59" ;
+NET "WRxBI" LOC = "P60" ;
+NET "RDxBI" LOC = "P63" ;
+
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