[Armadeus-commitlog] SF.net SVN: armadeus:[1235] trunk/firmware/wishbone_example/src

[<Fa...@us...>]

Revision: 1235
          http://armadeus.svn.sourceforge.net/armadeus/?rev=1235&view=rev
Author:   FabM
Date:     2009-04-22 09:09:35 +0000 (Wed, 22 Apr 2009)

Log Message:
-----------
[FIRMWARE] beautify wisbone_example VHDL code

Modified Paths:
--------------
    trunk/firmware/wishbone_example/src/button.vhd
    trunk/firmware/wishbone_example/src/intercon.vhd
    trunk/firmware/wishbone_example/src/led.vhd

Modified: trunk/firmware/wishbone_example/src/button.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/button.vhd	2009-04-21 08:27:09 UTC (rev 1234)
+++ trunk/firmware/wishbone_example/src/button.vhd	2009-04-22 09:09:35 UTC (rev 1235)
@@ -41,7 +41,11 @@
 
 ---------------------------------------------------------------------------
 Architecture button_1 of button is
-	---------------------------------------------------------------------------
+---------------------------------------------------------------------------
+    -- registers mapping
+    constant REG_ID     : std_logic := '0';
+    constant REG_BUTTON : std_logic := '1';
+
 	signal button_r : std_logic ;
 	signal reg : std_logic_vector( 15 downto 0);
 begin
@@ -56,7 +60,6 @@
 		end if;
 	end process cbutton;
 
-
 	-- rise interruption
 	pbutton : process(gls_clk,gls_reset)
 	begin
@@ -80,16 +83,16 @@
 			wbs_ack <= '0';
 			wbs_readdata <= (others => '0');
 		elsif(rising_edge(gls_clk)) then
-            wbs_ack <= '0';
 			if(wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1')then
     			wbs_ack <= '1';
-                if wbs_add = '0' then
+                if wbs_add = REG_ID then
 	    			wbs_readdata <= std_logic_vector(to_unsigned(id,16));
                 else
                     wbs_readdata <= reg;
                 end if;
             else
                 wbs_readdata <= (others => '0');
+                wbs_ack <= '0';
             end if;
 		end if;
 	end process pread;

Modified: trunk/firmware/wishbone_example/src/intercon.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/intercon.vhd	2009-04-21 08:27:09 UTC (rev 1234)
+++ trunk/firmware/wishbone_example/src/intercon.vhd	2009-04-22 09:09:35 UTC (rev 1235)
@@ -101,7 +101,7 @@
     led0_wbs_add <= wrapper_wbm_address(1);
     button0_wbs_add <= wrapper_wbm_address(1);
 
-    decodeproc : process(rstgen_syscon00_gls_clk,rstgen_syscon00_gls_reset,wrapper_wbm_address)
+    decodeproc : process(rstgen_syscon00_gls_clk,rstgen_syscon00_gls_reset)
     begin
         if rstgen_syscon00_gls_reset='1' then
             irq_mngr00_swb16_cs <= '0';

Modified: trunk/firmware/wishbone_example/src/led.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/led.vhd	2009-04-21 08:27:09 UTC (rev 1234)
+++ trunk/firmware/wishbone_example/src/led.vhd	2009-04-22 09:09:35 UTC (rev 1235)
@@ -42,24 +42,32 @@
 -----------------------------------------------------------------------
 Architecture led_1 of led is
 -----------------------------------------------------------------------
+    -- registers mapping
+    constant REG_LED : std_logic := '0';
+    constant REG_ID  : std_logic := '1';
+
     signal reg : std_logic_vector( wb_size-1 downto 0);
+    signal read_ack : std_logic ;
+    signal write_ack : std_logic ;
 begin
 
 -- connect led_o
 led_o <= reg(0);
 
-wbs_ack <= wbs_strobe;
+wbs_ack <= read_ack or write_ack;
 
 -- manage register
 write_bloc : process(gls_clk,gls_reset)
 begin
     if gls_reset = '1' then 
         reg <= (others => '0');
+        write_ack <= '0';
     elsif rising_edge(gls_clk) then
         if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
             reg <= wbs_writedata;
+            write_ack <= '1';
         else
-            reg <= reg;
+            write_ack <= '0';
         end if;
     end if;
 
@@ -71,13 +79,15 @@
         wbs_readdata <= (others => '0');
     elsif rising_edge(gls_clk) then
         if (wbs_strobe = '1' and wbs_write = '0'  and wbs_cycle = '1' ) then
-            if wbs_add = '0' then
+            read_ack <= '1';
+            if wbs_add = REG_LED then
                 wbs_readdata <= reg;
             else
                 wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
             end if;
         else
             wbs_readdata <= (others => '0');
+            read_ack <= '0';
         end if;
     end if;
 end process read_bloc;


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