[Armadeus-commitlog] SF.net SVN: armadeus:[1184] trunk/target/linux/debug/imxregs/imx27regs.h

[<ar...@us...>]

Revision: 1184
          http://armadeus.svn.sourceforge.net/armadeus/?rev=1184&view=rev
Author:   artemys
Date:     2009-03-22 18:00:25 +0000 (Sun, 22 Mar 2009)

Log Message:
-----------
[DEBUG] Makes eMMA PreProcessor registers accessible from imxregs

Modified Paths:
--------------
    trunk/target/linux/debug/imxregs/imx27regs.h

Modified: trunk/target/linux/debug/imxregs/imx27regs.h
===================================================================
--- trunk/target/linux/debug/imxregs/imx27regs.h	2009-03-22 17:58:48 UTC (rev 1183)
+++ trunk/target/linux/debug/imxregs/imx27regs.h	2009-03-22 18:00:25 UTC (rev 1184)
@@ -905,39 +905,39 @@
 { "PP_CSC_COEFF_012",          0x10026038, 0, 0xffffffff, 'x', "PP CSC Coefficient 0, 1, and" },
 { "PP_CSC_COEFF_34",           0x1002603C, 0, 0xffffffff, 'x', "PP CSC Coefficient 3 and 4" },
 // { "PP_RESIZE_COEF_TBL",        0x10026100 - 0x1002617C, 0, 0xffffffff, 'x', "PP Resize Coefficient Table Register" },
-{ "PrP_CNTL",                  0x10026400, 0, 0xffffffff, 'x', "PrP Control Register" },
-{ "PrP_INTRCNTL",              0x10026404, 0, 0xffffffff, 'x', "PrP Interrupt Control Register" },
-{ "PrP_INTRSTATUS",            0x10026408, 0, 0xffffffff, 'x', "PrP interrupt Status Register" },
-{ "PrP_SOURCE_Y_PTR",          0x1002640C, 0, 0xffffffff, 'x', "PrP Source Y Frame Start Address" },
-{ "PrP_SOURCE_CB_PTR",         0x10026410, 0, 0xffffffff, 'x', "PrP Source CB Frame Start Address" },
-{ "PrP_SOURCE_CR_PTR",         0x10026414, 0, 0xffffffff, 'x', "PrP Source CR Frame Start Address" },
-{ "PrP_DEST_RGB1_PTR",         0x10026418, 0, 0xffffffff, 'x', "PrP Destination RGB Frame-1 Start Address" },
-{ "PrP_DEST_RGB2_PTR",         0x1002641C, 0, 0xffffffff, 'x', "PrP Destination RGB Frame-2 Start Address" },
-{ "PrP_DEST_Y_PTR",            0x10026420, 0, 0xffffffff, 'x', "PrP Destination Y Frame Start Address" },
-{ "PrP_DEST_CB_PTR",           0x10026424, 0, 0xffffffff, 'x', "PrP Destination CB Frame Start Address" },
-{ "PrP_DEST_CR_PTR",           0x10026428, 0, 0xffffffff, 'x', "PrP Destination CR Frame Start Address" },
-{ "PrP_SOURCE_FRAME_SIZE",     0x1002642C, 0, 0xffffffff, 'x', "PrP Source Frame Size Register" },
-{ "PrP_CH1_LINE_STRIDE",       0x10026430, 0, 0xffffffff, 'x', "PrP Channel-1 Line stride Register" },
-{ "PrP_SRC_PIXEL_FORMAT_CNTL", 0x10026434, 0, 0xffffffff, 'x', "PrP Source Pixel Format Control Register" },
-{ "PrP_CH1_PIXEL_FORMAT_CNTL", 0x10026438, 0, 0xffffffff, 'x', "PrP CH1 Pixel Format Control Register" },
-{ "PrP_CH1_OUT_IMAGE_SIZE",    0x1002643C, 0, 0xffffffff, 'x', "PrP CH1 Output Image Size Register" },
-{ "PrP_CH2_OUT_IMAGE_SIZE",    0x10026440, 0, 0xffffffff, 'x', "PrP CH2 Output Image Size Register" },
-{ "PrP_SOURCE_LINE_STRIDE",    0x10026444, 0, 0xffffffff, 'x', "PrP Source Line Stride Register" },
-{ "PrP_CSC_COEFF_012",         0x10026448, 0, 0xffffffff, 'x', "PrP CSC Coefficients 0, 1, and" },
-{ "PrP_CSC_COEFF_345",         0x1002644C, 0, 0xffffffff, 'x', "PrP CSC Coefficients 3, 4, and" },
-{ "PrP_CSC_COEFF_678",         0x10026450, 0, 0xffffffff, 'x', "PrP CSC Coefficients 6, 7, and" },
-{ "PrP_CH1_HRESIZE_COEFF1",    0x10026454, 0, 0xffffffff, 'x', "PrP CH1 Horizontal Resize Coefficients Register" },
-{ "PrP_CH1_HRESIZE_COEFF2",    0x10026458, 0, 0xffffffff, 'x', "PrP CH1 Horizontal Resize Coefficients Register" },
-{ "PrP_CH1_HRESIZE_VALID",     0x1002645C, 0, 0xffffffff, 'x', "PrP CH1 Horizontal Resize Valid Register" },
-{ "PrP_CH1_VRESIZE_COEFF1",    0x10026460, 0, 0xffffffff, 'x', "PrP CH1 Vertical Resize Coefficients Register" },
-{ "PrP_CH1_VRESIZE_COEFF2",    0x10026464, 0, 0xffffffff, 'x', "PrP CH1 Vertical Resize Coefficients Register" },
-{ "PrP_CH1_VRESIZE_VALID",     0x10026468, 0, 0xffffffff, 'x', "PrP CH1 Vertical Resize Valid Register" },
-{ "PrP_CH2_HRESIZE_COEFF1",    0x1002646C, 0, 0xffffffff, 'x', "PrP CH2 Horizontal Resize Coefficients Register" },
-{ "PrP_CH2_HRESIZE_COEFF2",    0x10026470, 0, 0xffffffff, 'x', "PrP CH2 Horizontal Resize Coefficients Register" },
-{ "PrP_CH2_HRESIZE_VALID",     0x10026474, 0, 0xffffffff, 'x', "PrP CH2 Horizontal Resize Valid Register" },
-{ "PrP_CH2_VRESIZE_COEFF1",    0x10026478, 0, 0xffffffff, 'x', "PrP CH2 Vertical Resize Coefficients Register" },
-{ "PrP_CH2_VRESIZE_COEFF2",    0x1002647C, 0, 0xffffffff, 'x', "PrP CH2 Vertical Resize Coefficients Register" },
-{ "PrP_CH2_VRESIZE_VALID",     0x10026480, 0, 0xffffffff, 'x', "PrP CH2 Vertical Resize Valid Register" },
+{ "PRP_CNTL",                  0x10026400, 0, 0xffffffff, 'x', "PrP Control Register" },
+{ "PRP_INTRCNTL",              0x10026404, 0, 0xffffffff, 'x', "PrP Interrupt Control Register" },
+{ "PRP_INTRSTATUS",            0x10026408, 0, 0xffffffff, 'x', "PrP interrupt Status Register" },
+{ "PRP_SOURCE_Y_PTR",          0x1002640C, 0, 0xffffffff, 'x', "PrP Source Y Frame Start Address" },
+{ "PRP_SOURCE_CB_PTR",         0x10026410, 0, 0xffffffff, 'x', "PrP Source CB Frame Start Address" },
+{ "PRP_SOURCE_CR_PTR",         0x10026414, 0, 0xffffffff, 'x', "PrP Source CR Frame Start Address" },
+{ "PRP_DEST_RGB1_PTR",         0x10026418, 0, 0xffffffff, 'x', "PrP Destination RGB Frame-1 Start Address" },
+{ "PRP_DEST_RGB2_PTR",         0x1002641C, 0, 0xffffffff, 'x', "PrP Destination RGB Frame-2 Start Address" },
+{ "PRP_DEST_Y_PTR",            0x10026420, 0, 0xffffffff, 'x', "PrP Destination Y Frame Start Address" },
+{ "PRP_DEST_CB_PTR",           0x10026424, 0, 0xffffffff, 'x', "PrP Destination CB Frame Start Address" },
+{ "PRP_DEST_CR_PTR",           0x10026428, 0, 0xffffffff, 'x', "PrP Destination CR Frame Start Address" },
+{ "PRP_SOURCE_FRAME_SIZE",     0x1002642C, 0, 0xffffffff, 'x', "PrP Source Frame Size Register" },
+{ "PRP_CH1_LINE_STRIDE",       0x10026430, 0, 0xffffffff, 'x', "PrP Channel-1 Line stride Register" },
+{ "PRP_SRC_PIXEL_FORMAT_CNTL", 0x10026434, 0, 0xffffffff, 'x', "PrP Source Pixel Format Control Register" },
+{ "PRP_CH1_PIXEL_FORMAT_CNTL", 0x10026438, 0, 0xffffffff, 'x', "PrP CH1 Pixel Format Control Register" },
+{ "PRP_CH1_OUT_IMAGE_SIZE",    0x1002643C, 0, 0xffffffff, 'x', "PrP CH1 Output Image Size Register" },
+{ "PRP_CH2_OUT_IMAGE_SIZE",    0x10026440, 0, 0xffffffff, 'x', "PrP CH2 Output Image Size Register" },
+{ "PRP_SOURCE_LINE_STRIDE",    0x10026444, 0, 0xffffffff, 'x', "PrP Source Line Stride Register" },
+{ "PRP_CSC_COEFF_012",         0x10026448, 0, 0xffffffff, 'x', "PrP CSC Coefficients 0, 1, and" },
+{ "PRP_CSC_COEFF_345",         0x1002644C, 0, 0xffffffff, 'x', "PrP CSC Coefficients 3, 4, and" },
+{ "PRP_CSC_COEFF_678",         0x10026450, 0, 0xffffffff, 'x', "PrP CSC Coefficients 6, 7, and" },
+{ "PRP_CH1_HRESIZE_COEFF1",    0x10026454, 0, 0xffffffff, 'x', "PrP CH1 Horizontal Resize Coefficients Register" },
+{ "PRP_CH1_HRESIZE_COEFF2",    0x10026458, 0, 0xffffffff, 'x', "PrP CH1 Horizontal Resize Coefficients Register" },
+{ "PRP_CH1_HRESIZE_VALID",     0x1002645C, 0, 0xffffffff, 'x', "PrP CH1 Horizontal Resize Valid Register" },
+{ "PRP_CH1_VRESIZE_COEFF1",    0x10026460, 0, 0xffffffff, 'x', "PrP CH1 Vertical Resize Coefficients Register" },
+{ "PRP_CH1_VRESIZE_COEFF2",    0x10026464, 0, 0xffffffff, 'x', "PrP CH1 Vertical Resize Coefficients Register" },
+{ "PRP_CH1_VRESIZE_VALID",     0x10026468, 0, 0xffffffff, 'x', "PrP CH1 Vertical Resize Valid Register" },
+{ "PRP_CH2_HRESIZE_COEFF1",    0x1002646C, 0, 0xffffffff, 'x', "PrP CH2 Horizontal Resize Coefficients Register" },
+{ "PRP_CH2_HRESIZE_COEFF2",    0x10026470, 0, 0xffffffff, 'x', "PrP CH2 Horizontal Resize Coefficients Register" },
+{ "PRP_CH2_HRESIZE_VALID",     0x10026474, 0, 0xffffffff, 'x', "PrP CH2 Horizontal Resize Valid Register" },
+{ "PRP_CH2_VRESIZE_COEFF1",    0x10026478, 0, 0xffffffff, 'x', "PrP CH2 Vertical Resize Coefficients Register" },
+{ "PRP_CH2_VRESIZE_COEFF2",    0x1002647C, 0, 0xffffffff, 'x', "PrP CH2 Vertical Resize Coefficients Register" },
+{ "PRP_CH2_VRESIZE_VALID",     0x10026480, 0, 0xffffffff, 'x', "PrP CH2 Vertical Resize Valid Register" },
 // PLLCLK
 { "CSCR",      0x10027000, 0, 0xffffffff, 'x', "Clock Source Control Register" },
 { "MPCTL0",    0x10027004, 0, 0xffffffff, 'x', "MPLL Control Register 0" },


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