[Armadeus-commitlog] SF.net SVN: armadeus:[1155] trunk/firmware/wishbone_example
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[Armadeus-commitlog] SF.net SVN: armadeus:[1155] trunk/firmware/wishbone_example
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From: <Fa...@us...> - 2009-03-12 16:26:17
|
Revision: 1155
http://armadeus.svn.sourceforge.net/armadeus/?rev=1155&view=rev
Author: FabM
Date: 2009-03-12 16:25:53 +0000 (Thu, 12 Mar 2009)
Log Message:
-----------
[FIRMWARE] Updating wishbone example to be compatible with apf27
Modified Paths:
--------------
trunk/firmware/wishbone_example/Makefile
trunk/firmware/wishbone_example/src/button.vhd
trunk/firmware/wishbone_example/src/led.vhd
trunk/firmware/wishbone_example/src/top_wishbone_example.vhd
trunk/firmware/wishbone_example/testbench/top_wishbone_example_tb.vhd
Added Paths:
-----------
trunk/firmware/wishbone_example/intercon.odg
trunk/firmware/wishbone_example/src/intercon.vhd
trunk/firmware/wishbone_example/src/wishbone_example_apf27.ucf
trunk/firmware/wishbone_example/src/wishbone_example_apf9328.ucf
trunk/firmware/wishbone_example/src/wishbone_wrapper.vhd
trunk/firmware/wishbone_example/wb_buttonled.odg
Removed Paths:
-------------
trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd
trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd
trunk/firmware/wishbone_example/src/wishbone_example.ucf
Modified: trunk/firmware/wishbone_example/Makefile
===================================================================
--- trunk/firmware/wishbone_example/Makefile 2009-03-12 16:03:28 UTC (rev 1154)
+++ trunk/firmware/wishbone_example/Makefile 2009-03-12 16:25:53 UTC (rev 1155)
@@ -11,12 +11,12 @@
SYNTHESIS_FILE=$(PROJECT)_synthesis.vhd
PLACE_AND_ROUTE_FILE=$(PROJECT)_timesim.vhd
FILES=src/top_wishbone_example.vhd \
- src/imx9328_wb16_wrapper.vhd \
+ src/wishbone_wrapper.vhd \
src/rstgen_syscon.vhd \
src/irq_mngr.vhd \
src/led.vhd \
src/button.vhd \
- src/imx9328_wb16_wrapper00_mwb16_intercon.vhd \
+ src/intercon.vhd \
testbench/apf_test_pkg.vhd
# testbench
Added: trunk/firmware/wishbone_example/intercon.odg
===================================================================
(Binary files differ)
Property changes on: trunk/firmware/wishbone_example/intercon.odg
___________________________________________________________________
Added: svn:mime-type
+ application/octet-stream
Modified: trunk/firmware/wishbone_example/src/button.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/button.vhd 2009-03-12 16:03:28 UTC (rev 1154)
+++ trunk/firmware/wishbone_example/src/button.vhd 2009-03-12 16:25:53 UTC (rev 1155)
@@ -34,7 +34,7 @@
-- irq
irq : out std_logic ;
-- fpga input
- button : in std_logic
+ button_i : in std_logic
);
end entity;
@@ -52,7 +52,7 @@
if gls_reset = '1' then
reg <= (others => '0');
elsif rising_edge(gls_clk) then
- reg <= "000000000000000"&button;
+ reg <= "000000000000000"&button_i;
end if;
end process cbutton;
@@ -64,12 +64,12 @@
irq <= '0';
button_r <= '0';
elsif rising_edge(gls_clk) then
- if button_r /= button then
+ if button_r /= button_i then
irq <= '1';
else
irq <= '0';
end if;
- button_r <= button;
+ button_r <= button_i;
end if;
end process pbutton;
Deleted: trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd 2009-03-12 16:03:28 UTC (rev 1154)
+++ trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd 2009-03-12 16:25:53 UTC (rev 1155)
@@ -1,95 +0,0 @@
--------------------------------------------------------------------------------
---
--- File : imx9328_wb16_wrapper.vhd
--- Related files : (none)
---
--- Author(s) : Fabrice Mousset (fab...@la...)
--- Project : i.MX wrapper to Wishbone bus
---
--- Creation Date : 2007/01/19
---
--- Description : This is the top file of the IP
--------------------------------------------------------------------------------
--- Modifications :
------
--- 2008/03/05
--- Fabien Marteau (fab...@ar...)
--- adding comments and changing some signals names
---
--------------------------------------------------------------------------------
-
-library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.numeric_std.all;
-
--- ----------------------------------------------------------------------------
- Entity imx9328_wb16_wrapper is
--- ----------------------------------------------------------------------------
- port
- (
- -- i.MX Signals
- imx_address : in std_logic_vector(11 downto 0); -- LSB not used
- imx_data : inout std_logic_vector(15 downto 0);
- imx_cs_n : in std_logic;
- imx_oe_n : in std_logic;
- imx_eb3_n : in std_logic;
-
- -- Global Signals
- gls_reset : in std_logic;
- gls_clk : in std_logic;
-
- -- Interrupt out for write error
--- int_err : out std_logic;
-
- -- Wishbone interface signals
- wbm_address : out std_logic_vector(12 downto 0); -- Address bus
- wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
- wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
- wbm_strobe : out std_logic; -- Data Strobe
- wbm_write : out std_logic; -- Write access
- wbm_ack : in std_logic ; -- acknowledge
- wbm_cycle : out std_logic -- bus cycle in progress
- );
- end entity;
-
--- ----------------------------------------------------------------------------
- Architecture RTL of imx9328_wb16_wrapper is
--- ----------------------------------------------------------------------------
-
-signal write : std_logic;
-signal read : std_logic;
-signal strobe : std_logic;
-signal writedata : std_logic_vector(15 downto 0);
-signal address : std_logic_vector(12 downto 0);
-
-begin
-
--- ----------------------------------------------------------------------------
--- External signals synchronization process
--- ----------------------------------------------------------------------------
-process(gls_clk, gls_reset)
-begin
- if(gls_reset='1') then
- write <= '0';
- read <= '0';
- strobe <= '0';
- writedata <= (others => '0');
- address <= (others => '0');
- elsif(rising_edge(gls_clk)) then
- strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb3_n);
- write <= not (imx_cs_n or imx_eb3_n);
- read <= not (imx_cs_n or imx_oe_n);
- address <= imx_address & '0';
- writedata <= imx_data;
- end if;
-end process;
-
-wbm_address <= address when (strobe = '1') else (others => '0');
-wbm_writedata <= writedata when (write = '1') else (others => '0');
-wbm_strobe <= strobe;
-wbm_write <= write;
-wbm_cycle <= strobe;
-
-imx_data <= wbm_readdata when(read = '1' ) else (others => 'Z');
-
-end architecture RTL;
Deleted: trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd 2009-03-12 16:03:28 UTC (rev 1154)
+++ trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd 2009-03-12 16:25:53 UTC (rev 1155)
@@ -1,168 +0,0 @@
----------------------------------------------------------------------------
--- Company : Automaticaly generated by POD
--- Author(s) :
---
--- Creation Date : 2009-03-03
--- File : imx9328_wb16_wrapper00_mwb16.vhd
---
--- Abstract :
--- Connect slaves to mwb16 from imx9328_wb16_wrapper00
---
----------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.all;
-
-Entity imx9328_wb16_wrapper00_mwb16 is
- port
- (
-
- -- irq_mngr00_swb16 connection
- irq_mngr00_wbs_s1_address : out std_logic_vector(1 downto 0);
- irq_mngr00_wbs_s1_readdata : in std_logic_vector(15 downto 0);
- irq_mngr00_wbs_s1_writedata : out std_logic_vector(15 downto 0);
- irq_mngr00_wbs_s1_ack : in std_logic;
- irq_mngr00_wbs_s1_strobe : out std_logic;
- irq_mngr00_wbs_s1_cycle : out std_logic;
- irq_mngr00_wbs_s1_write : out std_logic;
-
- -- irq_mngr00_candr connection
- irq_mngr00_gls_clk : out std_logic;
- irq_mngr00_gls_reset : out std_logic;
-
- -- led0_swb16 connection
- led0_wbs_add : out std_logic;
- led0_wbs_writedata : out std_logic_vector(15 downto 0);
- led0_wbs_readdata : in std_logic_vector(15 downto 0);
- led0_wbs_strobe : out std_logic;
- led0_wbs_cycle : out std_logic;
- led0_wbs_write : out std_logic;
- led0_wbs_ack : in std_logic;
-
- -- led0_candr connection
- led0_gls_reset : out std_logic;
- led0_gls_clk : out std_logic;
-
- -- button0_swb16 connection
- button0_wbs_add : out std_logic;
- button0_wbs_readdata : in std_logic_vector(15 downto 0);
- button0_wbs_strobe : out std_logic;
- button0_wbs_write : out std_logic;
- button0_wbs_ack : in std_logic;
- button0_wbs_cycle : out std_logic;
-
- -- button0_candr connection
- button0_gls_reset : out std_logic;
- button0_gls_clk : out std_logic;
-
- -- imx9328_wb16_wrapper00_mwb16 connection
- imx9328_wb16_wrapper00_wbm_address : in std_logic_vector(12 downto 0);
- imx9328_wb16_wrapper00_wbm_readdata : out std_logic_vector(15 downto 0);
- imx9328_wb16_wrapper00_wbm_writedata : in std_logic_vector(15 downto 0);
- imx9328_wb16_wrapper00_wbm_strobe : in std_logic;
- imx9328_wb16_wrapper00_wbm_write : in std_logic;
- imx9328_wb16_wrapper00_wbm_ack : out std_logic;
- imx9328_wb16_wrapper00_wbm_cycle : in std_logic;
-
- -- imx9328_wb16_wrapper00_candr connection
- imx9328_wb16_wrapper00_gls_reset : out std_logic;
- imx9328_wb16_wrapper00_gls_clk : out std_logic;
-
- -- rstgen_syscon00_imx9328_wb16_wrapper00 connection
- rstgen_syscon00_gls_clk : in std_logic;
- rstgen_syscon00_gls_reset : in std_logic
- );
-end entity;
-
-architecture imx9328_wb16_wrapper00_mwb16_1 of imx9328_wb16_wrapper00_mwb16 is
- signal irq_mngr00_swb16_cs : std_logic := '0' ;
- signal led0_swb16_cs : std_logic := '0' ;
- signal button0_swb16_cs : std_logic := '0' ;
-begin
-
- -- Clock and Reset connection
- irq_mngr00_gls_clk <= rstgen_syscon00_gls_clk;
- irq_mngr00_gls_reset <= rstgen_syscon00_gls_reset;
-
- led0_gls_reset <= rstgen_syscon00_gls_reset;
- led0_gls_clk <= rstgen_syscon00_gls_clk;
-
- button0_gls_reset <= rstgen_syscon00_gls_reset;
- button0_gls_clk <= rstgen_syscon00_gls_clk;
-
- imx9328_wb16_wrapper00_gls_reset <= rstgen_syscon00_gls_reset;
- imx9328_wb16_wrapper00_gls_clk <= rstgen_syscon00_gls_clk;
-
-
- -- Address decoding --
- -----------------------
- irq_mngr00_wbs_s1_address <= imx9328_wb16_wrapper00_wbm_address(2 downto 1);
- led0_wbs_add <= imx9328_wb16_wrapper00_wbm_address(1);
- button0_wbs_add <= imx9328_wb16_wrapper00_wbm_address(1);
-
- decodeproc : process(rstgen_syscon00_gls_clk,rstgen_syscon00_gls_reset,imx9328_wb16_wrapper00_wbm_address)
- begin
- if rstgen_syscon00_gls_reset='1' then
- irq_mngr00_swb16_cs <= '0';
- led0_swb16_cs <= '0';
- button0_swb16_cs <= '0';
- elsif rising_edge(rstgen_syscon00_gls_clk) then
-
- if imx9328_wb16_wrapper00_wbm_address(12 downto 3)="0000000000" and imx9328_wb16_wrapper00_wbm_strobe='1' then
- irq_mngr00_swb16_cs <= '1';
- else
- irq_mngr00_swb16_cs <= '0';
- end if;
-
- if imx9328_wb16_wrapper00_wbm_address(12 downto 2)="00000000010" and imx9328_wb16_wrapper00_wbm_strobe='1' then
- led0_swb16_cs <= '1';
- else
- led0_swb16_cs <= '0';
- end if;
-
- if imx9328_wb16_wrapper00_wbm_address(12 downto 2)="00000000011" and imx9328_wb16_wrapper00_wbm_strobe='1' then
- button0_swb16_cs <= '1';
- else
- button0_swb16_cs <= '0';
- end if;
-
- end if;
- end process decodeproc;
-
- -----------------------------
- -- Control signals to slave
- -----------------------------
-
- -- for irq_mngr00
- irq_mngr00_wbs_s1_strobe <= (imx9328_wb16_wrapper00_wbm_strobe and irq_mngr00_swb16_cs );
- irq_mngr00_wbs_s1_cycle <= (imx9328_wb16_wrapper00_wbm_cycle and irq_mngr00_swb16_cs );
- irq_mngr00_wbs_s1_write <= (imx9328_wb16_wrapper00_wbm_write and irq_mngr00_swb16_cs );
- irq_mngr00_wbs_s1_writedata <= imx9328_wb16_wrapper00_wbm_writedata when (imx9328_wb16_wrapper00_wbm_write and irq_mngr00_swb16_cs ) = '1' else (others => '0');
-
- -- for led0
- led0_wbs_strobe <= (imx9328_wb16_wrapper00_wbm_strobe and led0_swb16_cs );
- led0_wbs_cycle <= (imx9328_wb16_wrapper00_wbm_cycle and led0_swb16_cs );
- led0_wbs_write <= (imx9328_wb16_wrapper00_wbm_write and led0_swb16_cs );
- led0_wbs_writedata <= imx9328_wb16_wrapper00_wbm_writedata when (imx9328_wb16_wrapper00_wbm_write and led0_swb16_cs ) = '1' else (others => '0');
-
- -- for button0
- button0_wbs_strobe <= (imx9328_wb16_wrapper00_wbm_strobe and button0_swb16_cs );
- button0_wbs_cycle <= (imx9328_wb16_wrapper00_wbm_cycle and button0_swb16_cs );
- button0_wbs_write <= '0';
-
-
- -------------------------------
- -- Control signal for master --
- -------------------------------
- imx9328_wb16_wrapper00_wbm_readdata <= irq_mngr00_wbs_s1_readdata when irq_mngr00_swb16_cs='1' else
- led0_wbs_readdata when led0_swb16_cs='1' else
- button0_wbs_readdata when button0_swb16_cs='1' else
- (others => '0');
- imx9328_wb16_wrapper00_wbm_ack <= (irq_mngr00_wbs_s1_ack and irq_mngr00_swb16_cs)
- or
- (led0_wbs_ack and led0_swb16_cs)
- or
- (button0_wbs_ack and button0_swb16_cs);
-
-end architecture imx9328_wb16_wrapper00_mwb16_1;
Copied: trunk/firmware/wishbone_example/src/intercon.vhd (from rev 1108, trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd)
===================================================================
--- trunk/firmware/wishbone_example/src/intercon.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/intercon.vhd 2009-03-12 16:25:53 UTC (rev 1155)
@@ -0,0 +1,168 @@
+---------------------------------------------------------------------------
+-- Company : Automaticaly generated by POD
+-- Author(s) :
+--
+-- Creation Date : 2009-03-03
+-- File : intercon.vhd
+--
+-- Abstract :
+-- Connect slaves to mwb16 from wrapper
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+Entity intercon is
+ port
+ (
+
+ -- irq_mngr00_swb16 connection
+ irq_mngr00_wbs_s1_address : out std_logic_vector(1 downto 0);
+ irq_mngr00_wbs_s1_readdata : in std_logic_vector(15 downto 0);
+ irq_mngr00_wbs_s1_writedata : out std_logic_vector(15 downto 0);
+ irq_mngr00_wbs_s1_ack : in std_logic;
+ irq_mngr00_wbs_s1_strobe : out std_logic;
+ irq_mngr00_wbs_s1_cycle : out std_logic;
+ irq_mngr00_wbs_s1_write : out std_logic;
+
+ -- irq_mngr00_candr connection
+ irq_mngr00_gls_clk : out std_logic;
+ irq_mngr00_gls_reset : out std_logic;
+
+ -- led0_swb16 connection
+ led0_wbs_add : out std_logic;
+ led0_wbs_writedata : out std_logic_vector(15 downto 0);
+ led0_wbs_readdata : in std_logic_vector(15 downto 0);
+ led0_wbs_strobe : out std_logic;
+ led0_wbs_cycle : out std_logic;
+ led0_wbs_write : out std_logic;
+ led0_wbs_ack : in std_logic;
+
+ -- led0_candr connection
+ led0_gls_reset : out std_logic;
+ led0_gls_clk : out std_logic;
+
+ -- button0_swb16 connection
+ button0_wbs_add : out std_logic;
+ button0_wbs_readdata : in std_logic_vector(15 downto 0);
+ button0_wbs_strobe : out std_logic;
+ button0_wbs_write : out std_logic;
+ button0_wbs_ack : in std_logic;
+ button0_wbs_cycle : out std_logic;
+
+ -- button0_candr connection
+ button0_gls_reset : out std_logic;
+ button0_gls_clk : out std_logic;
+
+ -- intercon connection
+ wrapper_wbm_address : in std_logic_vector(12 downto 0);
+ wrapper_wbm_readdata : out std_logic_vector(15 downto 0);
+ wrapper_wbm_writedata : in std_logic_vector(15 downto 0);
+ wrapper_wbm_strobe : in std_logic;
+ wrapper_wbm_write : in std_logic;
+ wrapper_wbm_ack : out std_logic;
+ wrapper_wbm_cycle : in std_logic;
+
+ -- wrapper_candr connection
+ wrapper_gls_reset : out std_logic;
+ wrapper_gls_clk : out std_logic;
+
+ -- rstgen_syscon00_wrapper connection
+ rstgen_syscon00_gls_clk : in std_logic;
+ rstgen_syscon00_gls_reset : in std_logic
+ );
+end entity;
+
+architecture intercon_1 of intercon is
+ signal irq_mngr00_swb16_cs : std_logic := '0' ;
+ signal led0_swb16_cs : std_logic := '0' ;
+ signal button0_swb16_cs : std_logic := '0' ;
+begin
+
+ -- Clock and Reset connection
+ irq_mngr00_gls_clk <= rstgen_syscon00_gls_clk;
+ irq_mngr00_gls_reset <= rstgen_syscon00_gls_reset;
+
+ led0_gls_reset <= rstgen_syscon00_gls_reset;
+ led0_gls_clk <= rstgen_syscon00_gls_clk;
+
+ button0_gls_reset <= rstgen_syscon00_gls_reset;
+ button0_gls_clk <= rstgen_syscon00_gls_clk;
+
+ wrapper_gls_reset <= rstgen_syscon00_gls_reset;
+ wrapper_gls_clk <= rstgen_syscon00_gls_clk;
+
+
+ -- Address decoding --
+ -----------------------
+ irq_mngr00_wbs_s1_address <= wrapper_wbm_address(2 downto 1);
+ led0_wbs_add <= wrapper_wbm_address(1);
+ button0_wbs_add <= wrapper_wbm_address(1);
+
+ decodeproc : process(rstgen_syscon00_gls_clk,rstgen_syscon00_gls_reset,wrapper_wbm_address)
+ begin
+ if rstgen_syscon00_gls_reset='1' then
+ irq_mngr00_swb16_cs <= '0';
+ led0_swb16_cs <= '0';
+ button0_swb16_cs <= '0';
+ elsif rising_edge(rstgen_syscon00_gls_clk) then
+
+ if wrapper_wbm_address(12 downto 3)="0000000000" and wrapper_wbm_strobe='1' then
+ irq_mngr00_swb16_cs <= '1';
+ else
+ irq_mngr00_swb16_cs <= '0';
+ end if;
+
+ if wrapper_wbm_address(12 downto 2)="00000000010" and wrapper_wbm_strobe='1' then
+ led0_swb16_cs <= '1';
+ else
+ led0_swb16_cs <= '0';
+ end if;
+
+ if wrapper_wbm_address(12 downto 2)="00000000011" and wrapper_wbm_strobe='1' then
+ button0_swb16_cs <= '1';
+ else
+ button0_swb16_cs <= '0';
+ end if;
+
+ end if;
+ end process decodeproc;
+
+ -----------------------------
+ -- Control signals to slave
+ -----------------------------
+
+ -- for irq_mngr00
+ irq_mngr00_wbs_s1_strobe <= (wrapper_wbm_strobe and irq_mngr00_swb16_cs );
+ irq_mngr00_wbs_s1_cycle <= (wrapper_wbm_cycle and irq_mngr00_swb16_cs );
+ irq_mngr00_wbs_s1_write <= (wrapper_wbm_write and irq_mngr00_swb16_cs );
+ irq_mngr00_wbs_s1_writedata <= wrapper_wbm_writedata when (wrapper_wbm_write and irq_mngr00_swb16_cs ) = '1' else (others => '0');
+
+ -- for led0
+ led0_wbs_strobe <= (wrapper_wbm_strobe and led0_swb16_cs );
+ led0_wbs_cycle <= (wrapper_wbm_cycle and led0_swb16_cs );
+ led0_wbs_write <= (wrapper_wbm_write and led0_swb16_cs );
+ led0_wbs_writedata <= wrapper_wbm_writedata when (wrapper_wbm_write and led0_swb16_cs ) = '1' else (others => '0');
+
+ -- for button0
+ button0_wbs_strobe <= (wrapper_wbm_strobe and button0_swb16_cs );
+ button0_wbs_cycle <= (wrapper_wbm_cycle and button0_swb16_cs );
+ button0_wbs_write <= '0';
+
+
+ -------------------------------
+ -- Control signal for master --
+ -------------------------------
+ wrapper_wbm_readdata <= irq_mngr00_wbs_s1_readdata when irq_mngr00_swb16_cs='1' else
+ led0_wbs_readdata when led0_swb16_cs='1' else
+ button0_wbs_readdata when button0_swb16_cs='1' else
+ (others => '0');
+ wrapper_wbm_ack <= (irq_mngr00_wbs_s1_ack and irq_mngr00_swb16_cs)
+ or
+ (led0_wbs_ack and led0_swb16_cs)
+ or
+ (button0_wbs_ack and button0_swb16_cs);
+
+end architecture intercon_1;
Modified: trunk/firmware/wishbone_example/src/led.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/led.vhd 2009-03-12 16:03:28 UTC (rev 1154)
+++ trunk/firmware/wishbone_example/src/led.vhd 2009-03-12 16:25:53 UTC (rev 1155)
@@ -34,7 +34,7 @@
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
- led : out std_logic
+ led_o : out std_logic
);
end entity led;
@@ -45,8 +45,8 @@
signal reg : std_logic_vector( wb_size-1 downto 0);
begin
--- connect led
-led <= reg(0);
+-- connect led_o
+led_o <= reg(0);
wbs_ack <= wbs_strobe;
Modified: trunk/firmware/wishbone_example/src/top_wishbone_example.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/top_wishbone_example.vhd 2009-03-12 16:03:28 UTC (rev 1154)
+++ trunk/firmware/wishbone_example/src/top_wishbone_example.vhd 2009-03-12 16:25:53 UTC (rev 1155)
@@ -18,15 +18,15 @@
port
(
- imx9328_wb16_wrapper00_imx_data : inout std_logic_vector(15 downto 0);
- imx9328_wb16_wrapper00_imx_address : in std_logic_vector(11 downto 0);
- rstgen_syscon00_ext_clk : in std_logic;
- imx9328_wb16_wrapper00_imx_cs_n : in std_logic;
- imx9328_wb16_wrapper00_imx_eb3_n : in std_logic;
- imx9328_wb16_wrapper00_imx_oe_n : in std_logic;
- irq_mngr00_gls_irq : out std_logic;
- led0_led : out std_logic;
- button0_button : in std_logic
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_address : in std_logic_vector(11 downto 0);
+ ext_clk : in std_logic;
+ imx_cs_n : in std_logic;
+ imx_eb3_n : in std_logic;
+ imx_oe_n : in std_logic;
+ gls_irq : out std_logic;
+ led_o : out std_logic;
+ button_i : in std_logic
);
end entity top_wishbone_example;
@@ -53,7 +53,7 @@
);
port (
-- int_led
- led : out std_logic;
+ led_o : out std_logic;
-- candr
gls_reset : in std_logic;
gls_clk : in std_logic;
@@ -74,7 +74,7 @@
);
port (
-- int_button
- button : in std_logic;
+ button_i : in std_logic;
irq : out std_logic;
-- candr
gls_reset : in std_logic;
@@ -89,24 +89,24 @@
);
end component;
- component imx9328_wb16_wrapper
+ component wishbone_wrapper
port (
-- eim
imx_address : in std_logic_vector(11 downto 0);
- imx_data : inout std_logic_vector(15 downto 0);
- imx_cs_n : in std_logic;
- imx_oe_n : in std_logic;
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_oe_n : in std_logic;
imx_eb3_n : in std_logic;
-- candr
- gls_reset : in std_logic;
- gls_clk : in std_logic;
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
-- mwb16
wbm_address : out std_logic_vector(12 downto 0);
- wbm_readdata : in std_logic_vector(15 downto 0);
- wbm_writedata : out std_logic_vector(15 downto 0);
- wbm_strobe : out std_logic;
+ wbm_readdata : in std_logic_vector(15 downto 0);
+ wbm_writedata: out std_logic_vector(15 downto 0);
+ wbm_strobe : out std_logic;
wbm_write : out std_logic;
- wbm_ack : in std_logic;
+ wbm_ack : in std_logic;
wbm_cycle : out std_logic
);
end component;
@@ -136,7 +136,7 @@
);
end component;
- component imx9328_wb16_wrapper00_mwb16
+ component intercon
port (
-- irq_mngr00_swb16
irq_mngr00_wbs_s1_address : out std_logic_vector(1 downto 0);
@@ -170,18 +170,18 @@
-- button0_candr
button0_gls_reset : out std_logic;
button0_gls_clk : out std_logic;
- -- imx9328_wb16_wrapper00_mwb16
- imx9328_wb16_wrapper00_wbm_address : in std_logic_vector(12 downto 0);
- imx9328_wb16_wrapper00_wbm_readdata : out std_logic_vector(15 downto 0);
- imx9328_wb16_wrapper00_wbm_writedata : in std_logic_vector(15 downto 0);
- imx9328_wb16_wrapper00_wbm_strobe : in std_logic;
- imx9328_wb16_wrapper00_wbm_write : in std_logic;
- imx9328_wb16_wrapper00_wbm_ack : out std_logic;
- imx9328_wb16_wrapper00_wbm_cycle : in std_logic;
- -- imx9328_wb16_wrapper00_candr
- imx9328_wb16_wrapper00_gls_reset : out std_logic;
- imx9328_wb16_wrapper00_gls_clk : out std_logic;
- -- rstgen_syscon00_imx9328_wb16_wrapper00
+ -- wrapper
+ wrapper_wbm_address : in std_logic_vector(12 downto 0);
+ wrapper_wbm_readdata : out std_logic_vector(15 downto 0);
+ wrapper_wbm_writedata : in std_logic_vector(15 downto 0);
+ wrapper_wbm_strobe : in std_logic;
+ wrapper_wbm_write : in std_logic;
+ wrapper_wbm_ack : out std_logic;
+ wrapper_wbm_cycle : in std_logic;
+ -- wrapper_candr
+ wrapper_gls_reset : out std_logic;
+ wrapper_gls_clk : out std_logic;
+ -- rstgen_syscon00_wrapper
rstgen_syscon00_gls_clk : in std_logic;
rstgen_syscon00_gls_reset : in std_logic
);
@@ -190,153 +190,90 @@
-- Signals declaration
-------------------------
- -- imx9328_wb16_wrapper00
- -- eim
- -- candr
- signal imx9328_wb16_wrapper00_gls_reset : std_logic;
- signal imx9328_wb16_wrapper00_gls_clk : std_logic;
- -- mwb16
- signal imx9328_wb16_wrapper00_wbm_address : std_logic_vector(12 downto 0);
- signal imx9328_wb16_wrapper00_wbm_readdata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_wbm_writedata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_wbm_strobe : std_logic;
- signal imx9328_wb16_wrapper00_wbm_write : std_logic;
- signal imx9328_wb16_wrapper00_wbm_ack : std_logic;
- signal imx9328_wb16_wrapper00_wbm_cycle : std_logic;
-
- -- rstgen_syscon00
- -- candr
- signal rstgen_syscon00_gls_clk : std_logic;
- signal rstgen_syscon00_gls_reset : std_logic;
- -- clk_ext
-
- -- irq_mngr00
- -- candr
- signal irq_mngr00_gls_clk : std_logic;
- signal irq_mngr00_gls_reset : std_logic;
- -- swb16
- signal irq_mngr00_wbs_s1_address : std_logic_vector(1 downto 0);
- signal irq_mngr00_wbs_s1_readdata : std_logic_vector(15 downto 0);
- signal irq_mngr00_wbs_s1_writedata : std_logic_vector(15 downto 0);
- signal irq_mngr00_wbs_s1_ack : std_logic;
- signal irq_mngr00_wbs_s1_strobe : std_logic;
- signal irq_mngr00_wbs_s1_cycle : std_logic;
- signal irq_mngr00_wbs_s1_write : std_logic;
- -- irq
- signal irq_mngr00_irqport : std_logic_vector(0 downto 0);
- -- ext_irq
-
- -- led0
- -- int_led
- -- candr
- signal led0_gls_reset : std_logic;
- signal led0_gls_clk : std_logic;
- -- swb16
- signal led0_wbs_add : std_logic;
- signal led0_wbs_writedata : std_logic_vector(15 downto 0);
- signal led0_wbs_readdata : std_logic_vector(15 downto 0);
- signal led0_wbs_strobe : std_logic;
- signal led0_wbs_cycle : std_logic;
- signal led0_wbs_write : std_logic;
- signal led0_wbs_ack : std_logic;
-
- -- button0
- -- int_button
- signal button0_irq : std_logic;
- -- candr
- signal button0_gls_reset : std_logic;
- signal button0_gls_clk : std_logic;
- -- swb16
- signal button0_wbs_add : std_logic;
- signal button0_wbs_readdata : std_logic_vector(15 downto 0);
- signal button0_wbs_strobe : std_logic;
- signal button0_wbs_write : std_logic;
- signal button0_wbs_ack : std_logic;
- signal button0_wbs_cycle : std_logic;
-
- -- imx9328_wb16_wrapper00_mwb16_intercon
+ -- intercon
-- irq_mngr00_swb16
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_address : std_logic_vector(1 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_readdata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_writedata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_ack : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_strobe : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_cycle : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_write : std_logic;
+ signal intercon_irq_mngr00_wbs_s1_address : std_logic_vector(1 downto 0);
+ signal intercon_irq_mngr00_wbs_s1_readdata : std_logic_vector(15 downto 0);
+ signal intercon_irq_mngr00_wbs_s1_writedata : std_logic_vector(15 downto 0);
+ signal intercon_irq_mngr00_wbs_s1_ack : std_logic;
+ signal intercon_irq_mngr00_wbs_s1_strobe : std_logic;
+ signal intercon_irq_mngr00_wbs_s1_cycle : std_logic;
+ signal intercon_irq_mngr00_wbs_s1_write : std_logic;
-- irq_mngr00_candr
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_gls_clk : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_gls_reset : std_logic;
+ signal intercon_irq_mngr00_gls_clk : std_logic;
+ signal intercon_irq_mngr00_gls_reset : std_logic;
-- led0_swb16
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_add : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_writedata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_readdata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_strobe : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_cycle : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_write : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_ack : std_logic;
+ signal intercon_led0_wbs_add : std_logic;
+ signal intercon_led0_wbs_writedata : std_logic_vector(15 downto 0);
+ signal intercon_led0_wbs_readdata : std_logic_vector(15 downto 0);
+ signal intercon_led0_wbs_strobe : std_logic;
+ signal intercon_led0_wbs_cycle : std_logic;
+ signal intercon_led0_wbs_write : std_logic;
+ signal intercon_led0_wbs_ack : std_logic;
-- led0_candr
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_gls_reset : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_led0_gls_clk : std_logic;
+ signal intercon_led0_gls_reset : std_logic;
+ signal intercon_led0_gls_clk : std_logic;
-- button0_swb16
- signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_add : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_readdata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_strobe : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_write : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_ack : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_cycle : std_logic;
+ signal intercon_button0_wbs_add : std_logic;
+ signal intercon_button0_wbs_readdata : std_logic_vector(15 downto 0);
+ signal intercon_button0_wbs_strobe : std_logic;
+ signal intercon_button0_wbs_write : std_logic;
+ signal intercon_button0_wbs_ack : std_logic;
+ signal intercon_button0_wbs_cycle : std_logic;
-- button0_candr
- signal imx9328_wb16_wrapper00_mwb16_intercon_button0_gls_reset : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_button0_gls_clk : std_logic;
- -- imx9328_wb16_wrapper00_mwb16
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_address : std_logic_vector(12 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_readdata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_writedata : std_logic_vector(15 downto 0);
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_strobe : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_write : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_ack : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_cycle : std_logic;
- -- imx9328_wb16_wrapper00_candr
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_gls_reset : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_gls_clk : std_logic;
- -- rstgen_syscon00_imx9328_wb16_wrapper00
- signal imx9328_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_clk : std_logic;
- signal imx9328_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_reset : std_logic;
+ signal intercon_button0_gls_reset : std_logic;
+ signal intercon_button0_gls_clk : std_logic;
+ -- wrapper
+ signal intercon_wrapper_wbm_address : std_logic_vector(12 downto 0);
+ signal intercon_wrapper_wbm_readdata : std_logic_vector(15 downto 0);
+ signal intercon_wrapper_wbm_writedata : std_logic_vector(15 downto 0);
+ signal intercon_wrapper_wbm_strobe : std_logic;
+ signal intercon_wrapper_wbm_write : std_logic;
+ signal intercon_wrapper_wbm_ack : std_logic;
+ signal intercon_wrapper_wbm_cycle : std_logic;
+ -- wrapper_candr
+ signal intercon_wrapper_gls_reset : std_logic;
+ signal intercon_wrapper_gls_clk : std_logic;
+ -- rstgen_syscon00_wrapper
+ signal intercon_rstgen_syscon00_gls_clk : std_logic;
+ signal intercon_rstgen_syscon00_gls_reset : std_logic;
- -- void pins
+ -- irq_mngr
+ signal irq_mngr00_irqport : std_logic_vector( 0 downto 0) ;
begin
-------------------------
-- declare instances
-------------------------
- imx9328_wb16_wrapper00 : imx9328_wb16_wrapper
+ wrapper : wishbone_wrapper
port map (
-- eim
- imx_address => imx9328_wb16_wrapper00_imx_address,
- imx_data => imx9328_wb16_wrapper00_imx_data,
- imx_cs_n => imx9328_wb16_wrapper00_imx_cs_n,
- imx_oe_n => imx9328_wb16_wrapper00_imx_oe_n,
- imx_eb3_n => imx9328_wb16_wrapper00_imx_eb3_n,
+ imx_address => imx_address,
+ imx_data => imx_data,
+ imx_cs_n => imx_cs_n,
+ imx_oe_n => imx_oe_n,
+ imx_eb3_n => imx_eb3_n,
-- candr
- gls_reset => imx9328_wb16_wrapper00_gls_reset,
- gls_clk => imx9328_wb16_wrapper00_gls_clk,
+ gls_reset => intercon_wrapper_gls_reset,
+ gls_clk => intercon_wrapper_gls_clk,
-- mwb16
- wbm_address => imx9328_wb16_wrapper00_wbm_address,
- wbm_readdata => imx9328_wb16_wrapper00_wbm_readdata,
- wbm_writedata => imx9328_wb16_wrapper00_wbm_writedata,
- wbm_strobe => imx9328_wb16_wrapper00_wbm_strobe,
- wbm_write => imx9328_wb16_wrapper00_wbm_write,
- wbm_ack => imx9328_wb16_wrapper00_wbm_ack,
- wbm_cycle => imx9328_wb16_wrapper00_wbm_cycle
+ wbm_address => intercon_wrapper_wbm_address,
+ wbm_readdata => intercon_wrapper_wbm_readdata,
+ wbm_writedata=> intercon_wrapper_wbm_writedata,
+ wbm_strobe => intercon_wrapper_wbm_strobe,
+ wbm_write => intercon_wrapper_wbm_write,
+ wbm_ack => intercon_wrapper_wbm_ack,
+ wbm_cycle => intercon_wrapper_wbm_cycle
);
rstgen_syscon00 : rstgen_syscon
port map (
-- candr
- gls_clk => rstgen_syscon00_gls_clk,
- gls_reset => rstgen_syscon00_gls_reset,
+ gls_clk => intercon_rstgen_syscon00_gls_clk,
+ gls_reset => intercon_rstgen_syscon00_gls_reset,
-- clk_ext
- ext_clk => rstgen_syscon00_ext_clk
+ ext_clk => ext_clk
);
irq_mngr00 : irq_mngr
@@ -347,20 +284,20 @@
)
port map (
-- candr
- gls_clk => irq_mngr00_gls_clk,
- gls_reset => irq_mngr00_gls_reset,
+ gls_clk => intercon_irq_mngr00_gls_clk,
+ gls_reset => intercon_irq_mngr00_gls_reset,
-- swb16
- wbs_s1_address => irq_mngr00_wbs_s1_address,
- wbs_s1_readdata => irq_mngr00_wbs_s1_readdata,
- wbs_s1_writedata => irq_mngr00_wbs_s1_writedata,
- wbs_s1_ack => irq_mngr00_wbs_s1_ack,
- wbs_s1_strobe => irq_mngr00_wbs_s1_strobe,
- wbs_s1_cycle => irq_mngr00_wbs_s1_cycle,
- wbs_s1_write => irq_mngr00_wbs_s1_write,
+ wbs_s1_address => intercon_irq_mngr00_wbs_s1_address,
+ wbs_s1_readdata => intercon_irq_mngr00_wbs_s1_readdata,
+ wbs_s1_writedata=> intercon_irq_mngr00_wbs_s1_writedata,
+ wbs_s1_ack => intercon_irq_mngr00_wbs_s1_ack,
+ wbs_s1_strobe => intercon_irq_mngr00_wbs_s1_strobe,
+ wbs_s1_cycle => intercon_irq_mngr00_wbs_s1_cycle,
+ wbs_s1_write => intercon_irq_mngr00_wbs_s1_write,
-- irq
- irqport => irq_mngr00_irqport,
+ irqport => irq_mngr00_irqport,
-- ext_irq
- gls_irq => irq_mngr00_gls_irq
+ gls_irq => gls_irq
);
led0 : led
@@ -370,18 +307,18 @@
)
port map (
-- int_led
- led => led0_led,
+ led_o => led_o,
-- candr
- gls_reset => led0_gls_reset,
- gls_clk => led0_gls_clk,
+ gls_reset => intercon_led0_gls_reset,
+ gls_clk => intercon_led0_gls_clk,
-- swb16
- wbs_add => led0_wbs_add,
- wbs_writedata => led0_wbs_writedata,
- wbs_readdata => led0_wbs_readdata,
- wbs_strobe => led0_wbs_strobe,
- wbs_cycle => led0_wbs_cycle,
- wbs_write => led0_wbs_write,
- wbs_ack => led0_wbs_ack
+ wbs_add => intercon_led0_wbs_add,
+ wbs_writedata=> intercon_led0_wbs_writedata,
+ wbs_readdata => intercon_led0_wbs_readdata,
+ wbs_strobe => intercon_led0_wbs_strobe,
+ wbs_cycle => intercon_led0_wbs_cycle,
+ wbs_write => intercon_led0_wbs_write,
+ wbs_ack => intercon_led0_wbs_ack
);
button0 : button
@@ -390,146 +327,69 @@
)
port map (
-- int_button
- button => button0_button,
- irq => button0_irq,
+ button_i => button_i,
+ irq => irq_mngr00_irqport(0),
-- candr
- gls_reset => button0_gls_reset,
- gls_clk => button0_gls_clk,
+ gls_reset => intercon_button0_gls_reset,
+ gls_clk => intercon_button0_gls_clk,
-- swb16
- wbs_add => button0_wbs_add,
- wbs_readdata => button0_wbs_readdata,
- wbs_strobe => button0_wbs_strobe,
- wbs_write => button0_wbs_write,
- wbs_ack => button0_wbs_ack,
- wbs_cycle => button0_wbs_cycle
+ wbs_add => intercon_button0_wbs_add,
+ wbs_readdata => intercon_button0_wbs_readdata,
+ wbs_strobe => intercon_button0_wbs_strobe,
+ wbs_write => intercon_button0_wbs_write,
+ wbs_ack => intercon_button0_wbs_ack,
+ wbs_cycle => intercon_button0_wbs_cycle
);
- imx9328_wb16_wrapper00_mwb16_intercon : imx9328_wb16_wrapper00_mwb16
+ intercon_intercon : intercon
port map (
-- irq_mngr00_swb16
- irq_mngr00_wbs_s1_address => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_address,
- irq_mngr00_wbs_s1_readdata => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_readdata,
- irq_mngr00_wbs_s1_writedata => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_writedata,
- irq_mngr00_wbs_s1_ack => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_ack,
- irq_mngr00_wbs_s1_strobe => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_strobe,
- irq_mngr00_wbs_s1_cycle => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_cycle,
- irq_mngr00_wbs_s1_write => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_write,
+ irq_mngr00_wbs_s1_address => intercon_irq_mngr00_wbs_s1_address,
+ irq_mngr00_wbs_s1_readdata => intercon_irq_mngr00_wbs_s1_readdata,
+ irq_mngr00_wbs_s1_writedata => intercon_irq_mngr00_wbs_s1_writedata,
+ irq_mngr00_wbs_s1_ack => intercon_irq_mngr00_wbs_s1_ack,
+ irq_mngr00_wbs_s1_strobe => intercon_irq_mngr00_wbs_s1_strobe,
+ irq_mngr00_wbs_s1_cycle => intercon_irq_mngr00_wbs_s1_cycle,
+ irq_mngr00_wbs_s1_write => intercon_irq_mngr00_wbs_s1_write,
-- irq_mngr00_candr
- irq_mngr00_gls_clk => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_gls_clk,
- irq_mngr00_gls_reset => imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_gls_reset,
+ irq_mngr00_gls_clk => intercon_irq_mngr00_gls_clk,
+ irq_mngr00_gls_reset => intercon_irq_mngr00_gls_reset,
-- led0_swb16
- led0_wbs_add => imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_add,
- led0_wbs_writedata => imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_writedata,
- led0_wbs_readdata => imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_readdata,
- led0_wbs_strobe => imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_strobe,
- led0_wbs_cycle => imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_cycle,
- led0_wbs_write => imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_write,
- led0_wbs_ack => imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_ack,
+ led0_wbs_add => intercon_led0_wbs_add,
+ led0_wbs_writedata => intercon_led0_wbs_writedata,
+ led0_wbs_readdata => intercon_led0_wbs_readdata,
+ led0_wbs_strobe => intercon_led0_wbs_strobe,
+ led0_wbs_cycle => intercon_led0_wbs_cycle,
+ led0_wbs_write => intercon_led0_wbs_write,
+ led0_wbs_ack => intercon_led0_wbs_ack,
-- led0_candr
- led0_gls_reset => imx9328_wb16_wrapper00_mwb16_intercon_led0_gls_reset,
- led0_gls_clk => imx9328_wb16_wrapper00_mwb16_intercon_led0_gls_clk,
+ led0_gls_reset => intercon_led0_gls_reset,
+ led0_gls_clk => intercon_led0_gls_clk,
-- button0_swb16
- button0_wbs_add => imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_add,
- button0_wbs_readdata => imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_readdata,
- button0_wbs_strobe => imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_strobe,
- button0_wbs_write => imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_write,
- button0_wbs_ack => imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_ack,
- button0_wbs_cycle => imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_cycle,
+ button0_wbs_add => intercon_button0_wbs_add,
+ button0_wbs_readdata => intercon_button0_wbs_readdata,
+ button0_wbs_strobe => intercon_button0_wbs_strobe,
+ button0_wbs_write => intercon_button0_wbs_write,
+ button0_wbs_ack => intercon_button0_wbs_ack,
+ button0_wbs_cycle => intercon_button0_wbs_cycle,
-- button0_candr
- button0_gls_reset => imx9328_wb16_wrapper00_mwb16_intercon_button0_gls_reset,
- button0_gls_clk => imx9328_wb16_wrapper00_mwb16_intercon_button0_gls_clk,
- -- imx9328_wb16_wrapper00_mwb16
- imx9328_wb16_wrapper00_wbm_address => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_address,
- imx9328_wb16_wrapper00_wbm_readdata => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_readdata,
- imx9328_wb16_wrapper00_wbm_writedata => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_writedata,
- imx9328_wb16_wrapper00_wbm_strobe => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_strobe,
- imx9328_wb16_wrapper00_wbm_write => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_write,
- imx9328_wb16_wrapper00_wbm_ack => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_ack,
- imx9328_wb16_wrapper00_wbm_cycle => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_cycle,
- -- imx9328_wb16_wrapper00_candr
- imx9328_wb16_wrapper00_gls_reset => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_gls_reset,
- imx9328_wb16_wrapper00_gls_clk => imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_gls_clk,
- -- rstgen_syscon00_imx9328_wb16_wrapper00
- rstgen_syscon00_gls_clk => imx9328_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_clk,
- rstgen_syscon00_gls_reset => imx9328_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_reset
+ button0_gls_reset => intercon_button0_gls_reset,
+ button0_gls_clk => intercon_button0_gls_clk,
+ -- intercon
+ wrapper_wbm_address => intercon_wrapper_wbm_address,
+ wrapper_wbm_readdata => intercon_wrapper_wbm_readdata,
+ wrapper_wbm_writedata => intercon_wrapper_wbm_writedata,
+ wrapper_wbm_strobe => intercon_wrapper_wbm_strobe,
+ wrapper_wbm_write => intercon_wrapper_wbm_write,
+ wrapper_wbm_ack => intercon_wrapper_wbm_ack,
+ wrapper_wbm_cycle => intercon_wrapper_wbm_cycle,
+ -- wrapper_candr
+ wrapper_gls_reset => intercon_wrapper_gls_reset,
+ wrapper_gls_clk => intercon_wrapper_gls_clk,
+ -- rstgen_syscon00_wrapper
+ rstgen_syscon00_gls_clk => intercon_rstgen_syscon00_gls_clk,
+ rstgen_syscon00_gls_reset => intercon_rstgen_syscon00_gls_reset
);
- ---------------------------
- -- instances connections --
- ---------------------------
-
- -- connect imx9328_wb16_wrapper00
- -- eim
- -- candr
- imx9328_wb16_wrapper00_gls_reset <= imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_gls_reset;
- imx9328_wb16_wrapper00_gls_clk <= imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_gls_clk;
- -- mwb16
- imx9328_wb16_wrapper00_wbm_readdata <= imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_readdata;
- imx9328_wb16_wrapper00_wbm_ack <= imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_ack;
-
- -- connect rstgen_syscon00
- -- candr
- -- clk_ext
-
- -- connect irq_mngr00
- -- candr
- irq_mngr00_gls_clk <= imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_gls_clk;
- irq_mngr00_gls_reset <= imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_gls_reset;
- -- swb16
- irq_mngr00_wbs_s1_address <= imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_address;
- irq_mngr00_wbs_s1_writedata <= imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_writedata;
- irq_mngr00_wbs_s1_strobe <= imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_strobe;
- irq_mngr00_wbs_s1_cycle <= imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_cycle;
- irq_mngr00_wbs_s1_write <= imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_write;
- -- irq
- irq_mngr00_irqport(0) <= button0_irq;
- -- ext_irq
-
- -- connect led0
- -- int_led
- -- candr
- led0_gls_reset <= imx9328_wb16_wrapper00_mwb16_intercon_led0_gls_reset;
- led0_gls_clk <= imx9328_wb16_wrapper00_mwb16_intercon_led0_gls_clk;
- -- swb16
- led0_wbs_add <= imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_add;
- led0_wbs_writedata <= imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_writedata;
- led0_wbs_strobe <= imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_strobe;
- led0_wbs_cycle <= imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_cycle;
- led0_wbs_write <= imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_write;
-
- -- connect button0
- -- int_button
- -- candr
- button0_gls_reset <= imx9328_wb16_wrapper00_mwb16_intercon_button0_gls_reset;
- button0_gls_clk <= imx9328_wb16_wrapper00_mwb16_intercon_button0_gls_clk;
- -- swb16
- button0_wbs_add <= imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_add;
- button0_wbs_strobe <= imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_strobe;
- button0_wbs_write <= imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_write;
- button0_wbs_cycle <= imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_cycle;
-
- -- connect imx9328_wb16_wrapper00_mwb16_intercon
- -- irq_mngr00_swb16
- imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_readdata <= irq_mngr00_wbs_s1_readdata;
- imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_ack <= irq_mngr00_wbs_s1_ack;
- -- irq_mngr00_candr
- -- led0_swb16
- imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_readdata <= led0_wbs_readdata;
- imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_ack <= led0_wbs_ack;
- -- led0_candr
- -- button0_swb16
- imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_readdata <= button0_wbs_readdata;
- imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_ack <= button0_wbs_ack;
- -- button0_candr
- -- imx9328_wb16_wrapper00_mwb16
- imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_address <= imx9328_wb16_wrapper00_wbm_address;
- imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_writedata <= imx9328_wb16_wrapper00_wbm_writedata;
- imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_strobe <= imx9328_wb16_wrapper00_wbm_strobe;
- imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_write <= imx9328_wb16_wrapper00_wbm_write;
- imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_cycle <= imx9328_wb16_wrapper00_wbm_cycle;
- -- imx9328_wb16_wrapper00_candr
- -- rstgen_syscon00_imx9328_wb16_wrapper00
- imx9328_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_clk <= rstgen_syscon00_gls_clk;
- imx9328_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_reset <= rstgen_syscon00_gls_reset;
-
end architecture top_wishbone_example_1;
+
Deleted: trunk/firmware/wishbone_example/src/wishbone_example.ucf
===================================================================
--- trunk/firmware/wishbone_example/src/wishbone_example.ucf 2009-03-12 16:03:28 UTC (rev 1154)
+++ trunk/firmware/wishbone_example/src/wishbone_example.ucf 2009-03-12 16:25:53 UTC (rev 1155)
@@ -1,76 +0,0 @@
-# Constraint file, automaticaly generated by pod
-NET "imx9328_wb16_wrapper00_imx_data<0>" LOC="P1" | IOSTANDARD=LVCMOS33;# D0
-NET "imx9328_wb16_wrapper00_imx_data<1>" LOC="P2" | IOSTANDARD=LVCMOS33;# D1
-NET "imx9328_wb16_wrapper00_imx_data<2>" LOC="P4" | IOSTANDARD=LVCMOS33;# D2
-NET "imx9328_wb16_wrapper00_imx_data<3>" LOC="P5" | IOSTANDARD=LVCMOS33;# D3
-NET "imx9328_wb16_wrapper00_imx_data<4>" LOC="P6" | IOSTANDARD=LVCMOS33;# D4
-NET "imx9328_wb16_wrapper00_imx_data<5>" LOC="P7" | IOSTANDARD=LVCMOS33;# D5
-NET "imx9328_wb16_wrapper00_imx_data<6>" LOC="P8" | IOSTANDARD=LVCMOS33;# D6
-NET "imx9328_wb16_wrapper00_imx_data<7>" LOC="P10" | IOSTANDARD=LVCMOS33;# D7
-NET "imx9328_wb16_wrapper00_imx_data<8>" LOC="P11" | IOSTANDARD=LVCMOS33;# D8
-NET "imx9328_wb16_wrapper00_imx_data<9>" LOC="P12" | IOSTANDARD=LVCMOS33;# D9
-NET "imx9328_wb16_wrapper00_imx_data<10>" LOC="P13" | IOSTANDARD=LVCMOS33;# D10
-NET "imx9328_wb16_wrapper00_imx_data<11>" LOC="P14" | IOSTANDARD=LVCMOS33;# D11
-NET "imx9328_wb16_wrapper00_imx_data<12>" LOC="P15" | IOSTANDARD=LVCMOS33;# D12
-NET "imx9328_wb16_wrapper00_imx_data<13>" LOC="P17" | IOSTANDARD=LVCMOS33;# D13
-NET "imx9328_wb16_wrapper00_imx_data<14>" LOC="P18" | IOSTANDARD=LVCMOS33;# D14
-NET "imx9328_wb16_wrapper00_imx_data<15>" LOC="P20" | IOSTANDARD=LVCMOS33;# D15
-NET "imx9328_wb16_wrapper00_imx_address<0>" LOC="P23" | IOSTANDARD=LVCMOS33;# A1
-NET "imx9328_wb16_wrapper00_imx_address<1>" LOC="P24" | IOSTANDARD=LVCMOS33;# A2
-NET "imx9328_wb16_wrapper00_imx_address<2>" LOC="P25" | IOSTANDARD=LVCMOS33;# A3
-NET "imx9328_wb16_wrapper00_imx_address<3>" LOC="P26" | IOSTANDARD=LVCMOS33;# A4
-NET "imx9328_wb16_wrapper00_imx_address<4>" LOC="P27" | IOSTANDARD=LVCMOS33;# A5
-NET "imx9328_wb16_wrapper00_imx_address<5>" LOC="P28" | IOSTANDARD=LVCMOS33;# A6
-NET "imx9328_wb16_wrapper00_imx_address<6>" LOC="P30" | IOSTANDARD=LVCMOS33;# A7
-NET "imx9328_wb16_wrapper00_imx_address<7>" LOC="P31" | IOSTANDARD=LVCMOS33;# A8
-NET "imx9328_wb16_wrapper00_imx_address<8>" LOC="P32" | IOSTANDARD=LVCMOS33;# A9
-NET "imx9328_wb16_wrapper00_imx_address<9>" LOC="P33" | IOSTANDARD=LVCMOS33;# A10
-NET "imx9328_wb16_wrapper00_imx_address<10>" LOC="P35" | IOSTANDARD=LVCMOS33;# A11
-NET "imx9328_wb16_wrapper00_imx_address<11>" LOC="P36" | IOSTANDARD=LVCMOS33;# A12
-NET "rstgen_syscon00_ext_clk" LOC="P55" | IOSTANDARD=LVCMOS33;# CLK0
-NET "rstgen_syscon00_ext_clk" TNM_NET = "rstgen_syscon00_ext_clk";
-TIMESPEC "TS_rstgen_syscon00_ext_clk" = PERIOD "rstgen_syscon00_ext_clk" 10.4167 ns HIGH 50 %;
-NET "imx9328_wb16_wrapper00_imx_cs_n" LOC="P59" | IOSTANDARD=LVCMOS33;# CTRL1
-NET "imx9328_wb16_wrapper00_imx_eb3_n" LOC="P60" | IOSTANDARD=LVCMOS33;# CTRL9
-NET "imx9328_wb16_wrapper00_imx_oe_n" LOC="P63" | IOSTANDARD=LVCMOS33;# CTRL10
-NET "irq_mngr00_gls_irq" LOC="P68" | IOSTANDARD=LVCMOS33;# TIM1
-NET "led0_led" LOC="P116" | IOSTANDARD=LVCMOS33;# IO_1
-NET "button0_button" LOC="P141" | IOSTANDARD=LVCMOS33;# IO_L01N_0
-NET "imx9328_wb16_wrapper00_imx_data<0>" LOC="P1" | IOSTANDARD=LVCMOS33;# D0
-NET "imx9328_wb16_wrapper00_imx_data<1>" LOC="P2" | IOSTANDARD=LVCMOS33;# D1
-NET "imx9328_wb16_wrapper00_imx_data<2>" LOC="P4" | IOSTANDARD=LVCMOS33;# D2
-NET "imx9328_wb16_wrapper00_imx_data<3>" LOC="P5" | IOSTANDARD=LVCMOS33;# D3
-NET "imx9328_wb16_wrapper00_imx_data<4>" LOC="P6" | IOSTANDARD=LVCMOS33;# D4
-NET "imx9328_wb16_wrapper00_imx_data<5>" LOC="P7" | IOSTANDARD=LVCMOS33;# D5
-NET "imx9328_wb16_wrapper00_imx_data<6>" LOC="P8" | IOSTANDARD=LVCMOS33;# D6
-NET "imx9328_wb16_wrapper00_imx_data<7>" LOC="P10" | IOSTANDARD=LVCMOS33;# D7
-NET "imx9328_wb16_wrapper00_imx_data<8>" LOC="P11" | IOSTANDARD=LVCMOS33;# D8
-NET "imx9328_wb16_wrapper00_imx_data<9>" LOC="P12" | IOSTANDARD=LVCMOS33;# D9
-NET "imx9328_wb16_wrapper00_imx_data<10>" LOC="P13" | IOSTANDARD=LVCMOS33;# D10
-NET "imx9328_wb16_wrapper00_imx_data<11>" LOC="P14" | IOSTANDARD=LVCMOS33;# D11
-NET "imx9328_wb16_wrapper00_imx_data<12>" LOC="P15" | IOSTANDARD=LVCMOS33;# D12
-NET "imx9328_wb16_wrapper00_imx_data<13>" LOC="P17" | IOSTANDARD=LVCMOS33;# D13
-NET "imx9328_wb16_wrapper00_imx_data<14>" LOC="P18" | IOSTANDARD=LVCMOS33;# D14
-NET "imx9328_wb16_wrapper00_imx_data<15>" LOC="P20" | IOSTANDARD=LVCMOS33;# D15
-NET "imx9328_wb16_wrapper00_imx_address<0>" LOC="P23" | IOSTANDARD=LVCMOS33;# A1
-NET "imx9328_wb16_wrapper00_imx_address<1>" LOC="P24" | IOSTANDARD=LVCMOS33;# A2
-NET "imx9328_wb16_wrapper00_imx_address<2>" LOC="P25" | IOSTANDARD=LVCMOS33;# A3
-NET "imx9328_wb16_wrapper00_imx_address<3>" LOC="P26" | IOSTANDARD=LVCMOS33;# A4
-NET "imx9328_wb16_wrapper00_imx_address<4>" LOC="P27" | IOSTANDARD=LVCMOS33;# A5
-NET "imx9328_wb16_wrapper00_imx_address<5>" LOC="P28" | IOSTANDARD=LVCMOS33;# A6
-NET "imx9328_wb16_wrapper00_imx_address<6>" LOC="P30" | IOSTANDARD=LVCMOS33;# A7
-NET "imx9328_wb16_wrapper00_imx_address<7>" LOC="P31" | IOSTANDARD=LVCMOS33;# A8
-NET "imx9328_wb16_wrapper00_imx_address<8>" LOC="P32" | IOSTANDARD=LVCMOS33;# A9
-NET "imx9328_wb16_wrapper00_imx_address<9>" LOC="P33" | IOSTANDARD=LVCMOS33;# A10
-NET "imx9328_wb16_wrapper00_imx_address<10>" LOC="P35" | IOSTANDARD=LVCMOS33;# A11
-NET "imx9328_wb16_wrapper00_imx_address<11>" LOC="P36" | IOSTANDARD=LVCMOS33;# A12
-NET "rstgen_syscon00_ext_clk" LOC="P55" | IOSTANDARD=LVCMOS33;# CLK0
-NET "rstgen_syscon00_ext_clk" TNM_NET = "rstgen_syscon00_ext_clk";
-TIMESPEC "TS_rstgen_syscon00_ext_clk" = PERIOD "rstgen_syscon00_ext_clk" 10.4167 ns HIGH 50 %;
-NET "imx9328_wb16_wrapper00_imx_cs_n" LOC="P59" | IOSTANDARD=LVCMOS...
[truncated message content] |
