[Armadeus-commitlog] SF.net SVN: armadeus:[1143] trunk/firmware/leds/button_led
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[Armadeus-commitlog] SF.net SVN: armadeus:[1143] trunk/firmware/leds/button_led
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From: <Fa...@us...> - 2009-03-11 14:04:41
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Revision: 1143
http://armadeus.svn.sourceforge.net/armadeus/?rev=1143&view=rev
Author: FabM
Date: 2009-03-11 14:04:26 +0000 (Wed, 11 Mar 2009)
Log Message:
-----------
[FIRMWARE] Make button_led design synchrone, and add a reset
Modified Paths:
--------------
trunk/firmware/leds/button_led/clock_divider.vhd
trunk/firmware/leds/button_led/debouncer.vhd
trunk/firmware/leds/button_led/flip_flop.vhd
trunk/firmware/leds/button_led/led_top.dia
trunk/firmware/leds/button_led/led_top.vhd
Added Paths:
-----------
trunk/firmware/leds/button_led/led_apf9328.ucf
trunk/firmware/leds/button_led/led_top_xc3s200.bit
trunk/firmware/leds/button_led/led_top_xc3s400.bit
trunk/firmware/leds/button_led/reset_gen.vhd
Removed Paths:
-------------
trunk/firmware/leds/button_led/led.ucf
trunk/firmware/leds/button_led/led_top_200k.bit
trunk/firmware/leds/button_led/led_top_400k.bit
Modified: trunk/firmware/leds/button_led/clock_divider.vhd
===================================================================
--- trunk/firmware/leds/button_led/clock_divider.vhd 2009-03-11 14:01:33 UTC (rev 1142)
+++ trunk/firmware/leds/button_led/clock_divider.vhd 2009-03-11 14:04:26 UTC (rev 1143)
@@ -1,26 +1,27 @@
----------------------------------------------------------------------------------
--- Company: Armadeus Project
--- Engineer: Benoit Canet
+-- company: armadeus project
+-- engineer: Benoît Canet
--
--- Create Date: 22:04:02 04/12/2007
--- Design Name:
--- Module Name: clock_divider - behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
+-- create date: 22:04:02 04/12/2007
+-- design name:
+-- module name: clock_divider - behavioral
+-- project name:
+-- target devices:
+-- tool versions:
+-- description:
--
--- Dependencies:
+-- dependencies:
--
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
+-- revision:
+-- revision 0.02 - add a reset (FabM)
+-- revision 0.01 - file created
+-- additional comments:
--
----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
entity clock_divider is
@@ -28,35 +29,34 @@
-- clock division ratio (must be a multiple of 2)
generic(ratio : integer := 2);
- port (clk_in : in STD_LOGIC;
- clk_out : out STD_LOGIC);
+ port (
+ reset : in std_logic ;
+ clk_in : in std_logic;
+ clk_out : out std_logic);
end clock_divider;
architecture behavioral of clock_divider is
- signal state : STD_LOGIC := '0';
+ signal state : std_logic := '0';
begin
- process (clk_in)
-
+ process (clk_in,reset)
variable count : integer range 0 to ratio;
-
begin
-
- if (clk_in'event) and (clk_in = '1') then
-
+ if reset = '1' then
+ count := 0;
+ clk_out <= '0';
+ elsif rising_edge(clk_in) then
-- count the number of clock change
count := count + 1;
-
-- if we waited long enough generate one clock change
if (count = ratio/2) then
state <= not state;
count := 0;
clk_out <= state;
end if;
-
end if;
end process;
Modified: trunk/firmware/leds/button_led/debouncer.vhd
===================================================================
--- trunk/firmware/leds/button_led/debouncer.vhd 2009-03-11 14:01:33 UTC (rev 1142)
+++ trunk/firmware/leds/button_led/debouncer.vhd 2009-03-11 14:04:26 UTC (rev 1143)
@@ -1,61 +1,66 @@
----------------------------------------------------------------------------------
--- Company: Armadeus Project
--- Engineer: Benoit Canet
+-- company: armadeus project
+-- engineer: Benoît Canet
--
--- Create Date: 21:48:05 04/12/2007
--- Design Name:
--- Module Name: debouncer - behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
+-- create date: 21:48:05 04/12/2007
+-- design name:
+-- module name: debouncer - behavioral
+-- project name:
+-- target devices:
+-- tool versions:
+-- description:
--
--- Dependencies:
+-- dependencies:
--
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
--- original code comes from Dennis Smith
--- http://homepage.mac.com/dgsmith1/HANDOUTS/EE452/debounce.vhd.txt
+-- revision:
+-- revision 0.02 - Make it synchrone with reset (FabM)
+-- revision 0.01 - file created
+-- additional comments:
+-- original code comes from dennis smith
+-- http://homepage.mac.com/dgsmith1/handouts/ee452/debounce.vhd.txt
----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
entity debouncer is
- port ( clk_100hz : in STD_LOGIC;
- button_in : in STD_LOGIC;
- button_debounced_out : out STD_LOGIC);
+ port ( clk : in std_logic;
+ reset : in std_logic ;
+ clk_ratio : in std_logic ;
+ button_in : in std_logic;
+ button_debounced_out : out std_logic);
end debouncer;
architecture behavioral of debouncer is
- signal shift_pb : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
- signal state : STD_LOGIC := '1';
+ signal shift_pb : std_logic_vector(3 downto 0) := "0000";
+ signal state : std_logic := '1';
begin
- process(clk_100hz)
+ process(clk,reset)
+ variable clk_ratio_old : std_logic := '0';
begin
- if (clk_100hz'event) and (clk_100hz = '1')
- then
- -- shift the register
- shift_pb(2 DOWNTO 0) <= shift_pb(3 DOWNTO 1);
- -- input the new sample in the register
- shift_pb(3) <= button_in;
- -- change output if needed
- case shift_pb is
- when "0000" =>
- state <= '0';
- when "1111" =>
- state <= '1';
- when others =>
- state <= state;
+ if reset = '1' then
+ state <= '0';
+ clk_ratio_old := '0';
+ elsif rising_edge(clk) then
+ if clk_ratio = '0' and clk_ratio /= clk_ratio_old then
+ -- shift the register
+ shift_pb(2 downto 0) <= shift_pb(3 downto 1);
+ -- input the new sample in the register
+ shift_pb(3) <= button_in;
+ -- change output if needed
+ case shift_pb is
+ when "0000" => state <= '0';
+ when "1111" => state <= '1';
+ when others => state <= state;
end case;
+ end if;
+ clk_ratio_old := clk_ratio;
end if;
-
end process;
button_debounced_out <= state;
Modified: trunk/firmware/leds/button_led/flip_flop.vhd
===================================================================
--- trunk/firmware/leds/button_led/flip_flop.vhd 2009-03-11 14:01:33 UTC (rev 1142)
+++ trunk/firmware/leds/button_led/flip_flop.vhd 2009-03-11 14:04:26 UTC (rev 1143)
@@ -1,32 +1,34 @@
----------------------------------------------------------------------------------
--- Company: Armadeus Project
--- Engineer: Benoit Canet
+-- company: armadeus project
+-- engineer: Benoît Canet
--
--- Create Date: 21:21:27 04/12/2007
--- Design Name:
--- Module Name: flip_flop - Behavioral
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
+-- create date: 21:21:27 04/12/2007
+-- design name:
+-- module name: flip_flop - behavioral
+-- project name:
+-- target devices:
+-- tool versions:
+-- description:
--
--- Dependencies:
+-- dependencies:
--
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
+-- revision:
+-- revision 0.02 - Synchronize with high speed clock (FabM)
+-- revision 0.01 - file created
+-- additional comments:
--
----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
-
entity flip_flop is
- port (clk_100hz : in STD_LOGIC;
- switch_in_n : in STD_LOGIC;
- led_out : out STD_LOGIC);
+ port (
+ clk : in std_logic;
+ reset : in std_logic ;
+ switch_in_n : in std_logic;
+ led_out : out std_logic
+ );
end flip_flop;
@@ -34,11 +36,15 @@
begin
- process(clk_100hz)
- variable state : STD_LOGIC := '0';
- variable latch : STD_LOGIC := '0';
+ led_output : process(clk,reset)
+ variable state : std_logic := '0';
+ variable latch : std_logic := '0';
begin
- if clk_100hz'event and (clk_100hz = '1') then
+ if reset = '1' then
+ led_out <= '0';
+ latch := '0';
+ state := '0';
+ elsif rising_edge(clk) then
-- switch_in_n is active when down
--( the switch is connected via a pullup)
if (switch_in_n = '0') and (latch /= switch_in_n) then
@@ -46,7 +52,6 @@
end if;
latch := switch_in_n;
led_out <= state;
-
end if;
end process;
Deleted: trunk/firmware/leds/button_led/led.ucf
===================================================================
--- trunk/firmware/leds/button_led/led.ucf 2009-03-11 14:01:33 UTC (rev 1142)
+++ trunk/firmware/leds/button_led/led.ucf 2009-03-11 14:04:26 UTC (rev 1143)
@@ -1,4 +0,0 @@
-# pinout
-NET "button" LOC = "P141" | IOSTANDARD = LVCMOS33 ;
-NET "clk" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
-NET "led" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
Copied: trunk/firmware/leds/button_led/led_apf9328.ucf (from rev 1116, trunk/firmware/leds/button_led/led.ucf)
===================================================================
--- trunk/firmware/leds/button_led/led_apf9328.ucf (rev 0)
+++ trunk/firmware/leds/button_led/led_apf9328.ucf 2009-03-11 14:04:26 UTC (rev 1143)
@@ -0,0 +1,4 @@
+# pinout
+NET "button" LOC = "P141" | IOSTANDARD = LVCMOS33 ;
+NET "clk" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
+NET "led" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
Modified: trunk/firmware/leds/button_led/led_top.dia
===================================================================
(Binary files differ)
Modified: trunk/firmware/leds/button_led/led_top.vhd
===================================================================
--- trunk/firmware/leds/button_led/led_top.vhd 2009-03-11 14:01:33 UTC (rev 1142)
+++ trunk/firmware/leds/button_led/led_top.vhd 2009-03-11 14:04:26 UTC (rev 1143)
@@ -1,83 +1,114 @@
----------------------------------------------------------------------------------
--- Company: Armadeus Project
--- Engineer: Benoit Canet
+-- company: armadeus project
+-- engineer: Benoît Canet
--
--- Create Date: 22:37:46 04/12/2007
--- Design Name:
--- Module Name: led_top - structural
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
+-- create date: 22:37:46 04/12/2007
+-- design name:
+-- module name: led_top - structural
+-- project name:
+-- target devices:
+-- tool versions:
+-- description:
--
--- Dependencies:
+-- dependencies:
--
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
+-- revision:
+-- revision 0.02 - Make it synchrone with reset (FabM)
+-- revision 0.01 - file created
+-- additional comments:
--
----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
entity led_top is
port (
- clk : in STD_LOGIC;
- button : in STD_LOGIC;
- led : out STD_LOGIC);
+ clk : in std_logic;
+ button : in std_logic;
+ led : out std_logic);
end led_top;
architecture structural of led_top is
- -- We declare the component we we'll use
+ -- we declare the component we we'll use
component clock_divider
generic (ratio: integer);
- port (clk_in : in STD_LOGIC;
- clk_out : out STD_LOGIC);
+ port (reset : in std_logic ;
+ clk_in : in std_logic;
+ clk_out : out std_logic);
end component;
-
- component debouncer
- port (clk_100hz : in STD_LOGIC;
- button_in : in STD_LOGIC;
- button_debounced_out : out STD_LOGIC);
- end component;
- component flip_flop
- port (clk_100hz : in STD_LOGIC;
- switch_in_n : in STD_LOGIC;
- led_out : out STD_LOGIC);
- end component;
+ component debouncer
+ port (clk : in std_logic ;
+ reset : in std_logic ;
+ clk_ratio : in std_logic;
+ button_in : in std_logic;
+ button_debounced_out : out std_logic);
+ end component;
+ component flip_flop
+ port (
+ clk : in std_logic;
+ reset : in std_logic ;
+ switch_in_n : in std_logic;
+ led_out : out std_logic
+ );
+ end component;
+
+ component reset_gen
+ generic (
+ invert_reset : std_logic := '0' -- 0 : not invert, 1 invert
+ );
+ port (
+ -- external signals
+ clk : in std_logic ;
+ --internal signals
+ reset : out std_logic
+ );
+ end component reset_gen;
+
-- internal signals
- signal clk_100hz : STD_LOGIC;
- signal button_debounced_n : STD_LOGIC;
-
- begin
-
- -- instantiate and connect the clock divider
- -- here we use a 96MHz/100Hz=960000 ratio
- i_clock_divider_identifier : clock_divider
- generic map(ratio => 960000)
- -- for simulation purpose use the following line
+ signal clk_ratio : std_logic;
+ signal reset : std_logic;
+ signal button_debounced_n : std_logic;
+
+begin
+
+ -- instantiate and connect the clock divider
+ -- here we use a 96mhz/100hz=960000 ratio
+ i_clock_divider_identifier : clock_divider
+ generic map(ratio => 960000)
+ -- for simulation purpose use the following line
-- instead of the previous
-- generic map(ratio => 2)
-
- port map (clk_in => clk,
- clk_out => clk_100hz);
- --instantiate and connect the debouncer
- i_debouncer_identifier : debouncer
- port map (button_in => button,
- clk_100hz => clk_100hz,
- button_debounced_out => button_debounced_n);
+ port map (reset => reset,
+ clk_in => clk,
+ clk_out => clk_ratio);
- --instantiate and connect the flip flop
- i_flip_flop_identifier : flip_flop
- port map (clk_100hz => clk_100hz,
- switch_in_n => button_debounced_n,
- led_out => led);
+ --instantiate and connect the debouncer
+ i_debouncer_identifier : debouncer
+ port map ( clk => clk,
+ reset => reset,
+ clk_ratio => clk_ratio,
+ button_in => button,
+ button_debounced_out => button_debounced_n);
+ --instantiate and connect the flip flop
+ i_flip_flop_identifier : flip_flop
+ port map (clk => clk,
+ reset => reset,
+ switch_in_n => button_debounced_n,
+ led_out => led);
+
+ i_reset_gen : reset_gen
+ generic map (invert_reset => '0')
+ port map (
+ clk => clk,
+ reset => reset
+ );
+
end structural;
Deleted: trunk/firmware/leds/button_led/led_top_200k.bit
===================================================================
(Binary files differ)
Deleted: trunk/firmware/leds/button_led/led_top_400k.bit
===================================================================
(Binary files differ)
Copied: trunk/firmware/leds/button_led/led_top_xc3s200.bit (from rev 1116, trunk/firmware/leds/button_led/led_top_200k.bit)
===================================================================
(Binary files differ)
Copied: trunk/firmware/leds/button_led/led_top_xc3s400.bit (from rev 1116, trunk/firmware/leds/button_led/led_top_400k.bit)
===================================================================
(Binary files differ)
Added: trunk/firmware/leds/button_led/reset_gen.vhd
===================================================================
--- trunk/firmware/leds/button_led/reset_gen.vhd (rev 0)
+++ trunk/firmware/leds/button_led/reset_gen.vhd 2009-03-11 14:04:26 UTC (rev 1143)
@@ -0,0 +1,56 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 05/03/2008
+-- File : reset_gen.vhd
+--
+-- Abstract :
+--
+---------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity reset_gen is
+---------------------------------------------------------------------------
+generic(
+ invert_reset : std_logic := '0' -- 0 : not invert, 1 invert
+);
+port
+(
+ -- external signals
+ clk : in std_logic ;
+ --internal signals
+ reset : out std_logic
+);
+end entity;
+
+
+---------------------------------------------------------------------------
+Architecture reset_gen_1 of reset_gen is
+---------------------------------------------------------------------------
+
+ signal dly: std_logic := '0';
+ signal rst: std_logic := '0';
+ signal reset_tmp : std_logic;
+
+begin
+
+ reset_tmp <= '0';
+ ----------------------------------------------------------------------------
+ -- RESET signal generator.
+ ----------------------------------------------------------------------------
+ process(clk)
+ begin
+ if(rising_edge(clk)) then
+ dly <= ( not(reset_tmp) and dly and not(rst) )
+ or ( not(reset_tmp) and not(dly) and rst );
+ rst <= ( not(reset_tmp) and not(dly) and not(rst) );
+ end if;
+ end process;
+ reset <= rst xor invert_reset ;
+
+end architecture reset_gen_1;
+
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