[Armadeus-commitlog] SF.net SVN: armadeus:[1126] trunk/target/linux/modules/fpga/dev_tools/ fpga_de
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[Armadeus-commitlog] SF.net SVN: armadeus:[1126] trunk/target/linux/modules/fpga/dev_tools/ fpga_devtools
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From: <ar...@us...> - 2009-03-08 15:45:51
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Revision: 1126
http://armadeus.svn.sourceforge.net/armadeus/?rev=1126&view=rev
Author: artemys
Date: 2009-03-08 15:45:46 +0000 (Sun, 08 Mar 2009)
Log Message:
-----------
[LINUX] fpgaloader driver cleanup (pass2)
Modified Paths:
--------------
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/apf27-fpga-loader.c
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.c
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.c
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.h
Removed Paths:
-------------
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.h
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/apf27-fpga-loader.c
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/apf27-fpga-loader.c 2009-03-08 15:40:50 UTC (rev 1125)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/apf27-fpga-loader.c 2009-03-08 15:45:46 UTC (rev 1126)
@@ -65,9 +65,9 @@
mxc_gpio_mode(CFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
gpio_set_value(CFG_FPGA_PWR, 0);
- fpga_addr = ioremap( FPGA_BASE_ADDR, 16);
- if( fpga_addr == NULL )
- return 0;
+ fpga_addr = ioremap( FPGA_BASE_ADDR, 16);
+ if( fpga_addr == NULL )
+ return 0;
return 1;
}
@@ -140,7 +140,7 @@
mxc_gpio_mode (CFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
mxc_gpio_mode (CFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
gpio_set_value(CFG_FPGA_PRG, 1);
- iounmap(fpga_addr);
+ iounmap(fpga_addr);
return 1;
}
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.c
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.c 2009-03-08 15:40:50 UTC (rev 1125)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.c 2009-03-08 15:45:46 UTC (rev 1126)
@@ -30,12 +30,14 @@
#include <linux/miscdevice.h>
#include <asm/uaccess.h>
-#include "fpga-loader.h"
#include "xilinx-fpga-loader.h"
#define DRIVER_VERSION "0.9"
#define DRIVER_NAME "fpgaloader"
+#define FPGA_PROC_DIRNAME "driver/fpga"
+#define FPGA_PROC_FILENAME FPGA_PROC_DIRNAME "/loader"
+#define FPGA_IOCTL 0x10000000 /* !! TO BE BETTER DEFINED !! */
/* global variables */
struct fpga_desc *g_current_desc = NULL;
@@ -69,7 +71,7 @@
goto out;
}
- ret = xilinx_load( g_current_desc, g_buffer, count );
+ ret = fpga_load( g_current_desc, g_buffer, count );
out:
/* Release exclusive access */
@@ -90,7 +92,7 @@
if( g_nb_users > 0 )
return -EBUSY;
- ret = xilinx_init_load( g_current_desc );
+ ret = fpga_init_load( g_current_desc );
if(!ret) {
printk("Starting FPGA download\n");
g_nb_users++;
@@ -106,7 +108,7 @@
static int armadeus_fpga_release(struct inode *inode, struct file *file)
{
- if( xilinx_finish_load(g_current_desc) )
+ if( fpga_finish_load(g_current_desc) )
printk("Failed to load FPGA !\n");
pr_debug("Closing access to /dev/fpga/loader%d\n", MINOR(inode->i_rdev));
@@ -170,10 +172,10 @@
/* Extract and test minor */
minor = MINOR(inode->i_rdev);
- if( minor > FPGA_MAX_MINOR ) {
+/* if( minor > FPGA_MAX_MINOR ) {
printk("Minor outside range: %d !\n", minor);
return -EFAULT;
- }
+ }*/
switch(cmd)
{
Deleted: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.h
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.h 2009-03-08 15:40:50 UTC (rev 1125)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.h 2009-03-08 15:45:46 UTC (rev 1126)
@@ -1,37 +0,0 @@
-/*
- ***********************************************************************
- *
- * (c) Copyright 2006 Armadeus project
- * Julien Boibessot <jul...@ar...>
- * Nicolas Colombain <nic...@ar...>
- * Generic Xilinx FPGA loader
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- **********************************************************************
- */
-
-#ifndef __FPGA_LOADER_H__
-#define __FPGA_LOADER_H__
-
-#define FPGA_PROC_DIRNAME "driver/fpga"
-#define FPGA_PROC_FILENAME FPGA_PROC_DIRNAME "/loader"
-
-// By default, we use dynamic allocation of major numbers
-#define FPGA_MAJOR 0
-#define FPGA_MAX_MINOR 254
-
-#define FPGA_IOCTL 0x10000000 // !! TO BE BETTER DEFINED !!
-
-#endif // __FPGA_LOADER_H__
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.c
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.c 2009-03-08 15:40:50 UTC (rev 1125)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.c 2009-03-08 15:45:46 UTC (rev 1126)
@@ -34,27 +34,25 @@
#include "xilinx-fpga-loader.h"
+
#define CONFIG_FPGA_DELAY()
-#define CFG_FPGA_WAIT 20000 // uS
+#define CFG_FPGA_WAIT 20000 /* uS */
-size_t bytecount = 0; // total bytes received
+size_t bytecount = 0; /* total bytes received */
-/*
- * Timeout function
- */
+
+/* Timeout function */
static unsigned long get_timer(unsigned long initTime)
{
- struct timeval tv;
- do_gettimeofday(&tv);
- if( tv.tv_usec > initTime ) // avoid overflow pb
- return tv.tv_usec - initTime;
- else
- return initTime - tv.tv_usec;
+ struct timeval tv;
+ do_gettimeofday(&tv);
+ if( tv.tv_usec > initTime ) /* avoid overflow pb */
+ return tv.tv_usec - initTime;
+ else
+ return initTime - tv.tv_usec;
}
-/*
- * dump the given descriptor infos
- */
+/* dump the given descriptor infos */
static int xilinx_dump_descriptor_info( struct fpga_desc *desc, char* buffer )
{
int len;
@@ -66,9 +64,9 @@
}
/**
- * program the FPGA (serial mode).
+ * program the FPGA (serial mode).
* return 0 if success, >0 while programming, <0 if error detected
- */
+ */
static size_t spartan_serial_load (struct fpga_desc *desc, const char* buf, size_t bsize)
{
Xilinx_Spartan_Slave_Serial_fns *fn = desc->iface_fns;
@@ -119,7 +117,7 @@
{
Xilinx_Spartan_Slave_Serial_fns *fn = desc->iface_fns;
if (fn) {
- unsigned long ts; /* timestamp */
+ unsigned long timestamp;
if(*fn->pre){
(*fn->pre)(); //Run the pre configuration function if there is one.
@@ -129,27 +127,27 @@
(*fn->pgm)(1); /* Assert the program, commit */
/* Wait for INIT state (init low) */
- ts = get_timer(0); /* get current time */
+ timestamp = get_timer(0); /* get current time */
do {
- CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
- PRINTF ("** Timeout waiting for INIT to start.\n");
- return -ETIMEDOUT;
- }
+ CONFIG_FPGA_DELAY ();
+ if (get_timer(timestamp) > CFG_FPGA_WAIT) {
+ pr_debug("** Timeout waiting for INIT to start.\n");
+ return -ETIMEDOUT;
+ }
} while (!(*fn->init)());
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
(*fn->pgm)(0); /* Deassert the program, commit */
- ts = get_timer(0); /* get current time */
+ timestamp = get_timer(0); /* get current time */
/* Now wait for INIT to go high */
do {
- CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
- PRINTF ("** Timeout waiting for INIT to clear.\n");
+ CONFIG_FPGA_DELAY ();
+ if (get_timer(timestamp) > CFG_FPGA_WAIT) {
+ pr_debug("** Timeout waiting for INIT to clear.\n");
return -ETIMEDOUT;
- }
+ }
} while ((*fn->init)());
bytecount = 0; /* reset byte count */
@@ -182,7 +180,7 @@
return -ETIMEDOUT;
}
}
- }
+ }
return 0;
}
@@ -194,8 +192,9 @@
static int spartan_parallel_init (struct fpga_desc *desc)
{
Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+
if (fn) {
- unsigned long ts; /* timestamp */
+ unsigned long timestamp;
/*
* Run the pre configuration function if there is one.
*/
@@ -206,12 +205,12 @@
/* Establish the initial state */
(*fn->pgm) (1); /* Assert the program, commit */
- ts = get_timer (0); /* get current time */
+ timestamp = get_timer(0); /* get current time */
/* Now wait for INIT to go down */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
- PRINTF ("** Timeout waiting for INIT to set.\n");
+ if (get_timer(timestamp) > CFG_FPGA_WAIT) {
+ pr_debug("** Timeout waiting for INIT to set.\n");
(*fn->abort) (); /* abort the burn */
return -ETIMEDOUT;
}
@@ -222,12 +221,12 @@
CONFIG_FPGA_DELAY ();
(*fn->pgm) (0); /* Deassert the program, commit */
- ts = get_timer (0); /* get current time */
+ timestamp = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
do {
CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
- PRINTF ("** Timeout waiting for INIT to clear.\n");
+ if (get_timer(timestamp) > CFG_FPGA_WAIT) {
+ pr_debug("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (); /* abort the burn */
return -ETIMEDOUT;
}
@@ -235,15 +234,15 @@
(*fn->wr) (1); /* Assert write, commit */
(*fn->cs) (1); /* Assert chip select, commit */
(*fn->clk) (1); /* Assert the clock pin */
- bytecount = 0; // reset byte count
- }
- return 0;
+ bytecount = 0; // reset byte count
+ }
+ return 0;
}
/**
- * program the FPGA (parallel mode).
+ * program the FPGA (parallel mode).
* return 0 if success, >0 while programming, <0 if error detected
- */
+ */
static size_t spartan_parallel_load (struct fpga_desc *desc, const char* buf, size_t bsize)
{
unsigned long flags;
@@ -251,20 +250,19 @@
if (fn) {
/* Load the data */
- size_t nbbyte = 0; // init local counter
+ size_t nbbyte = 0;
- raw_local_irq_save(flags);
+ raw_local_irq_save(flags);
+ while (nbbyte < bsize) {
+ (*fn->clk) (1); /* Assert the clock pin */
+ CONFIG_FPGA_DELAY ();
+ (*fn->wdata) (buf[nbbyte++]); /* write the data */
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk) (0); /* Deassert the clock pin */
+ bytecount++;
+ }
+ raw_local_irq_restore(flags);
- while (nbbyte < bsize) {
- (*fn->clk) (1); /* Assert the clock pin */
- CONFIG_FPGA_DELAY ();
- (*fn->wdata) (buf[nbbyte++]); /* write the data */
- CONFIG_FPGA_DELAY ();
- (*fn->clk) (0); /* Deassert the clock pin */
- bytecount++;
- }
- raw_local_irq_restore(flags);
-
return bsize;
}
return -EINVAL;
@@ -305,69 +303,68 @@
return 0;
}
-/**
- * program the FPGA.
- * return 0 if success, >0 while programming, <0 if error detected
- */
-size_t xilinx_load( struct fpga_desc *desc, const char *buf, size_t bsize )
+
+size_t fpga_load( struct fpga_desc *desc, const char *buf, size_t bsize )
{
- int ret = 0;
+ int ret = 0;
- if( desc ) {
- switch( desc->family ) /* check family */
- {
- case Xilinx_Spartan:
- {
- switch( desc->iface ) /* check donwload hardware interface */
- {
- case slave_serial: ret = spartan_serial_load( desc, buf, bsize ); break;
- case slave_parallel: ret = spartan_parallel_load (desc, buf, bsize); break;
- default: PRINTF("interface not supported!\n"); ret = -ENOSYS; break;
- }
- }
- break;
- default: PRINTF("family not supported!\n"); ret = -ENOSYS; break;
- }
- }
- else {
- PRINTF("invalid FPGA descriptor!\n");
- ret = -EINVAL;
- }
- return ret;
+ if( desc ) {
+ switch( desc->family ) /* check family */
+ {
+ case Xilinx_Spartan:
+ {
+ switch( desc->iface ) /* check download hardware interface */
+ {
+ case slave_serial: ret = spartan_serial_load( desc, buf, bsize ); break;
+ case slave_parallel: ret = spartan_parallel_load (desc, buf, bsize); break;
+ default: PRINTF("interface not supported!\n"); ret = -ENOSYS; break;
+ }
+ }
+ break;
+ default:
+ PRINTF("family not supported!\n");
+ ret = -ENOSYS;
+ break;
+ }
+ }
+ else {
+ PRINTF("invalid FPGA descriptor!\n");
+ ret = -EINVAL;
+ }
+ return ret;
}
-/**
- * initialize the FPGA programming interface.
- * return 0 if success, <0 if error detected
- */
-int xilinx_init_load( struct fpga_desc *desc )
+int fpga_init_load( struct fpga_desc *desc )
{
- int ret = 0;
+ int ret = 0;
- if( desc ) {
- switch( desc->family ) // check family
- {
- case Xilinx_Spartan:
- {
- switch( desc->iface ) // check donwload hardware interface
- {
- case slave_serial: ret = spartan_serial_init( desc ); break;
- case slave_parallel: ret = spartan_parallel_init( desc ); break;
- default: PRINTF("interface not supported!\n"); ret = -ENOSYS; break;
- }
- }
- break;
- default: PRINTF("family not supported!\n"); ret = -ENOSYS; break;
- }
- }
- else {
- PRINTF("invalid FPGA descriptor!\n");
- ret = -EINVAL;
- }
- return ret;
+ if( desc ) {
+ switch( desc->family )
+ {
+ case Xilinx_Spartan:
+ {
+ switch( desc->iface ) /* check donwload hardware interface */
+ {
+ case slave_serial: ret = spartan_serial_init( desc ); break;
+ case slave_parallel: ret = spartan_parallel_init( desc ); break;
+ default: pr_debug("interface not supported!\n"); ret = -ENOSYS; break;
+ }
+ }
+ break;
+ default:
+ pr_debug("family not supported!\n");
+ ret = -ENOSYS;
+ break;
+ }
+ }
+ else {
+ pr_debug("invalid FPGA descriptor!\n");
+ ret = -EINVAL;
+ }
+ return ret;
}
-int xilinx_finish_load( struct fpga_desc *desc )
+int fpga_finish_load( struct fpga_desc *desc )
{
int ret = 0;
@@ -385,28 +382,25 @@
ret = spartan_parallel_finish( desc );
break;
default:
- PRINTF("interface not supported!\n");
+ pr_debug("interface not supported!\n");
ret = -ENOSYS;
break;
}
}
break;
default:
- PRINTF("family not supported!\n");
+ pr_debug("family not supported!\n");
ret = -ENOSYS;
break;
}
} else {
- PRINTF("invalid FPGA descriptor!\n");
+ pr_debug("invalid FPGA descriptor!\n");
ret = -EINVAL;
}
return ret;
}
-/**
- * get some infos about FPGA download
- */
int fpga_get_infos( struct fpga_desc *desc, char* buffer )
{
int len = 0;
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.h
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.h 2009-03-08 15:40:50 UTC (rev 1125)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.h 2009-03-08 15:45:46 UTC (rev 1126)
@@ -117,19 +117,19 @@
* program the FPGA.
* return 0 if success, >0 while programming, <0 if error detected
*/
-size_t xilinx_load( struct fpga_desc *desc, const char *buf, size_t bsize );
+size_t fpga_load( struct fpga_desc *desc, const char *buf, size_t bsize );
/**
* initialize the FPGA programming interface
* return 0 if success, <0 if error detected
*/
-int xilinx_init_load( struct fpga_desc *desc );
+int fpga_init_load( struct fpga_desc *desc );
/* terminate FGPA loading */
-int xilinx_finish_load( struct fpga_desc *desc );
+int fpga_finish_load( struct fpga_desc *desc );
/**
- * get the descriptor infos, return the number of char placed in the buffer
+ * get some infos about FPGA download, return the number of char placed in the buffer
*/
int fpga_get_infos( struct fpga_desc *desc, char* buffer);
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