[Armadeus-commitlog] SF.net SVN: armadeus:[1108] trunk/firmware/wishbone_example
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[Armadeus-commitlog] SF.net SVN: armadeus:[1108] trunk/firmware/wishbone_example
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From: <Fa...@us...> - 2009-03-03 16:03:32
|
Revision: 1108
http://armadeus.svn.sourceforge.net/armadeus/?rev=1108&view=rev
Author: FabM
Date: 2009-03-03 16:03:26 +0000 (Tue, 03 Mar 2009)
Log Message:
-----------
[FIRMWARE] Updating wishbone_example to be compatible with linux drivers in target/linux/module/fpga/wishbone_example/ directory
Modified Paths:
--------------
trunk/firmware/wishbone_example/Makefile
trunk/firmware/wishbone_example/README
Added Paths:
-----------
trunk/firmware/wishbone_example/src/button.vhd
trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd
trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd
trunk/firmware/wishbone_example/src/irq_mngr.vhd
trunk/firmware/wishbone_example/src/led.vhd
trunk/firmware/wishbone_example/src/rstgen_syscon.vhd
trunk/firmware/wishbone_example/src/top_wishbone_example.vhd
trunk/firmware/wishbone_example/src/wishbone_example.ucf
trunk/firmware/wishbone_example/testbench/apf_test_pkg.vhd
trunk/firmware/wishbone_example/testbench/top_wishbone_example_tb.vhd
Removed Paths:
-------------
trunk/firmware/wishbone_example/src/intercon.vhd
trunk/firmware/wishbone_example/src/wb_button.vhd
trunk/firmware/wishbone_example/src/wb_led.ucf
trunk/firmware/wishbone_example/src/wb_led.vhd
trunk/firmware/wishbone_example/src/wb_top.vhd
trunk/firmware/wishbone_example/src/wishbone/
trunk/firmware/wishbone_example/testbench/wb_top_tb.vhd
Modified: trunk/firmware/wishbone_example/Makefile
===================================================================
--- trunk/firmware/wishbone_example/Makefile 2009-03-03 10:22:12 UTC (rev 1107)
+++ trunk/firmware/wishbone_example/Makefile 2009-03-03 16:03:26 UTC (rev 1108)
@@ -1,237 +1,98 @@
-# Makefile for VHDL synthesis and simulation
-# version 1.0
+# Makefile for ghdl simulation
+# version 1.2
# Fabien Marteau
# project name
-PROJECT=Wb_top
+PROJECT=top_wishbone_example
+
# vhdl files
-FILES = src/Wb_top.vhd src/Wb_button.vhd src/intercon.vhd src/wishbone/imx_wrapper.vhd src/wishbone/irq_mngr.vhd src/Wb_led.vhd src/wishbone/syscon.vhd
-# pin configuration
-UCF_FILE = src/Wb_led.ucf
-# Synthesis constraints file
-XCF_FILE =
+TESTBENCH_FILE=testbench/$(PROJECT)_tb.vhd
+LIBRARY_FILE=testbench/apf_test_pkg.vhd
+SYNTHESIS_FILE=$(PROJECT)_synthesis.vhd
+PLACE_AND_ROUTE_FILE=$(PROJECT)_timesim.vhd
+FILES=src/top_wishbone_example.vhd \
+ src/imx9328_wb16_wrapper.vhd \
+ src/rstgen_syscon.vhd \
+ src/irq_mngr.vhd \
+ src/led.vhd \
+ src/button.vhd \
+ src/imx9328_wb16_wrapper00_mwb16_intercon.vhd \
+ testbench/apf_test_pkg.vhd
+
# testbench
-SIMTOP = wb_top_tb
-SIMFILES = ../apf_pkg/apf_test_pkg.vhd testbench/Wb_top_tb.vhd
+SIMTOP =$(PROJECT)_tb
# Simu break condition
GHDL_SIM_OPT = --assert-level=error
#GHDL_SIM_OPT = --stop-time=500ns
-# FPGA options
-PART = xc3s200-4-tq144
-
-############################
-# Personnals options
-############################
-
-CAT=../Xtools/catcolor
-BRIEF=../Xtools/brief.py
-
-
-############################
-# Xilinx options
-############################
-BIN = bin
-WORK = work
-
-SYNTH = xst
-NGDBUILD = ngdbuild
-MAP = map
-PAR = par
-TRACE = trce
-BITGEN = bitgen
-
-ifdef $(XCF_FILE)
-XCF = -uc $(XCF_FILE)\n
-endif
-
##############################
# GHDL options
##############################
SIMDIR = simu
-SYNTHFILES = bin/bus_led_ise/netgen/synthesis
-GHDL_CMD = ghdl
-GHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic
-#GHDL_FLAGS = --ieee=synopsys -P~/Xilinx92i/coregen/ip/xilinx/primary/com/xilinx/ip/unisim --warn-no-vital-generic
+GHDL_CMD =ghdl
+GHDL_SIMU_FLAGS = --ieee=synopsys --warn-no-vital-generic
+GHDL_SYNTHESIS_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic
+GHDL_PANDR_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/simprim --warn-no-vital-generic
VIEW_CMD = /usr/bin/gtkwave
OBJS_FILES = $(patsubst %.vhd, %.o, $(notdir $(FILES)) )
OBJS_SIMFILES = $(patsubst %.vhd, %.o, $(notdir $(SIMFILES)) )
-#################################
-# Synthesis with xst
-#################################
-
-messages : bit
- $(BRIEF) $(BIN)/$(PROJECT)
- @echo bitstream : $(PROJECT).bit
-
-
-bit : $(BIN)/$(PROJECT).ncd trace
- -$(BITGEN) -intstyle xflow -w \
- -g DebugBitstream:No \
- -g Binary:yes \
- -g CRC:Enable \
- -g ConfigRate:6 \
- -g CclkPin:PullUp \
- -g M0Pin:PullUp \
- -g M1Pin:PullUp \
- -g M2Pin:PullUp \
- -g ProgPin:PullUp \
- -g DonePin:PullUp \
- -g TckPin:PullUp \
- -g TdiPin:PullUp \
- -g TdoPin:PullUp \
- -g TmsPin:PullUp \
- -g UnusedPin:PullDown \
- -g UserID:0xFFFFFFFF \
- -g DCMShutdown:Disable \
- -g DCIUpdateMode:AsRequired \
- -g StartUpClk:CClk \
- -g DONE_cycle:4 \
- -g GTS_cycle:5 \
- -g GWE_cycle:6 \
- -g LCK_cycle:NoWait \
- -g Match_cycle:Auto \
- -g Security:None \
- -g DonePipe:No \
- -g DriveDone:No \
- $(BIN)/$(PROJECT).ncd > $(BIN)/$(PROJECT).bitlog
- $(CAT) $(BIN)/$(PROJECT).bitlog
- -cp $(BIN)/$(PROJECT).bit /tftpboot/
- -cp $(BIN)/$(PROJECT).bin /tftpboot/
-
-trace: $(BIN)/$(PROJECT).ncd $(BIN)/$(PROJECT).pcf
- -$(TRACE) -intstyle xflow -e 3 -l 3 -s 4 -xml $(BIN)/$(PROJECT) $(BIN)/$(PROJECT).ncd -o $(BIN)/$(PROJECT).twr $(BIN)/$(PROJECT).pcf
- $(CAT) $(BIN)/$(PROJECT).tracelog
-
-$(BIN)/$(PROJECT).ncd : par
-
-par : $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).pcf
- - sh -c 'pid=$$$$; $(PAR) -w -intstyle xflow -ol std -t 1 $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).ncd $(BIN)/$(PROJECT).pcf | (sed "/^PAR done/q";kill $$pid)' > $(BIN)/$(PROJECT).parlog
- $(CAT) $(BIN)/$(PROJECT).parlog
- - killall -9 par
-
-$(BIN)/$(PROJECT).pcf $(BIN)/$(PROJECT)_map.ncd : map
-
-map : $(BIN)/$(PROJECT).ngd
- - sh -c 'pid=$$$$ ; $(MAP) -intstyle xflow -p $(PART) -cm area -pr b -k 4 -c 100 -o $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).ngd $(BIN)/$(PROJECT).pcf | (sed "/^See MAP report file/q" ; kill $$pid ) ' > $(BIN)/$(PROJECT).maplog
- $(CAT) $(BIN)/$(PROJECT).maplog
- - killall -9 map
-
-$(BIN)/$(PROJECT).ngd : ngdbuild
-
-ngdbuild : $(BIN)/$(PROJECT).ngr $(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).lso
- -$(NGDBUILD) -intstyle xflow -dd _ngo -nt timestamp -p $(PART) $(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).ngd -uc $(UCF_FILE) > $(BIN)/$(PROJECT).ngdlog
- $(CAT) $(BIN)/$(PROJECT).ngdlog
-
-$(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).ngr $(BIN)/$(PROJECT).lso : synthesis
-
-synthesis : $(BIN)/$(PROJECT).prj $(BIN)/$(PROJECT).xst
- $(SYNTH) -ifn $(BIN)/$(PROJECT).xst -ofn $(BIN)/$(PROJECT).log \
- | sed "s/^ERROR/[01\;31mERROR[00m/"\
- | sed "s/^WARNING/[01\;33mWARNING[00m/"\
- | sed "s/^INFO/[01\;32mINFO[0m/"
-
-$(BIN)/$(PROJECT).xst $(BIN)/$(PROJECT).prj :
- @mkdir -p $(BIN)
- @touch $(BIN)/$(PROJECT);
- @for f in $(FILES); do \
- echo vhdl $(WORK) \"$$f\" >> $(BIN)/$(PROJECT).prj;\
- done
- @echo work > $(BIN)/$(PROJECT).lso
- @mkdir -p ./bin/xst/projnav.tmp
- @echo " \
- set -tmpdir "./bin/xst/projnav.tmp" \n\
- set -xsthdpdir "./bin/xst" \n\
- run \n\
- -ifn $(BIN)/$(PROJECT).prj \n\
- -ifmt mixed \n\
- -ofn $(BIN)/$(PROJECT) \n\
- -ofmt NGC \n\
- -p $(PART) \n\
- -top $(PROJECT) \n\
- -opt_mode Speed \n\
- -opt_level 1 \n\
- $(XCF)\
- -iuc NO \n\
- -lso $(BIN)/$(PROJECT).lso \n\
- -keep_hierarchy NO \n\
- -rtlview Yes \n\
- -glob_opt AllClockNets \n\
- -read_cores YES \n\
- -write_timing_constraints NO \n\
- -cross_clock_analysis NO \n\
- -hierarchy_separator / \n\
- -bus_delimiter <> \n\
- -case maintain \n\
- -slice_utilization_ratio 100 \n\
- -bram_utilization_ratio 100 \n\
- -verilog2001 YES \n\
- -fsm_extract YES -fsm_encoding Auto \n\
- -safe_implementation No \n\
- -fsm_style lut \n\
- -ram_extract Yes \n\
- -ram_style Auto \n\
- -rom_extract Yes \n\
- -mux_style Auto \n\
- -decoder_extract YES \n\
- -priority_extract YES \n\
- -shreg_extract YES \n\
- -shift_extract YES \n\
- -xor_collapse YES \n\
- -rom_style Auto \n\
- -auto_bram_packing NO \n\
- -mux_extract YES \n\
- -resource_sharing YES \n\
- -async_to_sync NO \n\
- -mult_style auto \n\
- -iobuf YES \n\
- -max_fanout 500 \n\
- -bufg 8 \n\
- -register_duplication YES \n\
- -register_balancing No \n\
- -slice_packing YES \n\
- -optimize_primitives NO \n\
- -use_clock_enable Yes \n\
- -use_sync_set Yes \n\
- -use_sync_reset Yes \n\
- -iob auto \n\
- -equivalent_register_removal YES \n\
- -slice_utilization_ratio_maxmargin 5\n\
- " >> $(BIN)/$(PROJECT).xst
-
-clean : ghdl-clean
- -rm -rf $(BIN)
- -rm -rf _ngo
- -rm xilinx_device_details.xml
-
########################
# Simulation with GHDL
########################
-ghdl-compile :
+help:
+ @echo 'Cleaning:'
+ @echo ' clean - delete simulation directory'
+ @echo
+ @echo 'simulate:'
+ @echo ' ghdl-simu - make behavioural simulation'
+ @echo ' ghdl-synthesis - make post synthesis simulation'
+ @echo ' ghdl-pr - make post place and route simulation'
+ @echo ' '
+ @echo 'view result:'
+ @echo ' ghdl-view - Launch wave view with gtk-waves'
+
+ghdl-simu : ghdl-compil ghdl-run
+ghdl-synthesis : ghdl-compil-synthesis ghdl-run
+ghdl-pr : ghdl-compil-pr ghdl-run
+
+ghdl-compil :
mkdir -p simu
- $(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES)
- $(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simu --work=work $(SIMTOP)
+ $(GHDL_CMD) -i $(GHDL_SIMU_FLAGS) --workdir=simu --work=work $(TESTBENCH_FILE) $(LIBRARY_FILE) $(FILES)
+ $(GHDL_CMD) -m $(GHDL_SIMU_FLAGS) --workdir=simu --work=work $(SIMTOP)
@mv $(SIMTOP) simu/$(SIMTOP)
-#TODO: make it working !
-ghdl-simsynth :
- $(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simu --work=work $(SYNTHFILES) $(SIMFILES)
- $(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simu --work=work $(SIMTOP)
+ghdl-compil-synthesis:
+ @if [ ! -e $(SYNTHESIS_FILE) ] ; then\
+ echo "You have to copy $(SYNTHESIS_FILE), in this directory first" ;\
+ [ -e $(SYNTHESIS_FILE) ];\
+ fi;
+ mkdir -p simu
+ $(GHDL_CMD) -i $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(TESTBENCH_FILE) $(LIBRARY_FILE) $(SYNTHESIS_FILE)
+ $(GHDL_CMD) -m $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SIMTOP)
@mv $(SIMTOP) simu/$(SIMTOP)
+ghdl-compil-pr :
+ @if [ ! -e $(PLACE_AND_ROUTE_FILE) ] ; then\
+ echo "You have to copy $(PLACE_AND_ROUTE_FILE), in this directory first" ;\
+ [ -e $(PLACE_AND_ROUTE_FILE) ];\
+ fi;
+ mkdir -p simu
+ $(GHDL_CMD) -i $(GHDL_PANDR_FLAGS) --workdir=simu --work=work $(TESTBENCH_FILE) $(LIBRARY_FILE) $(PLACE_AND_ROUTE_FILE)
+ $(GHDL_CMD) -m $(GHDL_PANDR_FLAGS) --workdir=simu --work=work $(SIMTOP)
+ @mv $(SIMTOP) simu/$(SIMTOP)
+
ghdl-run :
@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
ghdl-view:
gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd
-ghdl-clean :
- $(GHDL_CMD) --clean --workdir=simu
+clean :
+ $(GHDL_CMD) --clean --workdir=simu
-rm -rf simu
-
Modified: trunk/firmware/wishbone_example/README
===================================================================
--- trunk/firmware/wishbone_example/README 2009-03-03 10:22:12 UTC (rev 1107)
+++ trunk/firmware/wishbone_example/README 2009-03-03 16:03:26 UTC (rev 1108)
@@ -4,18 +4,19 @@
send it to i.mx processor.To manage these irq
two registers are available :
irq_mask ( addr : 0x0000) : enable irq writing 1
- irq_pend/irq_ack (addr : 0x0002) : writing 1 acknowledge irq
- and reading 1 inform that an irq pending.
+ irq_pend/irq_ack (addr : 0x0002) : writing 1 acknowledge irq and
+ reading 1 inform that an irq
+ pending.
This design use one irq for button push and release.
* wb_led : a simple led register, one led is branched on register LSB.
To switch on led write '0' on led register. Address register
is :
- LED (addr : 0x0004) : on/off led
+ LED (addr : 0x0008) : on/off led
* wb_button: Simple button register, when button is pressed, register LSB
is '0', and when it's release LSB is '1'. On each switching
an interuption is send to irq_mngr. Address register is :
- button (addr : 0x0008) : read pressed value
+ button (addr : 0x000e) : read pressed value
see
http://www.armadeus.com/wiki/index.php?title=A_simple_design_with_Wishbone_bus
Added: trunk/firmware/wishbone_example/src/button.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/button.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/button.vhd 2009-03-03 16:03:26 UTC (rev 1108)
@@ -0,0 +1,98 @@
+---------------------------------------------------------------------------
+-- Company : ARMades Systems
+-- Author(s) : Fabien Marteau <fab...@ar...>
+--
+-- Creation Date : 10/03/2008
+-- File : button.vhd
+--
+-- Abstract :
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity button is
+---------------------------------------------------------------------------
+ generic(
+ id : natural := 2
+ );
+ port
+ (
+ -- global signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ -- Wishbone signals
+ wbs_add : in std_logic ;
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_cycle : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- irq
+ irq : out std_logic ;
+ -- fpga input
+ button : in std_logic
+ );
+end entity;
+
+
+---------------------------------------------------------------------------
+Architecture button_1 of button is
+ ---------------------------------------------------------------------------
+ signal button_r : std_logic ;
+ signal reg : std_logic_vector( 15 downto 0);
+begin
+
+ -- connect button
+ cbutton : process(gls_clk,gls_reset)
+ begin
+ if gls_reset = '1' then
+ reg <= (others => '0');
+ elsif rising_edge(gls_clk) then
+ reg <= "000000000000000"&button;
+ end if;
+ end process cbutton;
+
+
+ -- rise interruption
+ pbutton : process(gls_clk,gls_reset)
+ begin
+ if gls_reset = '1' then
+ irq <= '0';
+ button_r <= '0';
+ elsif rising_edge(gls_clk) then
+ if button_r /= button then
+ irq <= '1';
+ else
+ irq <= '0';
+ end if;
+ button_r <= button;
+ end if;
+ end process pbutton;
+
+ -- register reading process
+ pread : process(gls_clk,gls_reset)
+ begin
+ if(gls_reset = '1') then
+ wbs_ack <= '0';
+ wbs_readdata <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ wbs_ack <= '0';
+ if(wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1')then
+ wbs_ack <= '1';
+ if wbs_add = '0' then
+ wbs_readdata <= std_logic_vector(to_unsigned(id,16));
+ else
+ wbs_readdata <= reg;
+ end if;
+ else
+ wbs_readdata <= (others => '0');
+ end if;
+ end if;
+ end process pread;
+
+end architecture button_1;
+
Added: trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd 2009-03-03 16:03:26 UTC (rev 1108)
@@ -0,0 +1,95 @@
+-------------------------------------------------------------------------------
+--
+-- File : imx9328_wb16_wrapper.vhd
+-- Related files : (none)
+--
+-- Author(s) : Fabrice Mousset (fab...@la...)
+-- Project : i.MX wrapper to Wishbone bus
+--
+-- Creation Date : 2007/01/19
+--
+-- Description : This is the top file of the IP
+-------------------------------------------------------------------------------
+-- Modifications :
+-----
+-- 2008/03/05
+-- Fabien Marteau (fab...@ar...)
+-- adding comments and changing some signals names
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+
+-- ----------------------------------------------------------------------------
+ Entity imx9328_wb16_wrapper is
+-- ----------------------------------------------------------------------------
+ port
+ (
+ -- i.MX Signals
+ imx_address : in std_logic_vector(11 downto 0); -- LSB not used
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_oe_n : in std_logic;
+ imx_eb3_n : in std_logic;
+
+ -- Global Signals
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
+
+ -- Interrupt out for write error
+-- int_err : out std_logic;
+
+ -- Wishbone interface signals
+ wbm_address : out std_logic_vector(12 downto 0); -- Address bus
+ wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
+ wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
+ wbm_strobe : out std_logic; -- Data Strobe
+ wbm_write : out std_logic; -- Write access
+ wbm_ack : in std_logic ; -- acknowledge
+ wbm_cycle : out std_logic -- bus cycle in progress
+ );
+ end entity;
+
+-- ----------------------------------------------------------------------------
+ Architecture RTL of imx9328_wb16_wrapper is
+-- ----------------------------------------------------------------------------
+
+signal write : std_logic;
+signal read : std_logic;
+signal strobe : std_logic;
+signal writedata : std_logic_vector(15 downto 0);
+signal address : std_logic_vector(12 downto 0);
+
+begin
+
+-- ----------------------------------------------------------------------------
+-- External signals synchronization process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ write <= '0';
+ read <= '0';
+ strobe <= '0';
+ writedata <= (others => '0');
+ address <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb3_n);
+ write <= not (imx_cs_n or imx_eb3_n);
+ read <= not (imx_cs_n or imx_oe_n);
+ address <= imx_address & '0';
+ writedata <= imx_data;
+ end if;
+end process;
+
+wbm_address <= address when (strobe = '1') else (others => '0');
+wbm_writedata <= writedata when (write = '1') else (others => '0');
+wbm_strobe <= strobe;
+wbm_write <= write;
+wbm_cycle <= strobe;
+
+imx_data <= wbm_readdata when(read = '1' ) else (others => 'Z');
+
+end architecture RTL;
Added: trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd 2009-03-03 16:03:26 UTC (rev 1108)
@@ -0,0 +1,168 @@
+---------------------------------------------------------------------------
+-- Company : Automaticaly generated by POD
+-- Author(s) :
+--
+-- Creation Date : 2009-03-03
+-- File : imx9328_wb16_wrapper00_mwb16.vhd
+--
+-- Abstract :
+-- Connect slaves to mwb16 from imx9328_wb16_wrapper00
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+Entity imx9328_wb16_wrapper00_mwb16 is
+ port
+ (
+
+ -- irq_mngr00_swb16 connection
+ irq_mngr00_wbs_s1_address : out std_logic_vector(1 downto 0);
+ irq_mngr00_wbs_s1_readdata : in std_logic_vector(15 downto 0);
+ irq_mngr00_wbs_s1_writedata : out std_logic_vector(15 downto 0);
+ irq_mngr00_wbs_s1_ack : in std_logic;
+ irq_mngr00_wbs_s1_strobe : out std_logic;
+ irq_mngr00_wbs_s1_cycle : out std_logic;
+ irq_mngr00_wbs_s1_write : out std_logic;
+
+ -- irq_mngr00_candr connection
+ irq_mngr00_gls_clk : out std_logic;
+ irq_mngr00_gls_reset : out std_logic;
+
+ -- led0_swb16 connection
+ led0_wbs_add : out std_logic;
+ led0_wbs_writedata : out std_logic_vector(15 downto 0);
+ led0_wbs_readdata : in std_logic_vector(15 downto 0);
+ led0_wbs_strobe : out std_logic;
+ led0_wbs_cycle : out std_logic;
+ led0_wbs_write : out std_logic;
+ led0_wbs_ack : in std_logic;
+
+ -- led0_candr connection
+ led0_gls_reset : out std_logic;
+ led0_gls_clk : out std_logic;
+
+ -- button0_swb16 connection
+ button0_wbs_add : out std_logic;
+ button0_wbs_readdata : in std_logic_vector(15 downto 0);
+ button0_wbs_strobe : out std_logic;
+ button0_wbs_write : out std_logic;
+ button0_wbs_ack : in std_logic;
+ button0_wbs_cycle : out std_logic;
+
+ -- button0_candr connection
+ button0_gls_reset : out std_logic;
+ button0_gls_clk : out std_logic;
+
+ -- imx9328_wb16_wrapper00_mwb16 connection
+ imx9328_wb16_wrapper00_wbm_address : in std_logic_vector(12 downto 0);
+ imx9328_wb16_wrapper00_wbm_readdata : out std_logic_vector(15 downto 0);
+ imx9328_wb16_wrapper00_wbm_writedata : in std_logic_vector(15 downto 0);
+ imx9328_wb16_wrapper00_wbm_strobe : in std_logic;
+ imx9328_wb16_wrapper00_wbm_write : in std_logic;
+ imx9328_wb16_wrapper00_wbm_ack : out std_logic;
+ imx9328_wb16_wrapper00_wbm_cycle : in std_logic;
+
+ -- imx9328_wb16_wrapper00_candr connection
+ imx9328_wb16_wrapper00_gls_reset : out std_logic;
+ imx9328_wb16_wrapper00_gls_clk : out std_logic;
+
+ -- rstgen_syscon00_imx9328_wb16_wrapper00 connection
+ rstgen_syscon00_gls_clk : in std_logic;
+ rstgen_syscon00_gls_reset : in std_logic
+ );
+end entity;
+
+architecture imx9328_wb16_wrapper00_mwb16_1 of imx9328_wb16_wrapper00_mwb16 is
+ signal irq_mngr00_swb16_cs : std_logic := '0' ;
+ signal led0_swb16_cs : std_logic := '0' ;
+ signal button0_swb16_cs : std_logic := '0' ;
+begin
+
+ -- Clock and Reset connection
+ irq_mngr00_gls_clk <= rstgen_syscon00_gls_clk;
+ irq_mngr00_gls_reset <= rstgen_syscon00_gls_reset;
+
+ led0_gls_reset <= rstgen_syscon00_gls_reset;
+ led0_gls_clk <= rstgen_syscon00_gls_clk;
+
+ button0_gls_reset <= rstgen_syscon00_gls_reset;
+ button0_gls_clk <= rstgen_syscon00_gls_clk;
+
+ imx9328_wb16_wrapper00_gls_reset <= rstgen_syscon00_gls_reset;
+ imx9328_wb16_wrapper00_gls_clk <= rstgen_syscon00_gls_clk;
+
+
+ -- Address decoding --
+ -----------------------
+ irq_mngr00_wbs_s1_address <= imx9328_wb16_wrapper00_wbm_address(2 downto 1);
+ led0_wbs_add <= imx9328_wb16_wrapper00_wbm_address(1);
+ button0_wbs_add <= imx9328_wb16_wrapper00_wbm_address(1);
+
+ decodeproc : process(rstgen_syscon00_gls_clk,rstgen_syscon00_gls_reset,imx9328_wb16_wrapper00_wbm_address)
+ begin
+ if rstgen_syscon00_gls_reset='1' then
+ irq_mngr00_swb16_cs <= '0';
+ led0_swb16_cs <= '0';
+ button0_swb16_cs <= '0';
+ elsif rising_edge(rstgen_syscon00_gls_clk) then
+
+ if imx9328_wb16_wrapper00_wbm_address(12 downto 3)="0000000000" and imx9328_wb16_wrapper00_wbm_strobe='1' then
+ irq_mngr00_swb16_cs <= '1';
+ else
+ irq_mngr00_swb16_cs <= '0';
+ end if;
+
+ if imx9328_wb16_wrapper00_wbm_address(12 downto 2)="00000000010" and imx9328_wb16_wrapper00_wbm_strobe='1' then
+ led0_swb16_cs <= '1';
+ else
+ led0_swb16_cs <= '0';
+ end if;
+
+ if imx9328_wb16_wrapper00_wbm_address(12 downto 2)="00000000011" and imx9328_wb16_wrapper00_wbm_strobe='1' then
+ button0_swb16_cs <= '1';
+ else
+ button0_swb16_cs <= '0';
+ end if;
+
+ end if;
+ end process decodeproc;
+
+ -----------------------------
+ -- Control signals to slave
+ -----------------------------
+
+ -- for irq_mngr00
+ irq_mngr00_wbs_s1_strobe <= (imx9328_wb16_wrapper00_wbm_strobe and irq_mngr00_swb16_cs );
+ irq_mngr00_wbs_s1_cycle <= (imx9328_wb16_wrapper00_wbm_cycle and irq_mngr00_swb16_cs );
+ irq_mngr00_wbs_s1_write <= (imx9328_wb16_wrapper00_wbm_write and irq_mngr00_swb16_cs );
+ irq_mngr00_wbs_s1_writedata <= imx9328_wb16_wrapper00_wbm_writedata when (imx9328_wb16_wrapper00_wbm_write and irq_mngr00_swb16_cs ) = '1' else (others => '0');
+
+ -- for led0
+ led0_wbs_strobe <= (imx9328_wb16_wrapper00_wbm_strobe and led0_swb16_cs );
+ led0_wbs_cycle <= (imx9328_wb16_wrapper00_wbm_cycle and led0_swb16_cs );
+ led0_wbs_write <= (imx9328_wb16_wrapper00_wbm_write and led0_swb16_cs );
+ led0_wbs_writedata <= imx9328_wb16_wrapper00_wbm_writedata when (imx9328_wb16_wrapper00_wbm_write and led0_swb16_cs ) = '1' else (others => '0');
+
+ -- for button0
+ button0_wbs_strobe <= (imx9328_wb16_wrapper00_wbm_strobe and button0_swb16_cs );
+ button0_wbs_cycle <= (imx9328_wb16_wrapper00_wbm_cycle and button0_swb16_cs );
+ button0_wbs_write <= '0';
+
+
+ -------------------------------
+ -- Control signal for master --
+ -------------------------------
+ imx9328_wb16_wrapper00_wbm_readdata <= irq_mngr00_wbs_s1_readdata when irq_mngr00_swb16_cs='1' else
+ led0_wbs_readdata when led0_swb16_cs='1' else
+ button0_wbs_readdata when button0_swb16_cs='1' else
+ (others => '0');
+ imx9328_wb16_wrapper00_wbm_ack <= (irq_mngr00_wbs_s1_ack and irq_mngr00_swb16_cs)
+ or
+ (led0_wbs_ack and led0_swb16_cs)
+ or
+ (button0_wbs_ack and button0_swb16_cs);
+
+end architecture imx9328_wb16_wrapper00_mwb16_1;
Deleted: trunk/firmware/wishbone_example/src/intercon.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/intercon.vhd 2009-03-03 10:22:12 UTC (rev 1107)
+++ trunk/firmware/wishbone_example/src/intercon.vhd 2009-03-03 16:03:26 UTC (rev 1108)
@@ -1,157 +0,0 @@
----------------------------------------------------------------------------
--- Company : ARMadeus Systems
--- Author(s) : Fabien Marteau
---
--- Creation Date : 05/03/2008
--- File : intercon.vhd
---
--- Abstract : connect master wishbone device with
--- slave(s) wishbone device
---
------------------------------------------------------------------------------------
--- This program is free software; you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation; either version 2, or (at your option)
--- any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program; if not, write to the Free Software
--- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.all;
-
----------------------------------------------------------------------------
-Entity intercon is
----------------------------------------------------------------------------
- port
- (
- -- imx wishbone master connexion
- gls_reset_m1 : out std_logic ;
- gls_clk_m1 : out std_logic ;
-
- wbm_address_m1 : in std_logic_vector( 12 downto 0);
- wbm_readdata_m1 : out std_logic_vector( 15 downto 0);
- wbm_writedata_m1 : in std_logic_vector( 15 downto 0);
- wbm_strobe_m1 : in std_logic ;
- wbm_write_m1 : in std_logic ;
- wbm_sel_m1 : in std_logic_vector( 1 downto 0);
- wbm_ack_m1 : out std_logic ;
- wbm_cycle_m1 : in std_logic ;
-
- -- led wishbone slave connexion
- gls_reset_s1 : out std_logic ;
- gls_clk_s1 : out std_logic ;
- wbs_writedata_s1 : out std_logic_vector( 15 downto 0);
- wbs_readdata_s1 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s1 : out std_logic ;
- wbs_write_s1 : out std_logic ;
- wbs_ack_s1 : in std_logic ;
-
- -- button slave connexion
- gls_reset_s2 : out std_logic ;
- gls_clk_s2 : out std_logic ;
- wbs_readdata_s2 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s2 : out std_logic ;
- wbs_write_s2 : out std_logic ;
- wbs_ack_s2 : in std_logic ;
- wbs_irq_s2 : in std_logic ;
-
- -- irq slave connexion
- gls_reset_s3 : out std_logic ;
- gls_clk_s3 : out std_logic ;
- wbs_address_s3 : out std_logic ;
- wbs_writedata_s3 : out std_logic_vector( 15 downto 0);
- wbs_readdata_s3 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s3 : out std_logic ;
- wbs_write_s3 : out std_logic ;
- wbs_ack_s3 : in std_logic ;
- wbs_irq_s3 : out std_logic ;
-
- -- syscon connection
- gls_reset_sys : in std_logic ;
- gls_clk_sys : in std_logic
- );
-end entity;
-
----------------------------------------------------------------------------
-Architecture intercon_1 of intercon is
----------------------------------------------------------------------------
- signal led_cs : std_logic ;
- signal button_cs : std_logic ;
- signal irq_cs : std_logic ;
- signal cs :std_logic_vector( 2 downto 0);
-begin
-
- -- clock and reset management
- gls_reset_s1 <= gls_reset_sys;
- gls_clk_s1 <= gls_clk_sys;
-
- gls_reset_s2 <= gls_reset_sys;
- gls_clk_s2 <= gls_clk_sys;
-
- gls_reset_s3 <= gls_reset_sys;
- gls_clk_s3 <= gls_clk_sys;
-
- gls_reset_m1 <= gls_reset_sys;
- gls_clk_m1 <= gls_clk_sys;
-
- -----------------------------
- -- master => slave connexions
- -----------------------------
- -- address decode
- irq_cs <= '1' when wbm_address_m1 = "0000000000000" or wbm_address_m1 = "0000000000010"
- else '0';
- led_cs <= '1' when wbm_address_m1 = "0000000000100"
- else '0';
- button_cs <= '1' when wbm_address_m1 = "0000000001000"
- else '0';
-
- wbs_address_s3 <= wbm_address_m1(1);
-
- -- control signals
- -- for led (s1)
- wbs_writedata_s1 <= wbm_writedata_m1 when (wbm_write_m1 and led_cs)='1'
- else (others => '0');
- wbs_strobe_s1 <= (wbm_strobe_m1 and led_cs);
- wbs_write_s1 <= (wbm_write_m1 and led_cs);
- -- for button(s2) read only
- wbs_strobe_s2 <= (wbm_strobe_m1 and button_cs);
- wbs_write_s2 <= '0';
-
- -- for irq (s3)
- wbs_writedata_s3 <= wbm_writedata_m1 when (wbm_write_m1 and irq_cs)='1'
- else (others => '0');
- wbs_strobe_s3 <= (wbm_strobe_m1 and irq_cs);
- wbs_write_s3 <= (wbm_write_m1 and irq_cs);
-
- -----------------------------
- -- slave => master connexions
- -----------------------------
- cs(0) <= led_cs;
- cs(1) <= button_cs;
- cs(2) <= irq_cs;
-
- with cs select
- wbm_readdata_m1 <= wbs_readdata_s1 when "001",
- wbs_readdata_s2 when "010",
- wbs_readdata_s3 when "100",
- (others => '0') when others;
- with cs select
- wbm_ack_m1 <= wbs_ack_s1 when "001",
- wbs_ack_s2 when "010",
- wbs_ack_s3 when "100",
- '0' when others;
-
- -- irq management
- wbs_irq_s3 <= wbs_irq_s2;
-
-end architecture intercon_1;
Added: trunk/firmware/wishbone_example/src/irq_mngr.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/irq_mngr.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/irq_mngr.vhd 2009-03-03 16:03:26 UTC (rev 1108)
@@ -0,0 +1,154 @@
+-------------------------------------------------------------------------------
+--
+-- File : irq_mnrg.vhd
+-- Related files : (none)
+--
+-- Author(s) : Fabrice Mousset (fab...@la...)
+-- Project : Wishbone Interruption Manager
+--
+-- Creation Date : 2007/01/05
+--
+-- Description : This is the top file of the IP
+-------------------------------------------------------------------------------
+-- Modifications :
+-- 20/10/2008 : Detected rising edge instead of high state
+-- Fabien Marteau <fab...@ar...>
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+
+-- ----------------------------------------------------------------------------
+ Entity irq_mngr is
+-- ----------------------------------------------------------------------------
+ generic
+ (
+ id : natural := 0;
+ irq_count : integer := 16; -- always 16 default
+ irq_level : std_logic := '1'
+ );
+ port
+ (
+ -- Global Signals
+ gls_clk : in std_logic;
+ gls_reset : in std_logic;
+
+ -- Wishbone interface signals
+ wbs_s1_address : in std_logic_vector(1 downto 0); -- Address bus
+ wbs_s1_readdata : out std_logic_vector(15 downto 0); -- Data bus for read access
+ wbs_s1_writedata : in std_logic_vector(15 downto 0); -- Data bus for write access
+ wbs_s1_ack : out std_logic; -- Access acknowledge
+ wbs_s1_strobe : in std_logic; -- Strobe
+ wbs_s1_cycle : in std_logic ; -- Cycle
+ wbs_s1_write : in std_logic; -- Write access
+
+ -- irq from other IP
+ irqport : in std_logic_vector(irq_count-1 downto 0);
+
+ -- Component external signals
+ gls_irq : out std_logic -- IRQ request
+ );
+ end entity;
+
+-- ----------------------------------------------------------------------------
+ Architecture RTL of irq_mngr is
+-- ----------------------------------------------------------------------------
+
+signal irq_r : std_logic_vector(irq_count-1 downto 0);
+signal irq_old : std_logic_vector(irq_count-1 downto 0);
+
+signal irq_pend : std_logic_vector(irq_count-1 downto 0);
+signal irq_ack : std_logic_vector(irq_count-1 downto 0);
+
+signal irq_mask : std_logic_vector(irq_count-1 downto 0);
+
+signal readdata : std_logic_vector(15 downto 0);
+signal rd_ack : std_logic;
+signal wr_ack : std_logic;
+
+begin
+
+-- ----------------------------------------------------------------------------
+-- External signals synchronization process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ irq_r <= (others => '0');
+ irq_old <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ irq_r <= irqport;
+ irq_old <= irq_r;
+ end if;
+end process;
+
+-- ----------------------------------------------------------------------------
+-- Interruption requests latching process on rising edge
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ irq_pend <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ irq_pend <= (irq_pend or ((irq_r and (not irq_old))and irq_mask)) and (not irq_ack);
+ end if;
+end process;
+
+-- ----------------------------------------------------------------------------
+-- Register reading process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ rd_ack <= '0';
+ readdata <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ rd_ack <= '0';
+ if(wbs_s1_strobe = '1' and wbs_s1_write = '0' and wbs_s1_cycle = '1') then
+ rd_ack <= '1';
+ if(wbs_s1_address = "00") then
+ readdata(irq_count-1 downto 0) <= irq_mask;
+ elsif(wbs_s1_address="01") then
+ readdata(irq_count-1 downto 0) <= irq_pend;
+ elsif(wbs_s1_address="10") then
+ readdata <= std_logic_vector(to_unsigned(id,16));
+ else
+ readdata <= (others => '0');
+ end if;
+ end if;
+ end if;
+end process;
+
+-- ----------------------------------------------------------------------------
+-- Register update process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ irq_ack <= (others => '0');
+ wr_ack <= '0';
+ irq_mask <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ irq_ack <= (others => '0');
+ wr_ack <= '0';
+
+ if(wbs_s1_strobe = '1' and wbs_s1_write = '1' and wbs_s1_cycle = '1') then
+ wr_ack <= '1';
+ if(wbs_s1_address = "00") then
+ irq_mask <= wbs_s1_writedata(irq_count-1 downto 0);
+ elsif(wbs_s1_address = "01") then
+ irq_ack <= wbs_s1_writedata(irq_count-1 downto 0);
+ end if;
+ end if;
+ end if;
+end process;
+
+gls_irq <= irq_level when(unsigned(irq_pend) /= 0 and gls_reset = '0') else
+ not irq_level;
+
+wbs_s1_ack <= rd_ack or wr_ack;
+wbs_s1_readdata <= readdata when (wbs_s1_strobe = '1' and wbs_s1_write = '0' and wbs_s1_cycle = '1') else (others => '0');
+
+end architecture RTL;
Added: trunk/firmware/wishbone_example/src/led.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/led.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/led.vhd 2009-03-03 16:03:26 UTC (rev 1108)
@@ -0,0 +1,86 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 05/03/2008
+-- File : led.vhd
+--
+-- Abstract : drive one led with Wishbone bus
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-----------------------------------------------------------------------
+ Entity led is
+-----------------------------------------------------------------------
+ generic(
+ id : natural := 1;
+ wb_size : natural := 16 -- Data port size for wishbone
+ );
+ port
+ (
+ -- Syscon signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ -- Wishbone signals
+ wbs_add : in std_logic ;
+ wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
+ wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_cycle : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- out signals
+ led : out std_logic
+ );
+end entity led;
+
+
+-----------------------------------------------------------------------
+Architecture led_1 of led is
+-----------------------------------------------------------------------
+ signal reg : std_logic_vector( wb_size-1 downto 0);
+begin
+
+-- connect led
+led <= reg(0);
+
+wbs_ack <= wbs_strobe;
+
+-- manage register
+write_bloc : process(gls_clk,gls_reset)
+begin
+ if gls_reset = '1' then
+ reg <= (others => '0');
+ elsif rising_edge(gls_clk) then
+ if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
+ reg <= wbs_writedata;
+ else
+ reg <= reg;
+ end if;
+ end if;
+
+end process write_bloc;
+
+read_bloc : process(gls_clk, gls_reset)
+begin
+ if gls_reset = '1' then
+ wbs_readdata <= (others => '0');
+ elsif rising_edge(gls_clk) then
+ if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
+ if wbs_add = '0' then
+ wbs_readdata <= reg;
+ else
+ wbs_readdata <= std_logic_vector(to_unsigned(id,wb_size));
+ end if;
+ else
+ wbs_readdata <= (others => '0');
+ end if;
+ end if;
+end process read_bloc;
+
+end architecture led_1;
+
Added: trunk/firmware/wishbone_example/src/rstgen_syscon.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/rstgen_syscon.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/rstgen_syscon.vhd 2009-03-03 16:03:26 UTC (rev 1108)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 05/03/2008
+-- File : rstgen_syscon.vhd
+--
+-- Abstract :
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity rstgen_syscon is
+---------------------------------------------------------------------------
+generic(
+ invert_reset : std_logic := '0' -- 0 : not invert, 1 invert
+);
+port
+(
+ -- external signals
+ ext_clk : in std_logic ;
+ --internal signals
+ gls_clk : out std_logic ;
+ gls_reset : out std_logic
+);
+end entity;
+
+
+---------------------------------------------------------------------------
+Architecture rstgen_syscon_1 of rstgen_syscon is
+---------------------------------------------------------------------------
+
+ signal dly: std_logic := '0';
+ signal rst: std_logic := '0';
+ signal ext_reset : std_logic;
+
+begin
+
+ ext_reset <= '0';
+----------------------------------------------------------------------------
+-- RESET signal generator.
+----------------------------------------------------------------------------
+process(ext_clk)
+begin
+ if(rising_edge(ext_clk)) then
+ dly <= ( not(ext_reset) and dly and not(rst) )
+ or ( not(ext_reset) and not(dly) and rst );
+
+ rst <= ( not(ext_reset) and not(dly) and not(rst) );
+ end if;
+end process;
+
+gls_clk <= ext_clk;
+gls_reset <= rst xor invert_reset ;
+
+end architecture rstgen_syscon_1;
+
Added: trunk/firmware/wishbone_example/src/top_wishbone_example.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/top_wishbone_example.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/top_wishbone_example.vhd 2009-03-03 16:03:26 UTC (rev 1108)
@@ -0,0 +1,535 @@
+---------------------------------------------------------------------------
+-- Company : Automaticaly generated by POD
+-- Author(s) :
+--
+-- Creation Date : 2009-03-03
+-- File : Top_wishbone_example.vhd
+--
+-- Abstract :
+-- insert a description here
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+entity top_wishbone_example is
+
+ port
+ (
+ imx9328_wb16_wrapper00_imx_data : inout std_logic_vector(15 downto 0);
+ imx9328_wb16_wrapper00_imx_address : in std_logic_vector(11 downto 0);
+ rstgen_syscon00_ext_clk : in std_logic;
+ imx9328_wb16_wrapper00_imx_cs_n : in std_logic;
+ imx9328_wb16_wrapper00_imx_eb3_n : in std_logic;
+ imx9328_wb16_wrapper00_imx_oe_n : in std_logic;
+ irq_mngr00_gls_irq : out std_logic;
+ led0_led : out std_logic;
+ button0_button : in std_logic
+ );
+end entity top_wishbone_example;
+
+architecture top_wishbone_example_1 of top_wishbone_example is
+ -------------------------
+ -- declare components --
+ -------------------------
+
+
+ component rstgen_syscon
+ port (
+ -- candr
+ gls_clk : out std_logic;
+ gls_reset : out std_logic;
+ -- clk_ext
+ ext_clk : in std_logic
+ );
+ end component;
+
+ component led
+ generic(
+ id : natural := 2;
+ wb_size : natural := 16
+ );
+ port (
+ -- int_led
+ led : out std_logic;
+ -- candr
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
+ -- swb16
+ wbs_add : in std_logic;
+ wbs_writedata : in std_logic_vector(15 downto 0);
+ wbs_readdata : out std_logic_vector(15 downto 0);
+ wbs_strobe : in std_logic;
+ wbs_cycle : in std_logic;
+ wbs_write : in std_logic;
+ wbs_ack : out std_logic
+ );
+ end component;
+
+ component button
+ generic(
+ id : natural := 3
+ );
+ port (
+ -- int_button
+ button : in std_logic;
+ irq : out std_logic;
+ -- candr
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
+ -- swb16
+ wbs_add : in std_logic;
+ wbs_readdata : out std_logic_vector(15 downto 0);
+ wbs_strobe : in std_logic;
+ wbs_write : in std_logic;
+ wbs_ack : out std_logic;
+ wbs_cycle : in std_logic
+ );
+ end component;
+
+ component imx9328_wb16_wrapper
+ port (
+ -- eim
+ imx_address : in std_logic_vector(11 downto 0);
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_oe_n : in std_logic;
+ imx_eb3_n : in std_logic;
+ -- candr
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
+ -- mwb16
+ wbm_address : out std_logic_vector(12 downto 0);
+ wbm_readdata : in std_logic_vector(15 downto 0);
+ wbm_writedata : out std_logic_vector(15 downto 0);
+ wbm_strobe : out std_logic;
+ wbm_write : out std_logic;
+ wbm_ack : in std_logic;
+ wbm_cycle : out std_logic
+ );
+ end component;
+
+ component irq_mngr
+ generic(
+ id : natural := 1;
+ irq_level : std_logic := '1';
+ irq_count : integer := 1
+ );
+ port (
+ -- candr
+ gls_clk : in std_logic;
+ gls_reset : in std_logic;
+ -- swb16
+ wbs_s1_address : in std_logic_vector(1 downto 0);
+ wbs_s1_readdata : out std_logic_vector(15 downto 0);
+ wbs_s1_writedata : in std_logic_vector(15 downto 0);
+ wbs_s1_ack : out std_logic;
+ wbs_s1_strobe : in std_logic;
+ wbs_s1_cycle : in std_logic;
+ wbs_s1_write : in std_logic;
+ -- irq
+ irqport : in std_logic_vector(0 downto 0);
+ -- ext_irq
+ gls_irq : out std_logic
+ );
+ end component;
+
+ component imx9328_wb16_wrapper00_mwb16
+ port (
+ -- irq_mngr00_swb16
+ irq_mngr00_wbs_s1_address : out std_logic_vector(1 downto 0);
+ irq_mngr00_wbs_s1_readdata : in std_logic_vector(15 downto 0);
+ irq_mngr00_wbs_s1_writedata : out std_logic_vector(15 downto 0);
+ irq_mngr00_wbs_s1_ack : in std_logic;
+ irq_mngr00_wbs_s1_strobe : out std_logic;
+ irq_mngr00_wbs_s1_cycle : out std_logic;
+ irq_mngr00_wbs_s1_write : out std_logic;
+ -- irq_mngr00_candr
+ irq_mngr00_gls_clk : out std_logic;
+ irq_mngr00_gls_reset : out std_logic;
+ -- led0_swb16
+ led0_wbs_add : out std_logic;
+ led0_wbs_writedata : out std_logic_vector(15 downto 0);
+ led0_wbs_readdata : in std_logic_vector(15 downto 0);
+ led0_wbs_strobe : out std_logic;
+ led0_wbs_cycle : out std_logic;
+ led0_wbs_write : out std_logic;
+ led0_wbs_ack : in std_logic;
+ -- led0_candr
+ led0_gls_reset : out std_logic;
+ led0_gls_clk : out std_logic;
+ -- button0_swb16
+ button0_wbs_add : out std_logic;
+ button0_wbs_readdata : in std_logic_vector(15 downto 0);
+ button0_wbs_strobe : out std_logic;
+ button0_wbs_write : out std_logic;
+ button0_wbs_ack : in std_logic;
+ button0_wbs_cycle : out std_logic;
+ -- button0_candr
+ button0_gls_reset : out std_logic;
+ button0_gls_clk : out std_logic;
+ -- imx9328_wb16_wrapper00_mwb16
+ imx9328_wb16_wrapper00_wbm_address : in std_logic_vector(12 downto 0);
+ imx9328_wb16_wrapper00_wbm_readdata : out std_logic_vector(15 downto 0);
+ imx9328_wb16_wrapper00_wbm_writedata : in std_logic_vector(15 downto 0);
+ imx9328_wb16_wrapper00_wbm_strobe : in std_logic;
+ imx9328_wb16_wrapper00_wbm_write : in std_logic;
+ imx9328_wb16_wrapper00_wbm_ack : out std_logic;
+ imx9328_wb16_wrapper00_wbm_cycle : in std_logic;
+ -- imx9328_wb16_wrapper00_candr
+ imx9328_wb16_wrapper00_gls_reset : out std_logic;
+ imx9328_wb16_wrapper00_gls_clk : out std_logic;
+ -- rstgen_syscon00_imx9328_wb16_wrapper00
+ rstgen_syscon00_gls_clk : in std_logic;
+ rstgen_syscon00_gls_reset : in std_logic
+ );
+ end component;
+ -------------------------
+ -- Signals declaration
+ -------------------------
+
+ -- imx9328_wb16_wrapper00
+ -- eim
+ -- candr
+ signal imx9328_wb16_wrapper00_gls_reset : std_logic;
+ signal imx9328_wb16_wrapper00_gls_clk : std_logic;
+ -- mwb16
+ signal imx9328_wb16_wrapper00_wbm_address : std_logic_vector(12 downto 0);
+ signal imx9328_wb16_wrapper00_wbm_readdata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_wbm_writedata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_wbm_strobe : std_logic;
+ signal imx9328_wb16_wrapper00_wbm_write : std_logic;
+ signal imx9328_wb16_wrapper00_wbm_ack : std_logic;
+ signal imx9328_wb16_wrapper00_wbm_cycle : std_logic;
+
+ -- rstgen_syscon00
+ -- candr
+ signal rstgen_syscon00_gls_clk : std_logic;
+ signal rstgen_syscon00_gls_reset : std_logic;
+ -- clk_ext
+
+ -- irq_mngr00
+ -- candr
+ signal irq_mngr00_gls_clk : std_logic;
+ signal irq_mngr00_gls_reset : std_logic;
+ -- swb16
+ signal irq_mngr00_wbs_s1_address : std_logic_vector(1 downto 0);
+ signal irq_mngr00_wbs_s1_readdata : std_logic_vector(15 downto 0);
+ signal irq_mngr00_wbs_s1_writedata : std_logic_vector(15 downto 0);
+ signal irq_mngr00_wbs_s1_ack : std_logic;
+ signal irq_mngr00_wbs_s1_strobe : std_logic;
+ signal irq_mngr00_wbs_s1_cycle : std_logic;
+ signal irq_mngr00_wbs_s1_write : std_logic;
+ -- irq
+ signal irq_mngr00_irqport : std_logic_vector(0 downto 0);
+ -- ext_irq
+
+ -- led0
+ -- int_led
+ -- candr
+ signal led0_gls_reset : std_logic;
+ signal led0_gls_clk : std_logic;
+ -- swb16
+ signal led0_wbs_add : std_logic;
+ signal led0_wbs_writedata : std_logic_vector(15 downto 0);
+ signal led0_wbs_readdata : std_logic_vector(15 downto 0);
+ signal led0_wbs_strobe : std_logic;
+ signal led0_wbs_cycle : std_logic;
+ signal led0_wbs_write : std_logic;
+ signal led0_wbs_ack : std_logic;
+
+ -- button0
+ -- int_button
+ signal button0_irq : std_logic;
+ -- candr
+ signal button0_gls_reset : std_logic;
+ signal button0_gls_clk : std_logic;
+ -- swb16
+ signal button0_wbs_add : std_logic;
+ signal button0_wbs_readdata : std_logic_vector(15 downto 0);
+ signal button0_wbs_strobe : std_logic;
+ signal button0_wbs_write : std_logic;
+ signal button0_wbs_ack : std_logic;
+ signal button0_wbs_cycle : std_logic;
+
+ -- imx9328_wb16_wrapper00_mwb16_intercon
+ -- irq_mngr00_swb16
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_address : std_logic_vector(1 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_readdata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_writedata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_ack : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_strobe : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_cycle : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_wbs_s1_write : std_logic;
+ -- irq_mngr00_candr
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_gls_clk : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_irq_mngr00_gls_reset : std_logic;
+ -- led0_swb16
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_add : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_writedata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_readdata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_strobe : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_cycle : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_write : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_wbs_ack : std_logic;
+ -- led0_candr
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_gls_reset : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_led0_gls_clk : std_logic;
+ -- button0_swb16
+ signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_add : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_readdata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_strobe : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_write : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_ack : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_button0_wbs_cycle : std_logic;
+ -- button0_candr
+ signal imx9328_wb16_wrapper00_mwb16_intercon_button0_gls_reset : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_button0_gls_clk : std_logic;
+ -- imx9328_wb16_wrapper00_mwb16
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_address : std_logic_vector(12 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_readdata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_writedata : std_logic_vector(15 downto 0);
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_strobe : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_write : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_ack : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_wbm_cycle : std_logic;
+ -- imx9328_wb16_wrapper00_candr
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_gls_reset : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_imx9328_wb16_wrapper00_gls_clk : std_logic;
+ -- rstgen_syscon00_imx9328_wb16_wrapper00
+ signal imx9328_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_clk : std_logic;
+ signal imx9328_wb16_wrapper00_mwb16_intercon_rstgen_syscon00_gls_reset : std_logic;
+
+ -- void pins
+
+begin
+ -------------------------
+ -- declare instances
+ -------------------------
+
+ imx9328_wb16_wrapper00 : imx9328_wb16_wrapper
+ port map (
+ -- eim
+ imx_address => imx9328_wb16_wrapper00_imx_address,
+ imx_data => imx9328_wb16_wrapper00_imx_data,
+ imx_cs_n => imx9328_wb16_wrapper00_imx_cs_n,
+ imx_oe_n => imx9328_wb16_wrapper00_imx_oe_n,
+ imx_eb3_n => imx9328_wb16_wrapper00_imx_eb3_n,
+ -- candr
+ gls_reset => imx9328_wb16_wrapper00_gls_reset,
+ gls_clk => imx9328_wb16_wrapper00_gls_clk,
+ -- mwb16
+ wbm_address => imx9328_wb16_wrapper00_wbm_address,
+ wbm_readdata => imx9328_wb16_wrapper00_wbm_readdata,
+ wbm_writedata => imx9328_wb16_wrapper00_wbm_writedata,
+ wbm_strobe => imx9328_wb16_wrapper00_wbm_strobe,
+ wbm_write => imx9328_wb16_wrapper00_wbm_write,
+ wbm_ack => imx9328_wb16_wrapper00_wbm_ack,
+ wbm_cycle => imx9328_wb16_wrapper00_wbm_cycle
+ );
+
+ rstgen_syscon00 : rstgen_syscon
+ port map (
+ -- candr
+ gls_clk => rstgen_syscon00_gls_clk,
+ gls_reset => rstgen_syscon00_gls_reset,
+ -- clk_ext
+ ext_clk => rstgen_syscon00_ext_clk
+ );
+
+ irq_mngr00 : irq_mngr
+ generic map (
+ id => 1,
+ irq_level => '1',
+ irq_count => 1
+ )
+ port map (
+ -- candr
+ gls_clk => irq_mngr00_gls_clk,
+ gls_reset => irq_mngr00_gls_reset,
+ -- swb16
+ wbs_s1_address => irq_mngr00_wbs_s1_address,
+ wbs_s1_readdata => irq_mngr00_wbs_s1_readdata,
+ wbs_s1_writedata => irq_mngr00_wbs_s1_writedata,
+ wbs_s1_ack => irq_mngr00_wbs_s1_ack,
+ wbs_s1_strobe => irq_mngr00_wbs_s1_strobe,
+ wbs_s1_cycle => irq_mngr00_wbs_s1_cycle,
+ wbs_s1_write => irq_mngr00_wbs_s1_write,
+ -- irq
+ irqport => irq_mngr00_irqport,
+ -- ext_irq
+ gls_irq => irq_mngr00_gls_irq
+ );
+
+ led0 : led
+ generic map (
+ id => 2,
+ wb_size => 16
+ )
+ port map (
+ -- int_led
+ led => led0_led,
+ -- candr
+ gls_reset => led0_gls_reset,
+ gls_clk => led0_gls_clk,
+ -- swb16
+ wbs_add => led0_wbs_add,
+ wb...
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