[Armadeus-commitlog] SF.net SVN: armadeus:[1106] trunk/firmware/wishbone_example
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[Armadeus-commitlog] SF.net SVN: armadeus:[1106] trunk/firmware/wishbone_example
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From: <Fa...@us...> - 2009-03-03 09:56:57
|
Revision: 1106
http://armadeus.svn.sourceforge.net/armadeus/?rev=1106&view=rev
Author: FabM
Date: 2009-03-03 09:56:47 +0000 (Tue, 03 Mar 2009)
Log Message:
-----------
[FIRMWARE] Cleanup wishbone_example directory
Modified Paths:
--------------
trunk/firmware/wishbone_example/README
trunk/firmware/wishbone_example/src/intercon.vhd
trunk/firmware/wishbone_example/src/wishbone/imx_wrapper.vhd
trunk/firmware/wishbone_example/src/wishbone/irq_mngr.vhd
trunk/firmware/wishbone_example/src/wishbone/syscon.vhd
Added Paths:
-----------
trunk/firmware/wishbone_example/src/wb_button.vhd
trunk/firmware/wishbone_example/src/wb_led.ucf
trunk/firmware/wishbone_example/src/wb_led.vhd
trunk/firmware/wishbone_example/src/wb_top.vhd
trunk/firmware/wishbone_example/testbench/wb_top_tb.vhd
Removed Paths:
-------------
trunk/firmware/wishbone_example/src/Wb_button.vhd
trunk/firmware/wishbone_example/src/Wb_led.ucf
trunk/firmware/wishbone_example/src/Wb_led.vhd
trunk/firmware/wishbone_example/src/Wb_top.vhd
trunk/firmware/wishbone_example/testbench/Wb_top_tb.vhd
Modified: trunk/firmware/wishbone_example/README
===================================================================
--- trunk/firmware/wishbone_example/README 2009-03-02 16:14:50 UTC (rev 1105)
+++ trunk/firmware/wishbone_example/README 2009-03-03 09:56:47 UTC (rev 1106)
@@ -1,22 +1,22 @@
This project is an exemple for wishbone interface . There are three Wb slaves :
* irq_mngr : this slave joins irq from others wishbone IP and
- send it to i.mx processor.To manage these irq
- two registers are available :
- irq_mask ( addr : 0x0000) : enable irq writing 1
- irq_pend/irq_ack (addr : 0x0002) : writing 1 acknowledge irq
- and reading 1 inform that an irq pending.
- This design use one irq for button push and release.
+ send it to i.mx processor.To manage these irq
+ two registers are available :
+ irq_mask ( addr : 0x0000) : enable irq writing 1
+ irq_pend/irq_ack (addr : 0x0002) : writing 1 acknowledge irq
+ and reading 1 inform that an irq pending.
+ This design use one irq for button push and release.
-* Wb_led : a simple led register, one led is branched on register LSB.
- To switch on led write '0' on led register. Address register
- is :
- LED (addr : 0x0004)
-* Wb_button: Simple button register, when button is pressed, register LSB
- is '0', and when it's release LSB is '1'. On each switching
- an interuption is send to irq_mngr.
- button (addr : 0x0008)
+* wb_led : a simple led register, one led is branched on register LSB.
+ To switch on led write '0' on led register. Address register
+ is :
+ LED (addr : 0x0004) : on/off led
+* wb_button: Simple button register, when button is pressed, register LSB
+ is '0', and when it's release LSB is '1'. On each switching
+ an interuption is send to irq_mngr. Address register is :
+ button (addr : 0x0008) : read pressed value
see
-http://www.armadeus.com/wiki/index.php?title=FpgaArchitecture#La_composition_du_syst.C3.A8me_Wishbone
-(french) for more information about designing wishbone IP.
+http://www.armadeus.com/wiki/index.php?title=A_simple_design_with_Wishbone_bus
+for more informations about this design.
Deleted: trunk/firmware/wishbone_example/src/Wb_button.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/Wb_button.vhd 2009-03-02 16:14:50 UTC (rev 1105)
+++ trunk/firmware/wishbone_example/src/Wb_button.vhd 2009-03-03 09:56:47 UTC (rev 1106)
@@ -1,102 +0,0 @@
----------------------------------------------------------------------------
--- Company : ARMades Systems
--- Author(s) : Fabien Marteau <fab...@ar...>
---
--- Creation Date : 10/03/2008
--- File : Wb_button.vhd
---
--- Abstract :
---
------------------------------------------------------------------------------------
--- This program is free software; you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation; either version 2, or (at your option)
--- any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program; if not, write to the Free Software
--- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.all;
-
----------------------------------------------------------------------------
-Entity Wb_button is
----------------------------------------------------------------------------
- port
- (
- -- global signals
- gls_reset : in std_logic ;
- gls_clk : in std_logic ;
- -- Wishbone signals
--- wbs_writedata : in std_logic_vector( 15 downto 0);
- wbs_readdata : out std_logic_vector( 15 downto 0);
- wbs_strobe : in std_logic ;
- wbs_write : in std_logic ;
- wbs_ack : out std_logic;
- -- irq
- wbs_irq_s : out std_logic ;
- -- fpga input
- button : in std_logic
- );
-end entity;
-
-
----------------------------------------------------------------------------
-Architecture Wb_button_1 of Wb_button is
- ---------------------------------------------------------------------------
- signal button_r : std_logic ;
- signal reg : std_logic_vector( 15 downto 0);
-begin
-
- -- connect button
- cbutton : process(gls_clk,gls_reset)
- begin
- if gls_reset = '1' then
- reg <= (others => '0');
- elsif rising_edge(gls_clk) then
- reg <= "000000000000000"&button;
- end if;
- end process cbutton;
-
-
- -- rise interruption
- pbutton : process(gls_clk,gls_reset)
- begin
- if gls_reset = '1' then
- wbs_irq_s <= '0';
- button_r <= '0';
- elsif rising_edge(gls_clk) then
- if button_r /= button then
- wbs_irq_s <= '1';
- else
- wbs_irq_s <= '0';
- end if;
- button_r <= button;
- end if;
- end process pbutton;
-
- -- register reading process
- pread : process(gls_clk,gls_reset)
- begin
- if(gls_reset = '1') then
- wbs_ack <= '0';
- wbs_readdata <= (others => '0');
- elsif(falling_edge(gls_clk)) then
- wbs_ack <= '1';
- if(wbs_strobe = '1' and wbs_write = '0')then
- wbs_readdata <= reg;
- end if;
- end if;
- end process pread;
-
-end architecture Wb_button_1;
-
Deleted: trunk/firmware/wishbone_example/src/Wb_led.ucf
===================================================================
--- trunk/firmware/wishbone_example/src/Wb_led.ucf 2009-03-02 16:14:50 UTC (rev 1105)
+++ trunk/firmware/wishbone_example/src/Wb_led.ucf 2009-03-03 09:56:47 UTC (rev 1106)
@@ -1,60 +0,0 @@
-
-
-# Clock at 96MHzi
-NET "clk" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
-NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 10.42 ns HIGH 50 %;
-
-# IMX controls
-NET "imx_cs_n" LOC = "P59" | IOSTANDARD = LVCMOS33;
-NET "imx_eb3_n" LOC = "P60" | IOSTANDARD = LVCMOS33;
-NET "imx_oe_n" LOC = "P63" | IOSTANDARD = LVCMOS33;
-
-# IMX interruption
-NET "imx_irq" LOC = "P68" | IOSTANDARD = LVCMOS33;
-
-# IMX address bus
-NET "imx_addr<1>" LOC = "P23" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<2>" LOC = "P24" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<3>" LOC = "P25" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<4>" LOC = "P26" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<5>" LOC = "P27" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<6>" LOC = "P28" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<7>" LOC = "P30" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<8>" LOC = "P31" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<9>" LOC = "P32" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<10>" LOC = "P33" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<11>" LOC = "P35" | IOSTANDARD = LVCMOS33;
-NET "imx_addr<12>" LOC = "P36" | IOSTANDARD = LVCMOS33;
-
-# IMX data bus
-NET "imx_data<0>" LOC = "P1" | IOSTANDARD = LVCMOS33;
-NET "imx_data<1>" LOC = "P2" | IOSTANDARD = LVCMOS33;
-NET "imx_data<2>" LOC = "P4" | IOSTANDARD = LVCMOS33;
-NET "imx_data<3>" LOC = "P5" | IOSTANDARD = LVCMOS33;
-NET "imx_data<4>" LOC = "P6" | IOSTANDARD = LVCMOS33;
-NET "imx_data<5>" LOC = "P7" | IOSTANDARD = LVCMOS33;
-NET "imx_data<6>" LOC = "P8" | IOSTANDARD = LVCMOS33;
-NET "imx_data<7>" LOC = "P10" | IOSTANDARD = LVCMOS33;
-NET "imx_data<8>" LOC = "P11" | IOSTANDARD = LVCMOS33;
-NET "imx_data<9>" LOC = "P12" | IOSTANDARD = LVCMOS33;
-NET "imx_data<10>" LOC = "P13" | IOSTANDARD = LVCMOS33;
-NET "imx_data<11>" LOC = "P14" | IOSTANDARD = LVCMOS33;
-NET "imx_data<12>" LOC = "P15" | IOSTANDARD = LVCMOS33;
-NET "imx_data<13>" LOC = "P17" | IOSTANDARD = LVCMOS33;
-NET "imx_data<14>" LOC = "P18" | IOSTANDARD = LVCMOS33;
-NET "imx_data<15>" LOC = "P20" | IOSTANDARD = LVCMOS33;
-
-###############################################
-# fpga specific
-###############################################
-
-# led output
-NET "LED" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
-# Button input
-NET "button" LOC = "P141" | IOSTANDARD = LVCMOS33 ;
-
-# Test (X10 on devfull) connection
-#NET "imx_data0_test" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
-#NET "imx_addr1_test" LOC = "P97" | IOSTANDARD = LVCMOS33 ;
-
Deleted: trunk/firmware/wishbone_example/src/Wb_led.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/Wb_led.vhd 2009-03-02 16:14:50 UTC (rev 1105)
+++ trunk/firmware/wishbone_example/src/Wb_led.vhd 2009-03-03 09:56:47 UTC (rev 1106)
@@ -1,78 +0,0 @@
----------------------------------------------------------------------------
--- Company : ARMadeus Systems
--- Author(s) : Fabien Marteau
---
--- Creation Date : 05/03/2008
--- File : Wb_led.vhd
---
--- Abstract : drive one led with Wishbone bus
---
-------------------------------------------------------------------------------------
--- This program is free software; you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation; either version 2, or (at your option)
--- any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program; if not, write to the Free Software
--- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.all;
-
------------------------------------------------------------------------
- Entity Wb_led is
------------------------------------------------------------------------
- port
- (
- -- Syscon signals
- gls_reset : in std_logic ;
- gls_clk : in std_logic ;
- -- Wishbone signals
- wbs_writedata : in std_logic_vector( 15 downto 0);
- wbs_readdata : out std_logic_vector( 15 downto 0);
- wbs_strobe : in std_logic ;
- wbs_write : in std_logic ;
- wbs_ack : out std_logic;
- -- out signals
- LED : out std_logic
- );
-end entity;
-
-
------------------------------------------------------------------------
-Architecture Wb_led_1 of Wb_led is
------------------------------------------------------------------------
- signal reg : std_logic_vector( 15 downto 0);
-begin
-
--- connect led
-LED <= reg(0);
-
--- manage register
-reg_bloc : process(gls_clk,gls_reset)
-begin
- if gls_reset = '1' then
- reg <= (others => '0');
- elsif rising_edge(gls_clk) then
- if ((wbs_strobe and wbs_write) = '1' ) then
- reg <= wbs_writedata;
- else
- reg <= reg;
- end if;
- end if;
-
-end process reg_bloc;
-
-wbs_ack <= wbs_strobe;
-wbs_readdata <= reg;
-
-end architecture Wb_led_1;
-
Deleted: trunk/firmware/wishbone_example/src/Wb_top.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/Wb_top.vhd 2009-03-02 16:14:50 UTC (rev 1105)
+++ trunk/firmware/wishbone_example/src/Wb_top.vhd 2009-03-03 09:56:47 UTC (rev 1106)
@@ -1,386 +0,0 @@
----------------------------------------------------------------------------
--- Company : ARMadeus Systems
--- Author(s) : Fabien Marteau (fab...@ar...)
---
--- Creation Date : 05/03/2008
--- File : Wb_top.vhd
---
--- Abstract :
---
------------------------------------------------------------------------------------
--- This program is free software; you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation; either version 2, or (at your option)
--- any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program; if not, write to the Free Software
--- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-----------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.numeric_std.all;
-
----------------------------------------------------------------------------
-Entity Wb_top is
----------------------------------------------------------------------------
-port
-(
- -- imx EIM connexion
- imx_addr : in std_logic_vector( 12 downto 0);
- imx_data : inout std_logic_vector( 15 downto 0);
- imx_cs_n : in std_logic;
- imx_eb3_n : in std_logic ;
- imx_oe_n : in std_logic ;
- -- clock
- clk : in std_logic ;
- -- fpga specific
- LED : out std_logic;
- button : in std_logic ;
-
- -- irq
- imx_irq : out std_logic
-
-);
-end entity;
-
-
----------------------------------------------------------------------------
-Architecture Wb_top_1 of Wb_top is
----------------------------------------------------------------------------
- component imx_wrapper
- port (
- -- i.MX Signals
- imx_address : in std_logic_vector(12 downto 1);
- imx_data : inout std_logic_vector(15 downto 0);
- imx_cs_n : in std_logic;
- imx_oe_n : in std_logic;
- imx_eb3_n : in std_logic;
-
- -- Global Signals
- gls_reset : in std_logic;
- gls_clk : in std_logic;
-
- -- Wishbone interface signals
- wbm_address : out std_logic_vector(12 downto 0); -- Address bus
- wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
- wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
- wbm_strobe : out std_logic; -- Data Strobe
- wbm_write : out std_logic; -- Write access
- wbm_sel : out std_logic_vector(1 downto 0); -- select LSB or/and MSB byte
- wbm_ack : in std_logic ;
- wbm_cycle : out std_logic -- bus cycle in progress
- );
- end component;
-
- component syscon
- port(
- -- external signals
- ext_clk : in std_logic ;
- ext_reset : in std_logic ;
- --internal signals
- gls_clk : out std_logic ;
- gls_reset : out std_logic
- );
- end component;
-
- component intercon
- port (
- -- imx wishbone master connexion
- gls_reset_m1 : out std_logic ;
- gls_clk_m1 : out std_logic ;
-
- wbm_address_m1 : in std_logic_vector( 12 downto 0);
- wbm_readdata_m1 : out std_logic_vector( 15 downto 0);
- wbm_writedata_m1 : in std_logic_vector( 15 downto 0);
- wbm_strobe_m1 : in std_logic ;
- wbm_write_m1 : in std_logic ;
- wbm_sel_m1 : in std_logic_vector( 1 downto 0);
- wbm_ack_m1 : out std_logic ;
- wbm_cycle_m1 : in std_logic ;
-
- -- led wishbone slave connexion
- gls_reset_s1 : out std_logic ;
- gls_clk_s1 : out std_logic ;
- wbs_writedata_s1 : out std_logic_vector( 15 downto 0);
- wbs_readdata_s1 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s1 : out std_logic ;
- wbs_write_s1 : out std_logic ;
- wbs_ack_s1 : in std_logic ;
-
- -- button slave connexion
- gls_reset_s2 : out std_logic ;
- gls_clk_s2 : out std_logic ;
--- wbs_writedata_s2 : out std_logic_vector( 15 downto 0);
- wbs_readdata_s2 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s2 : out std_logic ;
- wbs_write_s2 : out std_logic ;
- wbs_ack_s2 : in std_logic ;
-
- wbs_irq_s2 : in std_logic ;
-
- -- irq slave connexion
- gls_reset_s3 : out std_logic ;
- gls_clk_s3 : out std_logic ;
- wbs_address_s3 : out std_logic ;
- wbs_writedata_s3 : out std_logic_vector( 15 downto 0);
- wbs_readdata_s3 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s3 : out std_logic ;
- wbs_write_s3 : out std_logic ;
- wbs_ack_s3 : in std_logic ;
- wbs_irq_s3 : out std_logic;
-
- -- syscon connection
- gls_reset_sys : in std_logic ;
- gls_clk_sys : in std_logic
- );
- end component intercon;
-
- component Wb_led
- port(
- -- Syscon signals
- gls_reset : in std_logic ;
- gls_clk : in std_logic ;
- -- Wishbone signals
- wbs_writedata : in std_logic_vector( 15 downto 0);
- wbs_readdata : out std_logic_vector( 15 downto 0);
- wbs_strobe : in std_logic ;
- wbs_write : in std_logic ;
- wbs_ack : out std_logic;
- -- out signals
- LED : out std_logic
- );
- end component;
-
- component Wb_button
- port (
- -- global signals
- gls_reset : in std_logic ;
- gls_clk : in std_logic ;
--- wbs_writedata : in std_logic_vector( 15 downto 0);
- wbs_readdata : out std_logic_vector( 15 downto 0);
- wbs_strobe : in std_logic ;
- wbs_write : in std_logic ;
- wbs_ack : out std_logic ;
-
- -- irq
- wbs_irq_s : out std_logic ;
-
- -- fpga input
- button : in std_logic
- );
- end component;
-
- component irq_mngr
- generic
- (
- irq_count : integer := 1;
- irq_level : std_logic := '1'
- );
- port (
- -- Global Signals
- gls_clk : in std_logic;
- gls_reset : in std_logic;
-
- -- Wishbone interface signals
- wbs_s1_address : in std_logic; -- Address bus
- wbs_s1_readdata : out std_logic_vector(15 downto 0); -- Data bus for read access
- wbs_s1_writedata : in std_logic_vector(15 downto 0); -- Data bus for write access
- wbs_s1_ack : out std_logic; -- Access acknowledge
- wbs_s1_strobe : in std_logic; -- Data Strobe
- wbs_s1_write : in std_logic; -- Write access
- -- irq from other IP
- wbs_s1_irq : in std_logic_vector(irq_count-1 downto 0);
-
- -- Component external signals
- gls_irq : out std_logic -- IRQ request
- );
- end component irq_mngr;
-
- -- irq_mngr connection signal
- signal gls_clk_s3 : std_logic ;
- signal gls_reset_s3 : std_logic ;
- signal wbs_address_s3 : std_logic ;
- signal wbs_readdata_s3 : std_logic_vector(15 downto 0);
- signal wbs_writedata_s3: std_logic_vector( 15 downto 0);
- signal wbs_ack_s3 : std_logic ;
- signal wbs_strobe_s3 : std_logic ;
- signal wbs_write_s3 : std_logic ;
- signal wbs_irq_s3 : std_logic;
-
- -- button connection signal
- signal gls_reset_s2 : std_logic ;
- signal gls_clk_s2 : std_logic ;
- signal wbs_readdata_s2 : std_logic_vector(15 downto 0);
---signal wbs_writedata_s2: std_logic_vector( 15 downto 0);
- signal wbs_ack_s2 : std_logic ;
- signal wbs_strobe_s2 : std_logic ;
- signal wbs_write_s2 : std_logic ;
-
- signal wbs_irq_s2 : std_logic ;
-
- -- imx_wrapper connection signals
- signal gls_reset_m1 : std_logic ;
- Signal gls_clk_m1 : std_logic ;
- signal wbm_address_m1 : std_logic_vector( 12 downto 0);
- Signal wbm_readdata_m1 : std_logic_vector( 15 downto 0);
- Signal wbm_writedata_m1 : std_logic_vector( 15 downto 0);
- Signal wbm_strobe_m1 : std_logic ;
- signal wbm_write_m1 : std_logic ;
- Signal wbm_sel_m1 : std_logic_vector( 1 downto 0);
- signal wbm_ack_m1 : std_logic ;
- Signal wbm_cycle_m1 : std_logic ;
-
- -- led connection signals
- Signal gls_reset_s1 : std_logic ;
- Signal gls_clk_s1 : std_logic ;
- Signal wbs_writedata_s1 : std_logic_vector( 15 downto 0);
- Signal wbs_readdata_s1 : std_logic_vector( 15 downto 0);
- Signal wbs_strobe_s1 : std_logic ;
- Signal wbs_write_s1 : std_logic ;
- Signal wbs_ack_s1 : std_logic ;
-
- -- syscon connection signals
- Signal gls_reset_sys : std_logic ;
- Signal gls_clk_sys : std_logic ;
-
-
-begin
-
- connect_imx_wrapper : imx_wrapper
- port map (
- imx_address => imx_addr(12 downto 1),
- imx_data => imx_data,
- imx_cs_n => imx_cs_n,
- imx_oe_n => imx_oe_n,
- imx_eb3_n => imx_eb3_n,
-
- gls_reset => gls_reset_m1,
- gls_clk => gls_clk_m1,
-
- wbm_address => wbm_address_m1,
- wbm_readdata => wbm_readdata_m1,
- wbm_writedata => wbm_writedata_m1,
- wbm_strobe => wbm_strobe_m1,
- wbm_write => wbm_write_m1,
- wbm_sel => wbm_sel_m1,
- wbm_ack => wbm_ack_m1,
- wbm_cycle => wbm_cycle_m1
- );
-
- connect_Wb_led : Wb_led
- port map (
- gls_reset => gls_reset_s1,
- gls_clk => gls_clk_s1,
-
- wbs_writedata => wbs_writedata_s1,
- wbs_readdata => wbs_readdata_s1,
- wbs_strobe => wbs_strobe_s1,
- wbs_write => wbs_write_s1,
- wbs_ack => wbs_ack_s1,
-
- LED => LED
- );
-
- connect_syscon : syscon
- port map (
- ext_clk => clk,
- ext_reset => '0',
-
- gls_clk => gls_clk_sys,
- gls_reset => gls_reset_sys
- );
-
- connect_intercon : intercon
- port map (
- -- imx_wrapper connexion
- gls_reset_m1 => gls_reset_m1,
- gls_clk_m1 => gls_clk_m1,
- wbm_address_m1 => wbm_address_m1,
- wbm_readdata_m1 => wbm_readdata_m1,
- wbm_writedata_m1 => wbm_writedata_m1,
- wbm_strobe_m1 => wbm_strobe_m1,
- wbm_write_m1 => wbm_write_m1,
- wbm_sel_m1 => wbm_sel_m1,
- wbm_ack_m1 => wbm_ack_m1,
- wbm_cycle_m1 => wbm_cycle_m1,
- -- led connexion
- gls_reset_s1 => gls_reset_s1,
- gls_clk_s1 => gls_clk_s1,
- wbs_writedata_s1 => wbs_writedata_s1,
- wbs_readdata_s1 => wbs_readdata_s1,
- wbs_strobe_s1 => wbs_strobe_s1,
- wbs_write_s1 => wbs_write_s1,
- wbs_ack_s1 => wbs_ack_s1,
- -- button connexion
- gls_reset_s2 => gls_reset_s2,
- gls_clk_s2 => gls_clk_s2,
--- wbs_writedata_s2 => wbs_writedata_s2,
- wbs_readdata_s2 => wbs_readdata_s2,
- wbs_strobe_s2 => wbs_strobe_s2,
- wbs_write_s2 => wbs_write_s2,
- wbs_ack_s2 => wbs_ack_s2,
-
- wbs_irq_s2 => wbs_irq_s2,
- -- irq connexion
- gls_reset_s3 => gls_reset_s3,
- gls_clk_s3 => gls_clk_s3,
- wbs_address_s3 => wbs_address_s3,
- wbs_writedata_s3 => wbs_writedata_s3,
- wbs_readdata_s3 => wbs_readdata_s3,
- wbs_strobe_s3 => wbs_strobe_s3,
- wbs_write_s3 => wbs_write_s3,
- wbs_ack_s3 => wbs_ack_s3,
- wbs_irq_s3 => wbs_irq_s3,
- -- global signals
- gls_reset_sys => gls_reset_sys,
- gls_clk_sys => gls_clk_sys
- );
-
- connect_button : Wb_button
- port map (
- -- global signals
- gls_reset => gls_reset_s2,
- gls_clk => gls_clk_s2,
--- wbs_writedata => wbs_writedata_s2,
- wbs_readdata => wbs_readdata_s2,
- wbs_strobe => wbs_strobe_s2,
- wbs_write => wbs_write_s2,
- wbs_ack => wbs_ack_s2,
-
- -- irq
- wbs_irq_s => wbs_irq_s2,
-
- -- fpga input
- button => button
- );
-
- connect_irq_mngr : irq_mngr
- port map (
- -- Global Signals
- gls_clk => gls_clk_s3,
- gls_reset => gls_reset_s3,
-
- -- Wishbone interface signals
- wbs_s1_address => wbs_address_s3, -- Address bus
- wbs_s1_readdata => wbs_readdata_s3, -- Data bus for read access
- wbs_s1_writedata => wbs_writedata_s3, -- Data bus for write access
- wbs_s1_ack => wbs_ack_s3, -- Access acknowledge
- wbs_s1_strobe => wbs_strobe_s3, -- Data Strobe
- wbs_s1_write => wbs_write_s3, -- Write access
- -- irq from other IP
- wbs_s1_irq(0) => wbs_irq_s3,
-
- -- Component external signals
- gls_irq => imx_irq
- );
-
-end architecture Wb_top_1;
-
Modified: trunk/firmware/wishbone_example/src/intercon.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/intercon.vhd 2009-03-02 16:14:50 UTC (rev 1105)
+++ trunk/firmware/wishbone_example/src/intercon.vhd 2009-03-03 09:56:47 UTC (rev 1106)
@@ -32,134 +32,126 @@
---------------------------------------------------------------------------
Entity intercon is
---------------------------------------------------------------------------
- port
- (
- -- imx wishbone master connexion
- gls_reset_m1 : out std_logic ;
- gls_clk_m1 : out std_logic ;
+ port
+ (
+ -- imx wishbone master connexion
+ gls_reset_m1 : out std_logic ;
+ gls_clk_m1 : out std_logic ;
- wbm_address_m1 : in std_logic_vector( 12 downto 0);
- wbm_readdata_m1 : out std_logic_vector( 15 downto 0);
- wbm_writedata_m1 : in std_logic_vector( 15 downto 0);
- wbm_strobe_m1 : in std_logic ;
- wbm_write_m1 : in std_logic ;
- wbm_sel_m1 : in std_logic_vector( 1 downto 0);
- wbm_ack_m1 : out std_logic ;
- wbm_cycle_m1 : in std_logic ;
+ wbm_address_m1 : in std_logic_vector( 12 downto 0);
+ wbm_readdata_m1 : out std_logic_vector( 15 downto 0);
+ wbm_writedata_m1 : in std_logic_vector( 15 downto 0);
+ wbm_strobe_m1 : in std_logic ;
+ wbm_write_m1 : in std_logic ;
+ wbm_sel_m1 : in std_logic_vector( 1 downto 0);
+ wbm_ack_m1 : out std_logic ;
+ wbm_cycle_m1 : in std_logic ;
- -- led wishbone slave connexion
- gls_reset_s1 : out std_logic ;
- gls_clk_s1 : out std_logic ;
- wbs_writedata_s1 : out std_logic_vector( 15 downto 0);
- wbs_readdata_s1 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s1 : out std_logic ;
- wbs_write_s1 : out std_logic ;
- wbs_ack_s1 : in std_logic ;
+ -- led wishbone slave connexion
+ gls_reset_s1 : out std_logic ;
+ gls_clk_s1 : out std_logic ;
+ wbs_writedata_s1 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s1 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s1 : out std_logic ;
+ wbs_write_s1 : out std_logic ;
+ wbs_ack_s1 : in std_logic ;
- -- button slave connexion
- gls_reset_s2 : out std_logic ;
- gls_clk_s2 : out std_logic ;
- wbs_readdata_s2 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s2 : out std_logic ;
- wbs_write_s2 : out std_logic ;
- wbs_ack_s2 : in std_logic ;
+ -- button slave connexion
+ gls_reset_s2 : out std_logic ;
+ gls_clk_s2 : out std_logic ;
+ wbs_readdata_s2 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s2 : out std_logic ;
+ wbs_write_s2 : out std_logic ;
+ wbs_ack_s2 : in std_logic ;
+ wbs_irq_s2 : in std_logic ;
- wbs_irq_s2 : in std_logic ;
+ -- irq slave connexion
+ gls_reset_s3 : out std_logic ;
+ gls_clk_s3 : out std_logic ;
+ wbs_address_s3 : out std_logic ;
+ wbs_writedata_s3 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s3 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s3 : out std_logic ;
+ wbs_write_s3 : out std_logic ;
+ wbs_ack_s3 : in std_logic ;
+ wbs_irq_s3 : out std_logic ;
- -- irq slave connexion
- gls_reset_s3 : out std_logic ;
- gls_clk_s3 : out std_logic ;
- wbs_address_s3 : out std_logic ;
- wbs_writedata_s3 : out std_logic_vector( 15 downto 0);
- wbs_readdata_s3 : in std_logic_vector( 15 downto 0);
- wbs_strobe_s3 : out std_logic ;
- wbs_write_s3 : out std_logic ;
- wbs_ack_s3 : in std_logic ;
- wbs_irq_s3 : out std_logic ;
-
- -- syscon connection
- gls_reset_sys : in std_logic ;
- gls_clk_sys : in std_logic
- );
+ -- syscon connection
+ gls_reset_sys : in std_logic ;
+ gls_clk_sys : in std_logic
+ );
end entity;
---------------------------------------------------------------------------
Architecture intercon_1 of intercon is
---------------------------------------------------------------------------
- signal led_cs : std_logic ;
- signal button_cs : std_logic ;
- signal irq_cs : std_logic ;
- signal cs :std_logic_vector( 2 downto 0);
+ signal led_cs : std_logic ;
+ signal button_cs : std_logic ;
+ signal irq_cs : std_logic ;
+ signal cs :std_logic_vector( 2 downto 0);
begin
- -- clock and reset management
- gls_reset_s1 <= gls_reset_sys;
- gls_clk_s1 <= gls_clk_sys;
+ -- clock and reset management
+ gls_reset_s1 <= gls_reset_sys;
+ gls_clk_s1 <= gls_clk_sys;
- gls_reset_s2 <= gls_reset_sys;
- gls_clk_s2 <= gls_clk_sys;
+ gls_reset_s2 <= gls_reset_sys;
+ gls_clk_s2 <= gls_clk_sys;
- gls_reset_s3 <= gls_reset_sys;
- gls_clk_s3 <= gls_clk_sys;
+ gls_reset_s3 <= gls_reset_sys;
+ gls_clk_s3 <= gls_clk_sys;
- gls_reset_m1 <= gls_reset_sys;
- gls_clk_m1 <= gls_clk_sys;
+ gls_reset_m1 <= gls_reset_sys;
+ gls_clk_m1 <= gls_clk_sys;
- -----------------------------
- -- master => slave connexions
- -----------------------------
- -- address decode
- irq_cs <= '1' when wbm_address_m1 = "0000000000000" or wbm_address_m1 = "0000000000010"
- else '0';
- led_cs <= '1' when wbm_address_m1 = "0000000000100"
- else '0';
- button_cs <= '1' when wbm_address_m1 = "0000000001000"
- else '0';
+ -----------------------------
+ -- master => slave connexions
+ -----------------------------
+ -- address decode
+ irq_cs <= '1' when wbm_address_m1 = "0000000000000" or wbm_address_m1 = "0000000000010"
+ else '0';
+ led_cs <= '1' when wbm_address_m1 = "0000000000100"
+ else '0';
+ button_cs <= '1' when wbm_address_m1 = "0000000001000"
+ else '0';
- wbs_address_s3 <= wbm_address_m1(1);
+ wbs_address_s3 <= wbm_address_m1(1);
- -- control signals
- -- for led (s1)
- wbs_writedata_s1 <= wbm_writedata_m1 when (wbm_write_m1 and led_cs)='1'
- else (others => '0');
- wbs_strobe_s1 <= (wbm_strobe_m1 and led_cs);
- wbs_write_s1 <= (wbm_write_m1 and led_cs);
- -- for button(s2) read only
- wbs_strobe_s2 <= (wbm_strobe_m1 and button_cs);
- wbs_write_s2 <= '0';
+ -- control signals
+ -- for led (s1)
+ wbs_writedata_s1 <= wbm_writedata_m1 when (wbm_write_m1 and led_cs)='1'
+ else (others => '0');
+ wbs_strobe_s1 <= (wbm_strobe_m1 and led_cs);
+ wbs_write_s1 <= (wbm_write_m1 and led_cs);
+ -- for button(s2) read only
+ wbs_strobe_s2 <= (wbm_strobe_m1 and button_cs);
+ wbs_write_s2 <= '0';
- -- for irq (s3)
- wbs_writedata_s3 <= wbm_writedata_m1 when (wbm_write_m1 and irq_cs)='1'
- else (others => '0');
- wbs_strobe_s3 <= (wbm_strobe_m1 and irq_cs);
- wbs_write_s3 <= (wbm_write_m1 and irq_cs);
+ -- for irq (s3)
+ wbs_writedata_s3 <= wbm_writedata_m1 when (wbm_write_m1 and irq_cs)='1'
+ else (others => '0');
+ wbs_strobe_s3 <= (wbm_strobe_m1 and irq_cs);
+ wbs_write_s3 <= (wbm_write_m1 and irq_cs);
- -----------------------------
- -- slave => master connexions
- -----------------------------
- cs(0) <= led_cs;
- cs(1) <= button_cs;
- cs(2) <= irq_cs;
+ -----------------------------
+ -- slave => master connexions
+ -----------------------------
+ cs(0) <= led_cs;
+ cs(1) <= button_cs;
+ cs(2) <= irq_cs;
- with cs select
- wbm_readdata_m1 <= wbs_readdata_s1 when "001",
- wbs_readdata_s2 when "010",
- wbs_readdata_s3 when "100",
- (others => '0') when others;
- with cs select
- wbm_ack_m1 <= wbs_ack_s1 when "001",
- wbs_ack_s2 when "010",
- wbs_ack_s3 when "100",
- '0' when others;
+ with cs select
+ wbm_readdata_m1 <= wbs_readdata_s1 when "001",
+ wbs_readdata_s2 when "010",
+ wbs_readdata_s3 when "100",
+ (others => '0') when others;
+ with cs select
+ wbm_ack_m1 <= wbs_ack_s1 when "001",
+ wbs_ack_s2 when "010",
+ wbs_ack_s3 when "100",
+ '0' when others;
+ -- irq management
+ wbs_irq_s3 <= wbs_irq_s2;
- -- irq management
- wbs_irq_s3 <= wbs_irq_s2;
-
- -- open connexion
--- wbm_sel_m1 => open;
--- wbm_cycle_m1 => open;
--- wbs_ack_s1 => open;
-
end architecture intercon_1;
-
Copied: trunk/firmware/wishbone_example/src/wb_button.vhd (from rev 1105, trunk/firmware/wishbone_example/src/Wb_button.vhd)
===================================================================
--- trunk/firmware/wishbone_example/src/wb_button.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/wb_button.vhd 2009-03-03 09:56:47 UTC (rev 1106)
@@ -0,0 +1,101 @@
+---------------------------------------------------------------------------
+-- Company : ARMades Systems
+-- Author(s) : Fabien Marteau <fab...@ar...>
+--
+-- Creation Date : 10/03/2008
+-- File : wb_button.vhd
+--
+-- Abstract :
+--
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity wb_button is
+---------------------------------------------------------------------------
+ port
+ (
+ -- global signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ -- Wishbone signals
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- irq
+ wbs_irq_s : out std_logic ;
+ -- fpga input
+ button : in std_logic
+ );
+end entity;
+
+
+---------------------------------------------------------------------------
+Architecture wb_button_1 of wb_button is
+ ---------------------------------------------------------------------------
+ signal button_r : std_logic ;
+ signal reg : std_logic_vector( 15 downto 0);
+begin
+
+ -- connect button
+ cbutton : process(gls_clk,gls_reset)
+ begin
+ if gls_reset = '1' then
+ reg <= (others => '0');
+ elsif rising_edge(gls_clk) then
+ reg <= "000000000000000"&button;
+ end if;
+ end process cbutton;
+
+
+ -- rise interruption
+ pbutton : process(gls_clk,gls_reset)
+ begin
+ if gls_reset = '1' then
+ wbs_irq_s <= '0';
+ button_r <= '0';
+ elsif rising_edge(gls_clk) then
+ if button_r /= button then
+ wbs_irq_s <= '1';
+ else
+ wbs_irq_s <= '0';
+ end if;
+ button_r <= button;
+ end if;
+ end process pbutton;
+
+ -- register reading process
+ pread : process(gls_clk,gls_reset)
+ begin
+ if(gls_reset = '1') then
+ wbs_ack <= '0';
+ wbs_readdata <= (others => '0');
+ elsif(falling_edge(gls_clk)) then
+ wbs_ack <= '1';
+ if(wbs_strobe = '1' and wbs_write = '0')then
+ wbs_readdata <= reg;
+ end if;
+ end if;
+ end process pread;
+
+end architecture wb_button_1;
+
Copied: trunk/firmware/wishbone_example/src/wb_led.ucf (from rev 1105, trunk/firmware/wishbone_example/src/Wb_led.ucf)
===================================================================
--- trunk/firmware/wishbone_example/src/wb_led.ucf (rev 0)
+++ trunk/firmware/wishbone_example/src/wb_led.ucf 2009-03-03 09:56:47 UTC (rev 1106)
@@ -0,0 +1,59 @@
+
+# Clock at 96MHzi
+NET "clk" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 10.42 ns HIGH 50 %;
+
+# IMX controls
+NET "imx_cs_n" LOC = "P59" | IOSTANDARD = LVCMOS33;
+NET "imx_eb3_n" LOC = "P60" | IOSTANDARD = LVCMOS33;
+NET "imx_oe_n" LOC = "P63" | IOSTANDARD = LVCMOS33;
+
+# IMX interruption
+NET "imx_irq" LOC = "P68" | IOSTANDARD = LVCMOS33;
+
+# IMX address bus
+NET "imx_addr<1>" LOC = "P23" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<2>" LOC = "P24" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<3>" LOC = "P25" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<4>" LOC = "P26" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<5>" LOC = "P27" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<6>" LOC = "P28" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<7>" LOC = "P30" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<8>" LOC = "P31" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<9>" LOC = "P32" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<10>" LOC = "P33" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<11>" LOC = "P35" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<12>" LOC = "P36" | IOSTANDARD = LVCMOS33;
+
+# IMX data bus
+NET "imx_data<0>" LOC = "P1" | IOSTANDARD = LVCMOS33;
+NET "imx_data<1>" LOC = "P2" | IOSTANDARD = LVCMOS33;
+NET "imx_data<2>" LOC = "P4" | IOSTANDARD = LVCMOS33;
+NET "imx_data<3>" LOC = "P5" | IOSTANDARD = LVCMOS33;
+NET "imx_data<4>" LOC = "P6" | IOSTANDARD = LVCMOS33;
+NET "imx_data<5>" LOC = "P7" | IOSTANDARD = LVCMOS33;
+NET "imx_data<6>" LOC = "P8" | IOSTANDARD = LVCMOS33;
+NET "imx_data<7>" LOC = "P10" | IOSTANDARD = LVCMOS33;
+NET "imx_data<8>" LOC = "P11" | IOSTANDARD = LVCMOS33;
+NET "imx_data<9>" LOC = "P12" | IOSTANDARD = LVCMOS33;
+NET "imx_data<10>" LOC = "P13" | IOSTANDARD = LVCMOS33;
+NET "imx_data<11>" LOC = "P14" | IOSTANDARD = LVCMOS33;
+NET "imx_data<12>" LOC = "P15" | IOSTANDARD = LVCMOS33;
+NET "imx_data<13>" LOC = "P17" | IOSTANDARD = LVCMOS33;
+NET "imx_data<14>" LOC = "P18" | IOSTANDARD = LVCMOS33;
+NET "imx_data<15>" LOC = "P20" | IOSTANDARD = LVCMOS33;
+
+###############################################
+# fpga specific
+###############################################
+
+# led output
+NET "LED" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
+# Button input
+NET "button" LOC = "P141" | IOSTANDARD = LVCMOS33 ;
+
+# Test (X10 on devfull) connection
+#NET "imx_data0_test" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
+#NET "imx_addr1_test" LOC = "P97" | IOSTANDARD = LVCMOS33 ;
+
Copied: trunk/firmware/wishbone_example/src/wb_led.vhd (from rev 1105, trunk/firmware/wishbone_example/src/Wb_led.vhd)
===================================================================
--- trunk/firmware/wishbone_example/src/wb_led.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/wb_led.vhd 2009-03-03 09:56:47 UTC (rev 1106)
@@ -0,0 +1,78 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 05/03/2008
+-- File : wb_led.vhd
+--
+-- Abstract : drive one led with Wishbone bus
+--
+------------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-----------------------------------------------------------------------
+ Entity wb_led is
+-----------------------------------------------------------------------
+ port
+ (
+ -- Syscon signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ -- Wishbone signals
+ wbs_writedata : in std_logic_vector( 15 downto 0);
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- out signals
+ LED : out std_logic
+ );
+end entity;
+
+
+-----------------------------------------------------------------------
+Architecture wb_led_1 of wb_led is
+-----------------------------------------------------------------------
+ signal reg : std_logic_vector( 15 downto 0);
+begin
+
+ -- connect led
+ LED <= reg(0);
+
+ -- manage register
+ reg_bloc : process(gls_clk,gls_reset)
+ begin
+ if gls_reset = '1' then
+ reg <= (others => '0');
+ elsif rising_edge(gls_clk) then
+ if ((wbs_strobe and wbs_write) = '1' ) then
+ reg <= wbs_writedata;
+ else
+ reg <= reg;
+ end if;
+ end if;
+
+ end process reg_bloc;
+
+ wbs_ack <= wbs_strobe;
+ wbs_readdata <= reg;
+
+end architecture wb_led_1;
+
Copied: trunk/firmware/wishbone_example/src/wb_top.vhd (from rev 1105, trunk/firmware/wishbone_example/src/Wb_top.vhd)
===================================================================
--- trunk/firmware/wishbone_example/src/wb_top.vhd (rev 0)
+++ trunk/firmware/wishbone_example/src/wb_top.vhd 2009-03-03 09:56:47 UTC (rev 1106)
@@ -0,0 +1,368 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau (fab...@ar...)
+--
+-- Creation Date : 05/03/2008
+-- File : Wb_top.vhd
+--
+-- Abstract :
+--
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity wb_top is
+---------------------------------------------------------------------------
+port
+(
+ -- imx EIM connexion
+ imx_addr : in std_logic_vector( 12 downto 0);
+ imx_data : inout std_logic_vector( 15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ -- clock
+ clk : in std_logic ;
+ -- fpga specific
+ LED : out std_logic;
+ button : in std_logic ;
+ -- irq
+ imx_irq : out std_logic
+);
+end entity;
+
+
+---------------------------------------------------------------------------
+architecture wb_top_1 of wb_top is
+---------------------------------------------------------------------------
+ component imx_wrapper
+ port (
+ -- i.MX Signals
+ imx_address : in std_logic_vector(12 downto 1);
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_oe_n : in std_logic;
+ imx_eb3_n : in std_logic;
+
+ -- Global Signals
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
+
+ -- Wishbone interface signals
+ wbm_address : out std_logic_vector(12 downto 0); -- Address bus
+ wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
+ wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
+ wbm_strobe : out std_logic; -- Data Strobe
+ wbm_write : out std_logic; -- Write access
+ wbm_sel : out std_logic_vector(1 downto 0); -- select LSB or/and MSB byte
+ wbm_ack : in std_logic ;
+ wbm_cycle : out std_logic -- bus cycle in progress
+ );
+ end component;
+
+ component syscon
+ port(
+ -- external signals
+ ext_clk : in std_logic ;
+ ext_reset : in std_logic ;
+ --internal signals
+ gls_clk : out std_logic ;
+ gls_reset : out std_logic
+ );
+ end component;
+
+ component intercon
+ port (
+ -- imx wishbone master connexion
+ gls_reset_m1 : out std_logic ;
+ gls_clk_m1 : out std_logic ;
+
+ wbm_address_m1 : in std_logic_vector( 12 downto 0);
+ wbm_readdata_m1 : out std_logic_vector( 15 downto 0);
+ wbm_writedata_m1 : in std_logic_vector( 15 downto 0);
+ wbm_strobe_m1 : in std_logic ;
+ wbm_write_m1 : in std_logic ;
+ wbm_sel_m1 : in std_logic_vector( 1 downto 0);
+ wbm_ack_m1 : out std_logic ;
+ wbm_cycle_m1 : in std_logic ;
+
+ -- led wishbone slave connexion
+ gls_reset_s1 : out std_logic ;
+ gls_clk_s1 : out std_logic ;
+ wbs_writedata_s1 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s1 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s1 : out std_logic ;
+ wbs_write_s1 : out std_logic ;
+ wbs_ack_s1 : in std_logic ;
+
+ -- button slave connexion
+ gls_reset_s2 : out std_logic ;
+ gls_clk_s2 : out std_logic ;
+ wbs_readdata_s2 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s2 : out std_logic ;
+ wbs_write_s2 : out std_logic ;
+ wbs_ack_s2 : in std_logic ;
+
+ wbs_irq_s2 : in std_logic ;
+
+ -- irq slave connexion
+ gls_reset_s3 : out std_logic ;
+ gls_clk_s3 : out std_logic ;
+ wbs_address_s3 : out std_logic ;
+ wbs_writedata_s3 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s3 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s3 : out std_logic ;
+ wbs_write_s3 : out std_logic ;
+ wbs_ack_s3 : in std_logic ;
+ wbs_irq_s3 : out std_logic;
+
+ -- syscon connection
+ gls_reset_sys : in std_logic ;
+ gls_clk_sys : in std_logic
+ );
+ end component intercon;
+
+ component wb_led
+ port(
+ -- Syscon signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ -- Wishbone signals
+ wbs_writedata : in std_logic_vector( 15 downto 0);
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- out signals
+ LED : out std_logic
+ );
+ end component;
+
+ component wb_button
+ port (
+ -- global signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic ;
+ -- irq
+ wbs_irq_s : out std_logic ;
+
+ -- fpga input
+ button : in std_logic
+ );
+ end component;
+
+ component irq_mngr
+ generic
+ (
+ irq_count : integer := 1;
+ irq_level : std_logic := '1'
+ );
+ port (
+ -- Global Signals
+ gls_clk : in std_logic;
+ gls_reset : in std_logic;
+
+ -- Wishbone interface signals
+ wbs_s1_address : in std_logic; -- Address bus
+ wbs_s1_readdata : out std_logic_vector(15 downto 0); -- Data bus for read access
+ wbs_s1_writedata : in std_logic_vector(15 downto 0); -- Data bus for write access
+ wbs_s1_ack : out std_logic; -- Access acknowledge
+ wbs_s1_strobe : in std_logic; -- Data Strobe
+ wbs_s1_write : in std_logic; -- Write access
+ -- irq from other IP
+ wbs_s1_irq : in std_logic_vector(irq_count-1 downto 0);
+ -- Component external signals
+ gls_irq : out std_logic -- IRQ request
+ );
+ end component irq_mngr;
+
+ -- irq_mngr connection signal
+ signal gls_clk_s3 : std_logic ;
+ signal gls_reset_s3 : std_logic ;
+ signal wbs_address_s3 : std_logic ;
+ signal wbs_readdata_s3 : std_logic_vector(15 downto 0);
+ signal wbs_writedata_s3: std_logic_vector( 15 downto 0);
+ signal wbs_ack_s3 : std_logic ;
+ signal wbs_strobe_s3 : std_logic ;
+ signal wbs_write_s3 : std_logic ;
+ signal wbs_irq_s3 : std_logic;
+
+ -- button connection signal
+ signal gls_reset_s2 : std_logic ;
+ signal gls_clk_s2 : std_logic ;
+ signal wbs_readdata_s2: std_logic_vector(15 downto 0);
+ signal wbs_ack_s2 : std_logic ;
+ signal wbs_strobe_s2 : std_logic ;
+ signal wbs_write_s2 : std_logic ;
+ signal wbs_irq_s2 : std_logic ;
+
+ -- imx_wrapper connection signals
+ signal gls_reset_m1 : std_logic ;
+ Signal gls_clk_m1 : std_logic ;
+ signal wbm_address_m1 : std_logic_vector( 12 downto 0);
+ Signal wbm_readdata_m1 : std_logic_vector( 15 downto 0);
+ Signal wbm_writedata_m1 : std_logic_vector( 15 downto 0);
+ Signal wbm_strobe_m1 : std_logic ;
+ signal wbm_write_m1 : std_logic ;
+ Signal wbm_sel_m1 : std_logic_vector( 1 downto 0);
+ signal wbm_ack_m1 : std_logic ;
+ Signal wbm_cycle_m1 : std_logic ;
+
+ -- led connection signals
+ Signal gls_reset_s1 : std_logic ;
+ Signal gls_clk_s1 : std_logic ;
+ Signal wbs_writedata_s1 : std_logic_vector( 15 downto 0);
+ Signal wbs_readdata_s1 : std_logic_vector( 15 downto 0);
+ Signal wbs_strobe_s1 : std_logic ;
+ Signal wbs_write_s1 : std_logic ;
+ Signal wbs_ack_s1 : std_logic ;
+
+ -- syscon connection signals
+ Signal gls_reset_sys : std_logic ;
+ Signal gls_clk_sys : std_logic ;
+
+begin
+
+ connect_imx_wrapper : imx_wrapper
+ port map (
+ imx_address => imx_addr(12 downto 1),
+ imx_data => imx_data,
+ imx_cs_n => imx_cs_n,
+ imx_oe_n => imx_oe_n,
+ imx_eb3_n => imx_eb3_n,
+
+ gls_reset => gls_reset_m1,
+ gls_clk => gls_clk_m1,
+
+ wbm_address => wbm_address_m1,
+ wbm_readdata => wbm_readdata_m1,
+ wbm_writedata => wbm_writedata_m1,
+ wbm_strobe => wbm_strobe_m1,
+ wbm_write => wbm_write_m1,
+ wbm_sel => wbm_sel_m1,
+ wbm_ack => wbm_ack_m1,
+ wbm_cycle => wbm_cycle_m1
+ );
+
+ connect_wb_led : wb_led
+ port map (
+ gls_reset => gls_reset_s1,
+ gls_clk => gls_clk_s1,
+
+ wbs_writedata => wbs_writedata_s1,
+ wbs_readdata => wbs_readdata_s1,
+ wbs_strobe => wbs_strobe_s1,
+ wbs_write => wbs_write_s1,
+ wbs_ack => wbs_ack_s1,
+
+ LED => LED
+ );
+
+ connect_syscon : syscon
+ port map (
+ ext_clk => clk,
+ ext_reset => '0',
+
+ gls_clk => gls_clk_sys,
+ gls_reset => gls_reset_sys
+ );
+
+ connect_intercon : intercon
+ port map (
+ -- imx_wrapper connexion
+ gls_reset_m1 => gls_reset_m1,
+ gls_clk_m1 => gls_clk_m1,
+ wbm_address_m1 => wbm_address_m1,
+ wbm_readdata_m1 => wbm_readdata_m1,
+ wbm_writedata_m1 => wbm_writedata_m1,
+ wbm_strobe_m1 => wbm_strobe_m1,
+ wbm_write_m1 => wbm_write_m1,
+ wbm_sel_m1 => wbm_sel_m1,
+ wbm_ack_m1 => wbm_ack_m1,
+ wbm_cycle_m1 => wbm_cycle_m1,
+ -- led connexion
+ gls_reset_s1 => gls_reset_s1,
+ gls_clk_s1 => gls_clk_s1,
+ wbs_writedata_s1 => wbs_writedata_s1,
+ wbs_readdata_s1 => wbs_readdata_s1,
+ wbs_strobe_s1 => wbs_strobe_s1,
+ wbs_write_s1 => wbs_write_s1,
+ wbs_ack_s1 => wbs_ack_s1,
+ -- button connexion
+ gls_reset_s2 => gls_reset_s2,
+ gls_clk_s2 => gls_clk_s2,
+ wbs_readdata_s2 => wbs_readdata_s2,
+ wbs_strobe_s2 => wbs_strobe_s2,
+ wbs_write_s2 => wbs_write_s2,
+ wbs_ack_s2 => wbs_ack_s2,
+ wbs_irq_s2 => wbs_irq_s2,
+ -- irq connexion
+ gls_reset_s3 => gls_reset_s3,
+ gls_clk_s3 => gls_clk_s3,
+ wbs_address_s3 => wbs_address_s3,
+ wbs_writedata_s3 => wbs_writedata_s3,
+ wbs_readdata_s3 => wbs_readdata_s3,
+ wbs_strobe_s3 => wbs_strobe_s3,
+ wbs_write_s3 => wbs_write_s3,
+ wbs_ack_s3 => wbs_ack_s3,
+ wbs_irq_s3 => wbs_irq_s3,
+ -- global signals
+ gls_reset_sys => gls_reset_sys,
+ gls_clk_sys => gls_clk_sys
+ );
+
+ connect_button : wb_button
+ port map (
+ -- global signals
+ gls_reset => gls_reset_s2,
+ gls_clk => gls_clk_s2,
+ wbs_readdata => wbs_readdata_s2,
+ wbs_strobe => wbs_strobe_s2,
+ wbs_write => wbs_write_s2,
+ wbs_ack => wbs_ack_s2,
+ -- irq
+ wbs_irq_s => wbs_irq_s2,
+ -- fpga input
+ button => button
+ );
+
+ connect_irq_mngr : irq_mngr
+ port map (
+ -- Global Signals
+ gls_clk => gls_clk_s3,
+ gls_reset => gls_reset_s3,
+ -- Wishbone interface signals
+ wbs_s1_address => wbs_address_s3, -- Address bus
+ wbs_s1_readdata => wbs_readdata_s3, -- Data bus for read access
+ wbs_s1_writedata => wbs_writedata_s3, -- Data bus for write access
+ wbs_s1_ack => wbs_ack_s3, -- Access acknowledge
+ wbs_s1_strobe => wbs_strobe_s3, -- Data Strobe
+ wbs_s1_write => wbs_write_s3, -- Write access
+ wbs_s1_irq(0) => wbs_irq_s3, -- irq from other IP
+ gls_irq => imx_irq -- Component external signals
+ );
+
+end architecture wb_top_1;
+
Modified: trunk/firmware/wishbone_example/src/wishbone/imx_wrapper.vhd
===================================================================
--- trunk/firmware/wishbone_example/src/wishbone/imx_wrapper.vhd 2009-03-02 16:14:50 UTC (rev 1105)
+++ trunk/firmware/wishbone_example/src/wishbone/imx_wrapper.vhd 2009-03-03 09:56:47 UTC (rev 1106)
@@ -49,20 +49,18 @@
imx_cs_n : in std_logic;
imx_oe_n : in std_logic;
imx_eb3_n : in std_logic;
-
-- Global Signals
gls_reset : in std_logic;
gls_clk : in std_logic;
-
-- Wishbone interface signals
- wbm_address : out std_logic_vector(12 downto 0); -- Address bus
- wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
- wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
- wbm_strobe : out std_logic; -- Data Strobe
- wbm_write : out std_logic; -- Write access
- wbm_sel : out std_logic_vector(1 downto 0); -- select LSB or/and MSB byte
- wbm_ack : in std_logic ; -- acknowledge
- wbm_cycle : out std_logic -- bus cycle in progress
+ wbm_address : out std_logic_vector(12 downto 0); -- Address bus
+ wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
+ wbm_writedata: out std_logic_vector(15 downto 0); -- Data bus for write access
+ wbm_strobe : out std_logic; -- Data Strobe
+ wbm_write : out std_logic; -- Write access
+ wbm_sel : out std_logic_vector(1 downto 0); -- select LSB or/and MSB byte
+ wbm_ack : in std_logic ; -- acknowledge
+ wbm_cycle : out std_logic -- bus cycle in progress
);
end entity;
@@ -70,43 +68,43 @@
Architecture RTL of imx_wrapper is
-- ----------------------------------------------------------------------------
-signal write : std_logic;
-signal read : std_logic;
-signal sel : std_logic_vector(1 downto 0);
-signal strobe : std_logic;
-signal writedata : std_logic_vector(15 downto 0);
-signal address : std_logic_vector(12 downto 0);
+ signal write : std_logic;
+ signal read : std_logic;
+ signal sel : std_logic_vector(1 downto 0);
+ signal strobe : std_logic;
+ signal writedata : std_logic_vector(15 downto 0);
+ signal address : std_logic_vector(12 downto 0);
begin
--- ----------------------------------------------------------------------------
--- External signals synchronization process
--- ----------------------------------------------------------------------------
-process(gls_clk, gls_reset)
-begin
- if(gls_reset='1') then
- write <= '0';
- read <= '0';
- sel <= "00";
- strobe <= '0';
- writedata <= (others => '0');
- address <= (others => '0');
- elsif(rising_edge(gls_clk)) then
- strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb3_n);
- write <= not (imx_cs_n or imx_eb...
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