[Armadeus-commitlog] SF.net SVN: armadeus:[1014] branches/tsc210x/buildroot/target/device/ armadeu
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[Armadeus-commitlog] SF.net SVN: armadeus:[1014] branches/tsc210x/buildroot/target/device/ armadeus/linux/kernel-patches/2.6.27.2
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From: <ar...@us...> - 2009-01-14 09:37:09
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Revision: 1014
http://armadeus.svn.sourceforge.net/armadeus/?rev=1014&view=rev
Author: artemys
Date: 2009-01-14 09:37:05 +0000 (Wed, 14 Jan 2009)
Log Message:
-----------
[TSC BRANCH] [LINUX] Remove old i.MXL SSI registers definition -> build is now broken
Modified Paths:
--------------
branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-030-armadeus-add_USB_registers.patch
branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-093-armadeus-add_ssi_registers_definition.patch
Modified: branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-030-armadeus-add_USB_registers.patch
===================================================================
--- branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-030-armadeus-add_USB_registers.patch 2009-01-14 09:32:35 UTC (rev 1013)
+++ branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-030-armadeus-add_USB_registers.patch 2009-01-14 09:37:05 UTC (rev 1014)
@@ -20,7 +20,7 @@
#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
-@@ -591,4 +591,146 @@
+@@ -591,4 +591,132 @@
#define UTS_RXFULL (1<<3) /* RxFIFO full */
#define UTS_SOFTRST (1<<0) /* Software reset */
@@ -142,20 +142,6 @@
+#define USB_ENDIAN (1<<28) /* Endian of USB modules */
+#define USB_POWER (1<<0) /* Power mode of USB modules */
+
-+/*
-+ * SSI register
-+ */
-+#define SSI_STX __REG(IMX_SSI_BASE)
-+#define SSI_SRX __REG(IMX_SSI_BASE + 0x4)
-+#define SSI_SCSR __REG(IMX_SSI_BASE + 0x8)
-+#define SSI_STCR __REG(IMX_SSI_BASE + 0xC)
-+#define SSI_SRCR __REG(IMX_SSI_BASE + 0x10)
-+#define SSI_STCCR __REG(IMX_SSI_BASE + 0x14)
-+#define SSI_SRCCR __REG(IMX_SSI_BASE + 0x18)
-+#define SSI_STSR __REG(IMX_SSI_BASE + 0x1C)
-+#define SSI_SFCSR __REG(IMX_SSI_BASE + 0x20)
-+#define SSI_STR __REG(IMX_SSI_BASE + 0x24)
-+#define SSI_SOR __REG(IMX_SSI_BASE + 0x28)
+
+#define SPI1_RXDATA __REG(IMX_SPI1_BASE + 0x0)
+#define SPI1_TXDATA __REG(IMX_SPI1_BASE + 0x4)
Modified: branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-093-armadeus-add_ssi_registers_definition.patch
===================================================================
--- branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-093-armadeus-add_ssi_registers_definition.patch 2009-01-14 09:32:35 UTC (rev 1013)
+++ branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-093-armadeus-add_ssi_registers_definition.patch 2009-01-14 09:37:05 UTC (rev 1014)
@@ -14,93 +14,3 @@
#define CCR_DMOD_LINEAR ( 0x0 << 12 )
#define CCR_DMOD_2D ( 0x1 << 12 )
#define CCR_DMOD_FIFO ( 0x2 << 12 )
-@@ -609,21 +609,76 @@
- #define USB_ENDIAN (1<<28) /* Endian of USB modules */
- #define USB_POWER (1<<0) /* Power mode of USB modules */
-
--/*
-- * SSI register
-+/*
-+ * SSI registers
- */
--#define SSI_STX __REG(IMX_SSI_BASE)
--#define SSI_SRX __REG(IMX_SSI_BASE + 0x4)
--#define SSI_SCSR __REG(IMX_SSI_BASE + 0x8)
--#define SSI_STCR __REG(IMX_SSI_BASE + 0xC)
--#define SSI_SRCR __REG(IMX_SSI_BASE + 0x10)
--#define SSI_STCCR __REG(IMX_SSI_BASE + 0x14)
--#define SSI_SRCCR __REG(IMX_SSI_BASE + 0x18)
--#define SSI_STSR __REG(IMX_SSI_BASE + 0x1C)
--#define SSI_SFCSR __REG(IMX_SSI_BASE + 0x20)
--#define SSI_STR __REG(IMX_SSI_BASE + 0x24)
--#define SSI_SOR __REG(IMX_SSI_BASE + 0x28)
-+#define SSI_STX __REG(IMX_SSI_BASE) /* Transmit Data */
-+#define SSI_SRX __REG(IMX_SSI_BASE + 0x4) /* Receive Data */
-+#define SSI_SCSR __REG(IMX_SSI_BASE + 0x8) /* Control/Status */
-+#define SSI_STCR __REG(IMX_SSI_BASE + 0xC) /* Transmit Config */
-+#define SSI_SRCR __REG(IMX_SSI_BASE + 0x10) /* Receive Donfig */
-+#define SSI_STCCR __REG(IMX_SSI_BASE + 0x14) /* Transmit Clock Ctrl */
-+#define SSI_SRCCR __REG(IMX_SSI_BASE + 0x18) /* Receive Clock Ctrl */
-+#define SSI_STSR __REG(IMX_SSI_BASE + 0x1C) /* Time Slot */
-+#define SSI_SFCSR __REG(IMX_SSI_BASE + 0x20) /* FIFO Control/Status */
-+#define SSI_SOR __REG(IMX_SSI_BASE + 0x28) /* Option */
-+
-+/* SSI Control/Status Register bit fields */
-+#define SSI_SYS_CLK_EN (1<<15) /* System Clock Enable */
-+#define SSI_NORMAL_MODE (0x00<<13) /* Normal Mode Select */
-+#define SSI_I2S_MASTER_MODE (0x01<<13) /* I2S Master Select */
-+#define SSI_I2S_SLAVE_MODE (0x02<<13) /* I2S Slave Select */
-+#define SSI_SYN (1<<12) /* Synchronous Mode */
-+#define SSI_NET (1<<11) /* Network Mode */
-+#define SSI_RE (1<<10) /* Receive Enable */
-+#define SSI_TE (1<<9) /* Transmit Enable */
-+#define SSI_EN (1<<8) /* SSI Enable*/
-+#define SSI_RDR (1<<7) /* Receive Data Ready */
-+#define SSI_TDE (1<<6) /* Transmit Data Register Empty */
-+#define SSI_ROE (1<<5) /* Receive Overrun Error */
-+#define SSI_TUE (1<<4) /* Transmitter Underrun Error */
-+#define SSI_TFS (1<<3) /* Transmit Frame Sync */
-+#define SSI_RFS (1<<2) /* Receive Frame Sync */
-+#define SSI_RFF (1<<1) /* Receive FIFO Full */
-+#define SSI_TFE (1<<0) /* Transmit FIFO Empty */
-+
-+/* SSI Transmit/Receive Configuration Registers bit fields */
-+#define SSI_BIT0 (1<<10) /* Transmit/Receive Bit0 */
-+#define SSI_MAE (1<<9) /* Transmit/Receive DMA Enable */
-+#define SSI_IE (1<<8) /* Transmit/Receive Interrupt Enable */
-+#define SSI_FEN (1<<7) /* Transmit/Receive FIFO Enable */
-+#define SSI_FDIR (1<<6) /* Transmit/Receive Frame Direction */
-+#define SSI_DIR (1<<5) /* Transmit/Receive Direction */
-+#define SSI_SHFD (1<<4) /* Transmit/Receive Shift Direction */
-+#define SSI_SCKP (1<<3) /* Transmit/Receive Clock Polarity */
-+#define SSI_FSI (1<<2) /* Transmit/Receive Frame Sync Invert */
-+#define SSI_FSL (1<<1) /* Transmit/Receive Frame Sync Length */
-+#define SSI_EFS (1<<0) /* Transmit/Receive Early Frame Sync */
-+
-+/* SSI Transmit/Receive Clock Control Registers bit fields */
-+#define SSI_PSR (1<<15) /* Prescaler Range */
-+#define SSI_WL_8 (0x00<<13) /* Word Length = 8 bits */
-+#define SSI_WL_10 (0x01<<13) /* Word Length = 10 bits */
-+#define SSI_WL_12 (0x02<<13) /* Word Length = 12 bits */
-+#define SSI_WL_16 (0x03<<13) /* Word Length = 16 bits */
-+#define SSI_DC(x) ((x&0x1F)<<8) /* Frame Rate Divider Control */
-+#define SSI_PM(x) ((x&0xFF)<<0) /* Prescaler Modulus Select */
-+
-+/* SSI FIFO Control/Status Register bit fields */
-+#define SSI_RFCNT(x) ((x&0x0F)<<12) /* Receive FIFO Counter */
-+#define SSI_TFCNT(x) ((x&0x0F)<<8) /* Transmit FIFO Counter */
-+#define SSI_RFWM(x) ((x&0x0F)<<4) /* Receive FIFO Full Watermark */
-+#define SSI_TFWM(x) ((x&0x0F)<<0) /* Transmit FIFO Empty Watermark */
-+
-+/* SSI Option Register bit fields */
-+#define SSI_CLKOFF (1<<6) /* Clock Off */
-+#define SSI_RX_CLR (1<<5) /* Receiver Clear */
-+#define SSI_TX_CLR (1<<4) /* Transmitter Clear */
-+#define SSI_SYNRST (1<<0) /* Frame Sync Reset */
-
-+/*
-+ * SPI registers
-+ */
- #define SPI1_RXDATA __REG(IMX_SPI1_BASE + 0x0)
- #define SPI1_TXDATA __REG(IMX_SPI1_BASE + 0x4)
- #define SPI1_CONTROL __REG(IMX_SPI1_BASE + 0x8)
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