[Armadeus-commitlog] SF.net SVN: armadeus:[1012] branches/tsc210x/buildroot/target/device/ armadeu
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[Armadeus-commitlog] SF.net SVN: armadeus:[1012] branches/tsc210x/buildroot/target/device/ armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27. 2-095-armadeus-imx-ssi-add_driver.patch
Revision: 1012
http://armadeus.svn.sourceforge.net/armadeus/?rev=1012&view=rev
Author: artemys
Date: 2009-01-14 08:07:18 +0000 (Wed, 14 Jan 2009)
Log Message:
-----------
[TSC BRANCH] [LINUX] Makes imx-ssi looks more like i.MX27 mxc-ssi
Modified Paths:
--------------
branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-095-armadeus-imx-ssi-add_driver.patch
Modified: branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-095-armadeus-imx-ssi-add_driver.patch
===================================================================
--- branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-095-armadeus-imx-ssi-add_driver.patch 2009-01-13 16:46:04 UTC (rev 1011)
+++ branches/tsc210x/buildroot/target/device/armadeus/linux/kernel-patches/2.6.27.2/linux-2.6.27.2-095-armadeus-imx-ssi-add_driver.patch 2009-01-14 08:07:18 UTC (rev 1012)
@@ -3,7 +3,7 @@
(Take a look at armadeus/target/linux/ directory to know how to generate it)
--- linux-2.6.27.2.original/sound/arm/imx-ssi.c
+++ linux-2.6.27.2.mod/sound/arm/imx-ssi.c
-@@ -0,0 +1,504 @@
+@@ -0,0 +1,514 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, ke...@pe...
@@ -130,19 +130,25 @@
+
+int imx_ssi_setup_unit_to_iis_slave(int id)
+{
-+// BUG_ON(unit[id].io == NULL);
++ u32 scsr;
+
+ pr_debug("%s called for unit %d\n", __func__, id);
++ BUG_ON(unit[id].io == NULL); /* (only one on i.MXL/1) */
+
-+ /* disable this unit (only one on i.MXL/1) */
-+ SSI_SCSR &= ~SSI_EN;
++ /* choose mode */
++ scsr = SSI_SCSR_I2S_MODE_SLAVE | SSI_SCSR_SYN;
+
++ /* disable this unit */
++ set_reg(scsr, SSI_SCSR, id);
++// SSI_SCSR &= ~SSI_SCSR_EN;
++
+ /* Transmit config */
-+ SSI_STCR = SSI_MAE | /* Activate DMA */
-+ SSI_FEN | /* FIFO enabled */
-+ SSI_SCKP | /* send @falling edge */
-+ SSI_FSI | /* Frame sync active low */
-+ SSI_EFS; /* one bit shift */
++ set_reg(SSI_MAE | /* Activate DMA */
++ SSI_FEN | /* FIFO enabled */
++ SSI_SCKP | /* send @falling edge */
++ SSI_FSI | /* Frame sync active low */
++ SSI_EFS, /* one bit shift */
++ SSI_STCR, id);
+
+// set_reg(SSI_STCR_TFEN0 | /* FIFO 0 enabled */
+// SSI_STCR_TXBIT0 | /* MSB first, data bits 0...15 are valid */
@@ -170,23 +176,22 @@
+ * words (left/right) there
+ */
+ /* SSI FIFO watermark */
-+ SSI_SFCSR = SSI_RFWM(8) | SSI_TFWM(TRANSMIT_WM_LEVEL);
-+// set_reg(SSI_SFCSR_RFWM0(DMA_RXFIFO_BURST) |
-+// SSI_SFCSR_TFWM0(DMA_TXFIFO_BURST), SSI_SFCSR, id);
++// SSI_SFCSR = SSI_RFWM(8) | SSI_TFWM(TRANSMIT_WM_LEVEL);
++ set_reg(SSI_SFCSR_RFWM(8) | SSI_SFCSR_TFWM(TRANSMIT_WM_LEVEL), SSI_SFCSR, id);
+
+ /*
+ * We want to provide I2S. This means we always need two words per
+ * sample signal. In this case 16 bit per word, 32 bit per sample.
+ * PMIC sends always 4 words (=2 samples) per sync!
+ */
-+ SSI_STCCR = SSI_WL_16 | SSI_DC(0);
-+// set_reg(SSI_STCCR_WL(16) | SSI_STCCR_DC(1), SSI_STCCR, id);
-+ SSI_SRCCR = SSI_WL_16 | SSI_DC(0);
-+// set_reg(SSI_SRCCR_WL(16) | SSI_SRCCR_DC(3), SSI_SRCCR, id);
++// SSI_STCCR = SSI_WL_16 | SSI_DC(0);
++ set_reg(SSI_WL_16 | SSI_DC(0), SSI_STCCR, id);
++// SSI_SRCCR = SSI_WL_16 | SSI_DC(0);
++ set_reg(SSI_WL_16 | SSI_DC(0), SSI_SRCCR, id);
+
+ /* enable the unit */
-+ SSI_SCSR = SSI_I2S_SLAVE_MODE | SSI_SYN | SSI_EN;
-+// set_reg(scr | SSI_SCR_SSIEN, SSI_SCR, id);
++// SSI_SCSR = SSI_SCSR_I2S_MODE_SLAVE | SSI_SCSR_SYN | SSI_SCSR_EN;
++ set_reg(scsr | SSI_SCSR_EN, SSI_SCSR, id);
+
+ return 0;
+}
@@ -194,21 +199,26 @@
+
+int imx_ssi_setup_unit_to_iis_master(int id)
+{
-+ BUG_ON(unit[id].io == NULL);
++ u32 scsr;
+
+ pr_debug("%s called for unit %d\n", __func__, id);
++ BUG_ON(unit[id].io == NULL); /* (only one on i.MXL/1) */
+
-+ /* disable this unit (only one on i.MXL/1) */
-+ SSI_SCSR &= ~SSI_EN;
++ /* choose mode */
++ scsr = SSI_SCSR_I2S_MODE_MSTR | SSI_SCSR_SYN;
+
++ /* disable this unit */
++ set_reg(scsr, SSI_SCSR, id);
++
+ /* Transmit config */
-+ SSI_STCR = SSI_MAE | /* Activate DMA */
-+ SSI_FEN | /* FIFO enabled */
-+ SSI_FDIR | /* Frame sync internally generated */
-+ SSI_DIR | /* Clock internally generated */
-+ SSI_SCKP | /* send @falling edge */
-+ SSI_FSI | /* Frame sync active low */
-+ SSI_EFS; /* one bit shift */
++ set_reg(SSI_MAE | /* Activate DMA */
++ SSI_FEN | /* FIFO enabled */
++ SSI_FDIR | /* Frame sync internally generated */
++ SSI_DIR | /* Clock internally generated */
++ SSI_SCKP | /* send @falling edge */
++ SSI_FSI | /* Frame sync active low */
++ SSI_EFS, /* one bit shift */
++ SSI_STCR, id);
+
+ /*
+ * Watermark settings:
@@ -222,18 +232,18 @@
+ * words (left/right) there
+ */
+ /* SSI FIFO watermark */
-+ SSI_SFCSR = SSI_RFWM(8) | SSI_TFWM(TRANSMIT_WM_LEVEL);
++ set_reg(SSI_SFCSR_RFWM(8) | SSI_SFCSR_TFWM(TRANSMIT_WM_LEVEL), SSI_SFCSR, id);
+
+ /*
+ * We want to provide I2S. This means we always need two words per
+ * sample signal. In this case 16 bit per word, 32 bit per sample.
+ * PMIC sends always 4 words (=2 samples) per sync!
+ */
-+ SSI_STCCR = 0x00006103;
-+ SSI_SRCCR = 0x00006103;
++// SSI_STCCR = 0x00006103;
++// SSI_SRCCR = 0x00006103;
+
+ /* enable the unit */
-+ SSI_SCSR = /*SSI_SYS_CLK_EN |*/ SSI_I2S_MASTER_MODE | SSI_SYN | /*SSI_TE |*/ SSI_EN;
++// SSI_SCSR = /*SSI_SYS_CLK_EN |*/ SSI_SCSR_I2S_MODE_MSTR | SSI_SCSR_SYN | /*SSI_TE |*/ SSI_SCSR_EN;
+
+ return 0;
+}
@@ -327,15 +337,15 @@
+int imx_ssi_prepare(struct snd_pcm_substream *substream,
+ int ssi_id)
+{
-+ SSI_SCSR |= SSI_EN;
-+// set_reg_bits(SSI_SCR_SSIEN, SSI_SCR_SSIEN, SSI_SCR, ssi_id);
++// SSI_SCSR |= SSI_SCSR_EN;
++ set_reg_bits(SSI_SCSR_EN, SSI_SCSR_EN, SSI_SCSR, ssi_id);
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+ SSI_STCR |= SSI_MAE;
-+/* set_reg_bits(SSI_SIER_TDMAE, SSI_SIER_TDMAE, SSI_SIER, ssi_id);*/
++// SSI_STCR |= SSI_MAE;
++ set_reg_bits(SSI_MAE, SSI_MAE, SSI_STCR, ssi_id);
+ else
-+ SSI_SRCR |= SSI_MAE;
-+// set_reg_bits(SSI_SIER_RDMAE, SSI_SIER_RDMAE, SSI_SIER, ssi_id);
++// SSI_SRCR |= SSI_MAE;
++ set_reg_bits(SSI_MAE, SSI_MAE, SSI_SRCR, ssi_id);
+
+ return 0;
+}
@@ -343,14 +353,14 @@
+void imx_ssi_shutdown(struct snd_pcm_substream *substream,
+ int ssi_id)
+{
-+ SSI_SCSR &= ~SSI_EN;
-+// set_reg_bits(SSI_SCR_SSIEN, 0, SSI_SCR, ssi_id);
++// SSI_SCSR &= ~SSI_SCSR_EN;
++ set_reg_bits(SSI_SCSR_EN, 0, SSI_SCSR, ssi_id);
+
+}
+
+int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd, int ssi_id)
+{
-+// u32 scr = get_reg(SSI_SCR, ssi_id);
++ u32 scsr = get_reg(SSI_SCSR, ssi_id);
+ u32 temp;
+
+ pr_debug("%s called\n", __func__);
@@ -358,30 +368,30 @@
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ /* clear SSI underrun (needed ??) */
-+ temp = SSI_SCSR;
-+ SSI_STX = 0x0000;
++ temp = get_reg(SSI_SCSR, ssi_id);
++ set_reg(0x0000, SSI_STX, ssi_id);
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+ SSI_SCSR |= SSI_TE;
++ scsr |= SSI_SCSR_TE;
+ else
-+ SSI_SCSR |= SSI_RE;
++ scsr |= SSI_SCSR_RE;
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-+ SSI_SCSR &= ~SSI_TE;
++ scsr &= ~SSI_SCSR_TE;
+ else
-+ SSI_SCSR &= ~SSI_RE;
++ scsr &= ~SSI_SCSR_RE;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
-+// set_reg(scr, SSI_SCR, ssi_id);
++ set_reg(scsr, SSI_SCSR, ssi_id);
+
+ return 0;
+}
@@ -554,3 +564,113 @@
+#define DMA_RXFIFO_BURST 0x4
+
+#endif /* __SOUND_ARM_IMX_SSI_H */
+PATCH AUTOMATICALLY GENERATED
+DON'T EDIT IT OR YOUR MODIFICATIONS WILL BE LOST
+(Take a look at armadeus/target/linux/ directory to know how to generate it)
+--- linux-2.6.27.2.original/arch/arm/mach-imx/include/mach/imx_ssi.h
++++ linux-2.6.27.2.mod/arch/arm/mach-imx/include/mach/imx_ssi.h
+@@ -0,0 +1,104 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2008 Juergen Beisert, ke...@pe...
++ * Copyright 2009 Armadeus systems, <jul...@ar...>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++#ifndef __ASM_ARCH_IMX_SSI_H
++#define __ASM_ARCH_IMX_SSI_H
++
++#include <linux/platform_device.h>
++
++struct imx_ssi_platform_data {
++ int (*init)(struct platform_device *pdev);
++ int (*exit)(struct platform_device *pdev);
++};
++
++/* Transmit Data Register */
++#define SSI_STX 0x00
++
++/* Receive Data Register */
++#define SSI_SRX 0x04
++
++/* Control/Status Register */
++#define SSI_SCSR 0x08
++# define SSI_SCSR_SYS_CLK_EN (1<<15) /* System Clock Enable */
++# define SSI_SCSR_I2S_MODE_NORM (0x00<<13) /* Normal Mode Select */
++# define SSI_SCSR_I2S_MODE_MSTR (0x01<<13) /* I2S Master Select */
++# define SSI_SCSR_I2S_MODE_SLAVE (0x02<<13) /* I2S Slave Select */
++# define SSI_SCSR_SYN (1<<12) /* Synchronous Mode */
++# define SSI_SCSR_NET (1<<11) /* Network Mode */
++# define SSI_SCSR_RE (1<<10) /* Receive Enable */
++# define SSI_SCSR_TE (1<<9) /* Transmit Enable */
++# define SSI_SCSR_EN (1<<8) /* SSI Enable*/
++# define SSI_SCSR_RDR (1<<7) /* Receive Data Ready */
++# define SSI_SCSR_TDE (1<<6) /* Transmit Data Reg. Empty */
++# define SSI_SCSR_ROE (1<<5) /* Receive Overrun Error */
++# define SSI_SCSR_TUE (1<<4) /* Transmitter Underrun Error */
++# define SSI_SCSR_TFS (1<<3) /* Transmit Frame Sync */
++# define SSI_SCSR_RFS (1<<2) /* Receive Frame Sync */
++# define SSI_SCSR_RFF (1<<1) /* Receive FIFO Full */
++# define SSI_SCSR_TFE (1<<0) /* Transmit FIFO Empty */
++# define SSI_SCSR_I2S_MODE_SHIFT 13
++
++/* Transmit Configuration Register */
++#define SSI_STCR 0x0c
++/* Receive Configuration Register */
++#define SSI_SRCR 0x10
++/* STCR & SRCR have the same bit fields */
++# define SSI_BIT0 (1<<10) /* Transmit/Receive Bit0 */
++# define SSI_MAE (1<<9) /* Transmit/Receive DMA Enable */
++# define SSI_IE (1<<8) /* Transmit/Receive Interrupt Enable */
++# define SSI_FEN (1<<7) /* Transmit/Receive FIFO Enable */
++# define SSI_FDIR (1<<6) /* Transmit/Receive Frame Direction */
++# define SSI_DIR (1<<5) /* Transmit/Receive Direction */
++# define SSI_SHFD (1<<4) /* Transmit/Receive Shift Direction */
++# define SSI_SCKP (1<<3) /* Transmit/Receive Clock Polarity */
++# define SSI_FSI (1<<2) /* Transmit/Receive Frame Sync Invert */
++# define SSI_FSL (1<<1) /* Transmit/Receive Frame Sync Length */
++# define SSI_EFS (1<<0) /* Transmit/Receive Early Frame Sync */
++
++/* Transmit Clock Control Register */
++#define SSI_STCCR 0x14
++/* Receive Clock Control Register */
++#define SSI_SRCCR 0x18
++/* STCCR & SRCCR have the same bit fields */
++# define SSI_PSR (1 << 15) /* Prescaler Range */
++# define SSI_WL_8 (0x00 << 13) /* Word Length = 8 bits */
++# define SSI_WL_10 (0x01 << 13) /* Word Length = 10 bits */
++# define SSI_WL_12 (0x02 << 13) /* Word Length = 12 bits */
++# define SSI_WL_16 (0x03 << 13) /* Word Length = 16 bits */
++# define SSI_DC(x) (((x) & 0x1f) << 8) /* Frame Rate Divider Control */
++# define SSI_PM(x) (((x) & 0xff) << 0) /* Prescaler Modulus Select */
++
++/* Time Slot Register */
++#define SSI_STSR 0x1c
++
++/* FIFO Control/Status Register */
++#define SSI_SFCSR 0x20
++# define SSI_SFCSR_RFCNT(x) (((x) & 0x0f) << 12) /* Receive FIFO Counter */
++# define SSI_SFCSR_TFCNT(x) (((x) & 0x0f) << 8) /* Transmit FIFO Counter */
++# define SSI_SFCSR_RFWM(x) (((x) & 0x0f) << 4) /* RX FIFO Full Watermark */
++# define SSI_SFCSR_TFWM(x) (((x) & 0x0f) << 0) /* TX FIFO Empty Watermark */
++
++/* Option Register */
++#define SSI_SOR 0x28
++# define SSI_SOR_CLKOFF (1<<6) /* Clock Off */
++# define SSI_SOR_RX_CLR (1<<5) /* Receiver Clear */
++# define SSI_SOR_TX_CLR (1<<4) /* Transmitter Clear */
++# define SSI_SOR_SYNRST (1<<0) /* Frame Sync Reset */
++
++#endif /* __ASM_ARCH_IMX_SSI_H */
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