[Armadeus-commitlog] SF.net SVN: armadeus:[996] trunk/target/linux/debug/imxregs/imx27regs.h

[<ar...@us...>]

Revision: 996
          http://armadeus.svn.sourceforge.net/armadeus/?rev=996&view=rev
Author:   artemys
Date:     2009-01-07 17:57:03 +0000 (Wed, 07 Jan 2009)

Log Message:
-----------
[DEBUG] imxregs: makes the distinguish between the two SSI register sets on i.MX27

Modified Paths:
--------------
    trunk/target/linux/debug/imxregs/imx27regs.h

Modified: trunk/target/linux/debug/imxregs/imx27regs.h
===================================================================
--- trunk/target/linux/debug/imxregs/imx27regs.h	2009-01-06 00:19:40 UTC (rev 995)
+++ trunk/target/linux/debug/imxregs/imx27regs.h	2009-01-07 17:57:03 UTC (rev 996)
@@ -334,53 +334,53 @@
 { "CSPI_DMA2",    0x1000F018, 0, 0xffffffff, 'x', "CSPI DMA Register 2" },
 { "CSPI_RESET2",  0x1000F01C, 0, 0xffffffff, 'x', "CSPI 2 Soft Reset Register" },
 // SSI1
-{ "STX0",    0x10010000, 0, 0xffffffff, 'x', "SSI Transmit Data Register 0" },
-{ "STX1",    0x10010004, 0, 0xffffffff, 'x', "SSI Transmit Data Register 1" },
-{ "SRX0",    0x10010008, 0, 0xffffffff, 'x', "SSI Receive Data Register 0" },
-{ "SRX1",    0x1001000C, 0, 0xffffffff, 'x', "SSI Receive Data Register 1" },
-{ "SCR",     0x10010010, 0, 0xffffffff, 'x', "SSI Control Register" },
-{ "SISR",    0x10010014, 0, 0xffffffff, 'x', "SSI Interrupt Status Register" },
-{ "SIER",    0x10010018, 0, 0xffffffff, 'x', "SSI Interrupt Enable Register" },
-{ "STCR",    0x1001001C, 0, 0xffffffff, 'x', "SSI Transmit Configuration Register" },
-{ "SRCR",    0x10010020, 0, 0xffffffff, 'x', "SSI Receive Configuration Register" },
-{ "STCCR",   0x10010024, 0, 0xffffffff, 'x', "SSI Transmit Clock Control Register" },
-{ "SRCCR",   0x10010028, 0, 0xffffffff, 'x', "SSI Receive Clock Control Register" },
-{ "SFCSR",   0x1001002C, 0, 0xffffffff, 'x', "SSI FIFO Control/Status Register" },
-{ "STR",     0x10010030, 0, 0xffffffff, 'x', "SSI Test Register" },
-{ "SOR",     0x10010034, 0, 0xffffffff, 'x', "SSI Option Register" },
-{ "SACNT",   0x10010038, 0, 0xffffffff, 'x', "SSI AC97 Control Register" },
-{ "SACADD",  0x1001003C, 0, 0xffffffff, 'x', "SSI AC97 Command Address Register" },
-{ "SACDAT",  0x10010040, 0, 0xffffffff, 'x', "SSI AC97 Command Data Register" },
-{ "SATAG",   0x10010044, 0, 0xffffffff, 'x', "SSI AC97 Tag Register" },
-{ "STMSK",   0x10010048, 0, 0xffffffff, 'x', "SSI Transmit Time Slot Mask Register" },
-{ "SRMSK",   0x1001004C, 0, 0xffffffff, 'x', "SSI Receive Time Slot Mask Register" },
-{ "SACCST",  0x10010050, 0, 0xffffffff, 'x', "SSI AC97 Channel Status Register" },
-{ "SACCEN",  0x10010054, 0, 0xffffffff, 'x', "SSI AC97 Channel Enable Register" },
-{ "SACCDIS", 0x10010058, 0, 0xffffffff, 'x', "SSI AC97 Channel Disable Register" },
+{ "STX0_1",    0x10010000, 0, 0xffffffff, 'x', "SSI_1 Transmit Data Register 0" },
+{ "STX1_1",    0x10010004, 0, 0xffffffff, 'x', "SSI_1 Transmit Data Register 1" },
+{ "SRX0_1",    0x10010008, 0, 0xffffffff, 'x', "SSI_1 Receive Data Register 0" },
+{ "SRX1_1",    0x1001000C, 0, 0xffffffff, 'x', "SSI_1 Receive Data Register 1" },
+{ "SCR_1",     0x10010010, 0, 0xffffffff, 'x', "SSI_1 Control Register" },
+{ "SISR_1",    0x10010014, 0, 0xffffffff, 'x', "SSI_1 Interrupt Status Register" },
+{ "SIER_1",    0x10010018, 0, 0xffffffff, 'x', "SSI_1 Interrupt Enable Register" },
+{ "STCR_1",    0x1001001C, 0, 0xffffffff, 'x', "SSI_1 Transmit Configuration Register" },
+{ "SRCR_1",    0x10010020, 0, 0xffffffff, 'x', "SSI_1 Receive Configuration Register" },
+{ "STCCR_1",   0x10010024, 0, 0xffffffff, 'x', "SSI_1 Transmit Clock Control Register" },
+{ "SRCCR_1",   0x10010028, 0, 0xffffffff, 'x', "SSI_1 Receive Clock Control Register" },
+{ "SFCSR_1",   0x1001002C, 0, 0xffffffff, 'x', "SSI_1 FIFO Control/Status Register" },
+{ "STR_1",     0x10010030, 0, 0xffffffff, 'x', "SSI_1 Test Register" },
+{ "SOR_1",     0x10010034, 0, 0xffffffff, 'x', "SSI_1 Option Register" },
+{ "SACNT_1",   0x10010038, 0, 0xffffffff, 'x', "SSI_1 AC97 Control Register" },
+{ "SACADD_1",  0x1001003C, 0, 0xffffffff, 'x', "SSI_1 AC97 Command Address Register" },
+{ "SACDAT_1",  0x10010040, 0, 0xffffffff, 'x', "SSI_1 AC97 Command Data Register" },
+{ "SATAG_1",   0x10010044, 0, 0xffffffff, 'x', "SSI_1 AC97 Tag Register" },
+{ "STMSK_1",   0x10010048, 0, 0xffffffff, 'x', "SSI_1 Transmit Time Slot Mask Register" },
+{ "SRMSK_1",   0x1001004C, 0, 0xffffffff, 'x', "SSI_1 Receive Time Slot Mask Register" },
+{ "SACCST_1",  0x10010050, 0, 0xffffffff, 'x', "SSI_1 AC97 Channel Status Register" },
+{ "SACCEN_1",  0x10010054, 0, 0xffffffff, 'x', "SSI_1 AC97 Channel Enable Register" },
+{ "SACCDIS_1", 0x10010058, 0, 0xffffffff, 'x', "SSI_1 AC97 Channel Disable Register" },
 // SSI2
-{ "STX0",    0x10011000, 0, 0xffffffff, 'x', "SSI Transmit Data Register 0" },
-{ "STX1",    0x10011004, 0, 0xffffffff, 'x', "SSI Transmit Data Register 1" },
-{ "SRX0",    0x10011008, 0, 0xffffffff, 'x', "SSI Receive Data Register 0" },
-{ "SRX1",    0x1001100C, 0, 0xffffffff, 'x', "SSI Receive Data Register 1" },
-{ "SCR",     0x10011010, 0, 0xffffffff, 'x', "SSI Control Register" },
-{ "SISR",    0x10011014, 0, 0xffffffff, 'x', "SSI Interrupt Status Register" },
-{ "SIER",    0x10011018, 0, 0xffffffff, 'x', "SSI Interrupt Enable Register" },
-{ "STCR",    0x1001101C, 0, 0xffffffff, 'x', "SSI Transmit Configuration Register" },
-{ "SRCR",    0x10011020, 0, 0xffffffff, 'x', "SSI Receive Configuration Register" },
-{ "STCCR",   0x10011024, 0, 0xffffffff, 'x', "SSI Transmit Clock Control Register" },
-{ "SRCCR",   0x10011028, 0, 0xffffffff, 'x', "SSI Receive Clock Control Register" },
-{ "SFCSR",   0x1001102C, 0, 0xffffffff, 'x', "SSI FIFO Control/Status Register" },
-{ "STR",     0x10011030, 0, 0xffffffff, 'x', "SSI Test Register" },
-{ "SOR",     0x10011034, 0, 0xffffffff, 'x', "SSI Option Register" },
-{ "SACNT",   0x10011038, 0, 0xffffffff, 'x', "SSI AC97 Control Register" },
-{ "SACADD",  0x1001103C, 0, 0xffffffff, 'x', "SSI AC97 Command Address Register" },
-{ "SACDAT",  0x10011040, 0, 0xffffffff, 'x', "SSI AC97 Command Data Register" },
-{ "SATAG",   0x10011044, 0, 0xffffffff, 'x', "SSI AC97 Tag Register" },
-{ "STMSK",   0x10011048, 0, 0xffffffff, 'x', "SSI Transmit Time Slot Mask Register" },
-{ "SRMSK",   0x1001104C, 0, 0xffffffff, 'x', "SSI Receive Time Slot Mask Register" },
-{ "SACCST",  0x10011050, 0, 0xffffffff, 'x', "SSI AC97 Channel Status Register" },
-{ "SACCEN",  0x10011054, 0, 0xffffffff, 'x', "SSI AC97 Channel Enable Register" },
-{ "SACCDIS", 0x10011058, 0, 0xffffffff, 'x', "SSI AC97 Channel Disable Register" },
+{ "STX0_2",    0x10011000, 0, 0xffffffff, 'x', "SSI_2 Transmit Data Register 0" },
+{ "STX1_2",    0x10011004, 0, 0xffffffff, 'x', "SSI_2 Transmit Data Register 1" },
+{ "SRX0_2",    0x10011008, 0, 0xffffffff, 'x', "SSI_2 Receive Data Register 0" },
+{ "SRX1_2",    0x1001100C, 0, 0xffffffff, 'x', "SSI_2 Receive Data Register 1" },
+{ "SCR_2",     0x10011010, 0, 0xffffffff, 'x', "SSI_2 Control Register" },
+{ "SISR_2",    0x10011014, 0, 0xffffffff, 'x', "SSI_2 Interrupt Status Register" },
+{ "SIER_2",    0x10011018, 0, 0xffffffff, 'x', "SSI_2 Interrupt Enable Register" },
+{ "STCR_2",    0x1001101C, 0, 0xffffffff, 'x', "SSI_2 Transmit Configuration Register" },
+{ "SRCR_2",    0x10011020, 0, 0xffffffff, 'x', "SSI_2 Receive Configuration Register" },
+{ "STCCR_2",   0x10011024, 0, 0xffffffff, 'x', "SSI_2 Transmit Clock Control Register" },
+{ "SRCCR_2",   0x10011028, 0, 0xffffffff, 'x', "SSI_2 Receive Clock Control Register" },
+{ "SFCSR_2",   0x1001102C, 0, 0xffffffff, 'x', "SSI_2 FIFO Control/Status Register" },
+{ "STR_2",     0x10011030, 0, 0xffffffff, 'x', "SSI_2 Test Register" },
+{ "SOR_2",     0x10011034, 0, 0xffffffff, 'x', "SSI_2 Option Register" },
+{ "SACNT_2",   0x10011038, 0, 0xffffffff, 'x', "SSI_2 AC97 Control Register" },
+{ "SACADD_2",  0x1001103C, 0, 0xffffffff, 'x', "SSI_2 AC97 Command Address Register" },
+{ "SACDAT_2",  0x10011040, 0, 0xffffffff, 'x', "SSI_2 AC97 Command Data Register" },
+{ "SATAG_2",   0x10011044, 0, 0xffffffff, 'x', "SSI_2 AC97 Tag Register" },
+{ "STMSK_2",   0x10011048, 0, 0xffffffff, 'x', "SSI_2 Transmit Time Slot Mask Register" },
+{ "SRMSK_2",   0x1001104C, 0, 0xffffffff, 'x', "SSI_2 Receive Time Slot Mask Register" },
+{ "SACCST_2",  0x10011050, 0, 0xffffffff, 'x', "SSI_2 AC97 Channel Status Register" },
+{ "SACCEN_2",  0x10011054, 0, 0xffffffff, 'x', "SSI_2 AC97 Channel Enable Register" },
+{ "SACCDIS_2", 0x10011058, 0, 0xffffffff, 'x', "SSI_2 AC97 Channel Disable Register" },
 // I2C1
 { "IADR", 0x10012000, 0, 0xffffffff, 'x', "I2C Address Register" },
 { "IFDR", 0x10012004, 0, 0xffffffff, 'x', "I2C Frequency Divider Register" },


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