[Armadeus-commitlog] SF.net SVN: armadeus:[978] trunk/target/linux/modules/isp1761/ apf9328-isp1761
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[Armadeus-commitlog] SF.net SVN: armadeus:[978] trunk/target/linux/modules/isp1761/ apf9328-isp1761.c
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From: <jo...@us...> - 2008-12-28 00:55:30
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Revision: 978
http://armadeus.svn.sourceforge.net/armadeus/?rev=978&view=rev
Author: jorasse
Date: 2008-12-28 00:55:25 +0000 (Sun, 28 Dec 2008)
Log Message:
-----------
[linux] Clean-up apf9328-isp1761 driver - hardware configuration moved to apf9328.c and u-boot 1.3.4 patch 3.5
Modified Paths:
--------------
trunk/target/linux/modules/isp1761/apf9328-isp1761.c
Modified: trunk/target/linux/modules/isp1761/apf9328-isp1761.c
===================================================================
--- trunk/target/linux/modules/isp1761/apf9328-isp1761.c 2008-12-28 00:51:11 UTC (rev 977)
+++ trunk/target/linux/modules/isp1761/apf9328-isp1761.c 2008-12-28 00:55:25 UTC (rev 978)
@@ -1,3 +1,7 @@
+/*
+ * Deprecated - Now part of apf9328.c kernel file and U-Boot 1.3.4 patch 3.5
+ */
+
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/device.h>
@@ -14,145 +18,15 @@
#include <mach/hardware.h>
#include <mach/imx-regs.h>
#endif
-#include <asm/delay.h>
-#include <linux/usb/isp116x.h>
-#define ISP1761_BASE IMX_CS3_PHYS
-#define ISP1761_GPIO_IRQ GPIO_PORTC | 10
-#define ISP1761_IRQ IRQ_GPIOC(10)
-#define CS3U 0x18 /*chip select 3 upper register */
-#define CS3L 0x1C /*chip select 3 lower register */
-
-#define CONFIG_SYS_BUS_FREQ 96 /* 96|48... MHz (BCLOCK and HCLOCK) */
-#define CFG_HCLK_LGTH (1000/CONFIG_SYS_BUS_FREQ) /* ns */
-
-
-
-/* CS3 configuration for ISP176x USB Host */
-#define CFG_CS3_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 peripherals */
-#define CFG_CS3_PIN_ASSERT 0 /* chip select pin state when */
- /* chip select disabled */
-#define CFG_CS3_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
- /* 3=8bits on D[7:0] 6=32 bits..*/
-#define CFG_CS3_SUPERVISOR_PROTECT 0 /* 1 : user mode access prohibited*/
-#define CFG_CS3_WRITE_PROTECT 0 /* 1 : write access prohibited */
-#define CFG_CS3_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal*/
-
-#define CFG_CS3_READ_CYC_LGTH 110 /* ns */
-#define CFG_CS3_OE_ASSERT_DLY 45 /* ns */
-#define CFG_CS3_OE_NEG_DLY 40 /* ns */
-
-#define CFG_CS3_CS_NEG_LGTH 30 /* max 30 ns CS HIGH to CS LOW at 100MHz*/
-#define CFG_CS3_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
-
-#define CFG_CS3_WRITE_XTRA_LGTH 0 /* ns */
-#define CFG_CS3_EB_ASSERT_DLY 45 /* ns */
-#define CFG_CS3_EB_NEG_DLY 45 /* ns */
-#define CFG_CS3_CS_ASSERT_NEG_DLY 35 /* ns */
-
-#define CFG_CS3_SYNC_ENABLE 0 /* enable synchronous burst mode*/
-#define CFG_CS3_SYNC_PAGE_MODE_EMUL 0 /* enable page mode emulation */
-#define CFG_CS3_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
-#define CFG_CS3_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
-#define CFG_CS3_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
-#define CFG_CS3_SYNC_DAT_OUT_LGTH 0 /* ns */
-
-
-#define CFG_CS3U_VAL\
- ((((CFG_CS3_XTRA_DEAD_CYC+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)\
- |((((CFG_CS3_WRITE_XTRA_LGTH+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)<<4)\
- |(((((CFG_CS3_READ_CYC_LGTH+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)-1)&0x3F)<<8)\
- |((((CFG_CS3_CS_NEG_LGTH+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x03)<<14)\
- |((((CFG_CS3_SYNC_DAT_OUT_LGTH+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)<<16)\
- |((CFG_CS3_SYNC_ENABLE&0x01)<<20)\
- |((CFG_CS3_SYNC_PAGE_MODE_EMUL&0x01)<<21)\
- |((CFG_CS3_SYNC_PAGE_SIZE&0x03)<<22)\
- |((((CFG_CS3_SYNC_BURST_CLK_START+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)<<24)\
- |((CFG_CS3_SYNC_BURST_CLK_DIV&0x03)<<28))
-
-#define CFG_CS3L_VAL\
- ((CFG_CS3_CHIP_SELECT_ENABLE&0x01)\
- |((CFG_CS3_PIN_ASSERT&0x01)<<1)\
- |((CFG_CS3_WRITE_PROTECT&0x01)<<4)\
- |((CFG_CS3_SUPERVISOR_PROTECT&0x01)<<6)\
- |((CFG_CS3_DATA_PORT_SIZE&0x07)<<8)\
- |((CFG_CS3_EB_SIGNAL_CONTROL_WRITE&0x01)<<11)\
- |((((CFG_CS3_CS_ASSERT_NEG_DLY+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)<<12)\
- |(((((CFG_CS3_EB_NEG_DLY*2)+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)<<16)\
- |(((((CFG_CS3_EB_ASSERT_DLY*2)+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)<<20)\
- |(((((CFG_CS3_OE_NEG_DLY*2)+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)<<24)\
- |(((((CFG_CS3_OE_ASSERT_DLY*2)+CFG_HCLK_LGTH-1)/CFG_HCLK_LGTH)&0x0F)<<28))
-
-
-
-static void apf_isp116x_delay(struct device *dev, int delay)
-{
- /* On this platform, we work with 200MHz clock, giving
- 5 ns per instruction. The cycle below involves 2
- instructions and we lose 2 more instruction times due
- to pipeline flush at jump. I.e., we consume 20 ns
- per cycle.
- */
- int cyc = delay / 20;
-
- __asm__ volatile ("0:\n"
- " subs %0, %1, #1\n"
- " bge 0b\n"
- :"=r" (cyc)
- :"0"(cyc));
-}
-
-static struct isp116x_platform_data isp116x_pdata = {
- .sel15Kres = 1,
- .oc_enable = 1,
- .int_act_high = 0,
- .int_edge_triggered = 1,
- .remote_wakeup_enable = 1,
- .delay = apf_isp116x_delay,
-};
-
-static struct resource devfull_isp1761_resources[] = {
- [0] = {
- .name = "isp1761-regs",
- .start = ISP1761_BASE + 0x00000000,
- .end = ISP1761_BASE + 0x000fffff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = ISP1761_IRQ,
- .end = ISP1761_IRQ,
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct platform_device devfull_isp1761_device = {
- .name = "isp1761",
- .id = 0,
- .num_resources = ARRAY_SIZE(devfull_isp1761_resources),
- .resource = devfull_isp1761_resources,
- .dev = { .platform_data = &isp116x_pdata, },
-};
-
-static struct platform_device *devfull_isp1761_devices[] = {
- &devfull_isp1761_device,
-};
-
int __init devfull_isp1761_init(void)
-{
- unsigned int num_devices=ARRAY_SIZE(devfull_isp1761_devices);
- /* configure the chip select 3 */
- __REG(IMX_EIM_BASE + CS3U + IMX_IO_BASE) = CFG_CS3U_VAL; //CSU
- __REG(IMX_EIM_BASE + CS3L + IMX_IO_BASE) = CFG_CS3L_VAL; //CSL
- imx_gpio_mode( ISP1761_GPIO_IRQ | GPIO_IN | GPIO_GIUS ); /* Set up IRQ line. */
- set_irq_type( ISP1761_IRQ, IRQF_TRIGGER_FALLING );
-
- return platform_add_devices(devfull_isp1761_devices, num_devices);
+{
+ return 0;
}
void __exit devfull_isp1761_exit(void)
{
- platform_device_unregister(&devfull_isp1761_device);
}
module_init(devfull_isp1761_init);
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