[Armadeus-commitlog] SF.net SVN: armadeus:[960] trunk/target/linux/debug/imxssi
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[Armadeus-commitlog] SF.net SVN: armadeus:[960] trunk/target/linux/debug/imxssi
|
From: <ar...@us...> - 2008-12-15 16:37:22
|
Revision: 960
http://armadeus.svn.sourceforge.net/armadeus/?rev=960&view=rev
Author: artemys
Date: 2008-12-15 16:37:15 +0000 (Mon, 15 Dec 2008)
Log Message:
-----------
[DEBUG] imxssi: removes what imxregs is already doing (very well ;-) )
Modified Paths:
--------------
trunk/target/linux/debug/imxssi/Makefile
trunk/target/linux/debug/imxssi/imxssi.c
Removed Paths:
-------------
trunk/target/linux/debug/imxssi/imxregs.h
Modified: trunk/target/linux/debug/imxssi/Makefile
===================================================================
--- trunk/target/linux/debug/imxssi/Makefile 2008-12-15 15:19:39 UTC (rev 959)
+++ trunk/target/linux/debug/imxssi/Makefile 2008-12-15 16:37:15 UTC (rev 960)
@@ -1,9 +1,9 @@
-
-all: imxssi
-
-imxssi: imxssi.c imxregs.h
- arm-linux-gcc imxssi.c -O2 -lm -o $@
-
-clean:
- rm -f *.o
- rm -f imxssi
+
+all: imxssi
+
+imxssi: imxssi.c ../imxregs/imxregs.h
+ arm-linux-gcc imxssi.c -O2 -lm -o $@
+
+clean:
+ rm -f *.o
+ rm -f imxssi
Deleted: trunk/target/linux/debug/imxssi/imxregs.h
===================================================================
--- trunk/target/linux/debug/imxssi/imxregs.h 2008-12-15 15:19:39 UTC (rev 959)
+++ trunk/target/linux/debug/imxssi/imxregs.h 2008-12-15 16:37:15 UTC (rev 960)
@@ -1,541 +0,0 @@
-/*
- * imxregs.h - Tool to display and modify iMX registers from Linux's userspace
- *
- * Author/Maintainer: J. Boibessot
- * Derivated from pxaregs (c) Copyright 2002 by M&N Logistik-L�ungen Online GmbH
- *
- * This tool is placed under the GPL.
- *
-*/
-
-typedef unsigned int u32;
-
-struct reg_info {
- char *name;
- u32 addr;
- int shift;
- u32 mask;
- char type;
- char *desc;
-};
-
-
-static struct reg_info regs[] =
-{
-// RTC
-{ "HOURMIN", 0x00204000, 0, 0xffffffff, 'x', "RTC Hours and minutes counter register" },
-{ "SECONDS", 0x00204004, 0, 0xffffffff, 'x', "RTC Seconds counter register" },
-{ "ALRM_HM", 0x00204008, 0, 0xffffffff, 'x', "RTC Hours and minutes alarm register" },
-{ "ALRM_SEC", 0x0020400C, 0, 0xffffffff, 'x', "RTC Seconds alarm register" },
-{ "RCCTL", 0x00204010, 0, 0xffffffff, 'x', "RTC Control register" },
-{ "RTCIENR", 0x00204018, 0, 0xffffffff, 'x', "RTC Interrupt Enable register" },
-{ "STPWCH", 0x0020401C, 0, 0xffffffff, 'x', "RTC Stopwatch minutes register" },
-{ "DAYR", 0x00204020, 0, 0xffffffff, 'x', "RTC Days counter register" },
-{ "DAYALARM", 0x00204024, 0, 0xffffffff, 'x', "RTC Day Alarm register" },
-//LCD
-{ "SSA", 0x00205000, 0, 0xffffffff, 'x', "Screen Start Address Register" },
-{ "SIZE", 0x00205004, 0, 0xffffffff, 'x', "Size Register" },
-{ "VPW", 0x00205008, 0, 0xffffffff, 'x', "Virtual Page Width Register" },
-{ "CPOS", 0x0020500C, 0, 0xffffffff, 'x', "LCD Cursor Position Register" },
-{ "LCWHB", 0x00205010, 0, 0xffffffff, 'x', "LCD Cursor Width Height and Blink Register" },
-{ "LCHCC", 0x00205014, 0, 0xffffffff, 'x', "LCD Color Cursor Mapping Register" },
-{ "LPCR", 0x00205018, 0, 0xffffffff, 'x', "Panel Configuration Register" },
-{ "HCR", 0x0020501C, 0, 0xffffffff, 'x', "Horizontal Configuration Register" },
-{ "VCR", 0x00205020, 0, 0xffffffff, 'x', "Vertical Configuration Register" },
-{ "POS", 0x00205024, 0, 0xffffffff, 'x', "Panning Offset Register" },
-{ "LGPMR", 0x00205028, 0, 0xffffffff, 'x', "LCD Gray Palette Mapping Register" },
-{ "PWMR", 0x0020502C, 0, 0xffffffff, 'x', "PWM Contrast Control Register" },
-{ "DMACR", 0x00205030, 0, 0xffffffff, 'x', "DMA Control Register" },
-{ "RMCR", 0x00205034, 0, 0xffffffff, 'x', "Refresh Mode Control Register" },
-{ "LCDICR", 0x00205038, 0, 0xffffffff, 'x', "Interrupt Configuration Register" },
-{ "LCDISR", 0x00205040, 0, 0xffffffff, 'x', "Interrupt Status Register" },
-// UART
-{ "URX11D_2", 0x0020702C, 0, 0xffffffff, 'x', "UART2 Receiver Register 11" },
-{ "URX12D_2", 0x00207030, 0, 0xffffffff, 'x', "UART2 Receiver Register 12" },
-{ "URX13D_2", 0x00207034, 0, 0xffffffff, 'x', "UART2 Receiver Register 13" },
-{ "URX14D_2", 0x00207038, 0, 0xffffffff, 'x', "UART2 Receiver Register 14" },
-{ "URX15D_2", 0x0020703C, 0, 0xffffffff, 'x', "UART2 Receiver Register 15" },
-{ "UTX0D_2", 0X00207040, 0, 0xffffffff, 'x', "UART2 Transmitter Register 0" },
-{ "UTX1D_2", 0X00207044, 0, 0xffffffff, 'x', "UART2 Transmitter Register 1" },
-{ "UTX2D_2", 0X00207048, 0, 0xffffffff, 'x', "UART2 Transmitter Register 2" },
-{ "UTX3D_2", 0X0020704C, 0, 0xffffffff, 'x', "UART2 Transmitter Register 3" },
-{ "UTX4D_2", 0X00207050, 0, 0xffffffff, 'x', "UART2 Transmitter Register 4" },
-{ "UTX5D_2", 0X00207054, 0, 0xffffffff, 'x', "UART2 Transmitter Register 5" },
-{ "UTX6D_2", 0X00207058, 0, 0xffffffff, 'x', "UART2 Transmitter Register 6" },
-{ "UTX7D_2", 0X0020705C, 0, 0xffffffff, 'x', "UART2 Transmitter Register 7" },
-{ "UTX8D_2", 0X00207060, 0, 0xffffffff, 'x', "UART2 Transmitter Register 8" },
-{ "UTX9D_2", 0X00207064, 0, 0xffffffff, 'x', "UART2 Transmitter Register 9" },
-{ "UTX10D_2", 0X00207068, 0, 0xffffffff, 'x', "UART2 Transmitter Register 10" },
-{ "UTX11D_2", 0X0020706C, 0, 0xffffffff, 'x', "UART2 Transmitter Register 11" },
-{ "UTX12D_2", 0X00207070, 0, 0xffffffff, 'x', "UART2 Transmitter Register 12" },
-{ "UTX13D_2", 0X00207074, 0, 0xffffffff, 'x', "UART2 Transmitter Register 13" },
-{ "UTX14D_2", 0X00207078, 0, 0xffffffff, 'x', "UART2 Transmitter Register 14" },
-{ "UTX15D_2", 0X0020707C, 0, 0xffffffff, 'x', "UART2 Transmitter Register 15" },
-{ "UCR1_2", 0x00207080, 0, 0xffffffff, 'x', "UART2 Control Register 1" },
-{ "UCR2_2", 0x00207084, 0, 0xffffffff, 'x', "UART2 Control Register 2" },
-{ "UCR3_2", 0x00207088, 0, 0xffffffff, 'x', "UART2 Control Register 3" },
-{ "UCR4_2", 0x0020708C, 0, 0xffffffff, 'x', "UART2 Control Register 4" },
-{ "UFCR_2", 0x00207090, 0, 0xffffffff, 'x', "UART2 FIFO Control Register" },
-{ "USR1_2", 0x00207094, 0, 0xffffffff, 'x', "UART2 Status Register 1" },
-{ "USR2_2", 0x00207098, 0, 0xffffffff, 'x', "UART2 Status Register 2" },
-{ "UESC_2", 0x0020709C, 0, 0xffffffff, 'x', "UART2 Escape Character Register" },
-{ "UTIM_2", 0x002070A0, 0, 0xffffffff, 'x', "UART2 Escape Timer Register" },
-{ "UBIR_2", 0x002070A4, 0, 0xffffffff, 'x', "UART2 BRM Incremental Register" },
-{ "UBMR_2", 0x002070A8, 0, 0xffffffff, 'x', "UART2 BRM Modulator Register" },
-{ "UBRC_2", 0x002070AC, 0, 0xffffffff, 'x', "UART2 Baud Rate Count Register" },
-{ "BIPR1_2", 0x002070B0, 0, 0xffffffff, 'x', "UART2 BRM Incremental Preset Register 1" },
-{ "BIPR2_2", 0x002070B4, 0, 0xffffffff, 'x', "UART2 BRM Incremental Preset Register 2" },
-{ "BIPR3_2", 0x002070B8, 0, 0xffffffff, 'x', "UART2 BRM Incremental Preset Register 3" },
-{ "BIPR4_2", 0x002070BC, 0, 0xffffffff, 'x', "UART2 BRM Incremental Preset Register 4" },
-{ "BMPR1_2", 0x002070C0, 0, 0xffffffff, 'x', "UART2 BRM Modulator Preset Register 1" },
-{ "BMPR2_2", 0x002070C4, 0, 0xffffffff, 'x', "UART2 BRM Modulator Preset Register 2" },
-{ "BMPR3_2", 0x002070C8, 0, 0xffffffff, 'x', "UART2 BRM Modulator Preset Register 3" },
-{ "BMPR4_2", 0x002070CC, 0, 0xffffffff, 'x', "UART2 BRM Modulator Preset Register 4" },
-{ "UTS_2", 0x002070D0, 0, 0xffffffff, 'x', "UART2 Test Register 1" },
-// PWM
-{ "PWMC", 0x00208000, 0, 0xffffffff, 'x', "PWM Control Register" },
-{ "PWMS", 0x00208004, 0, 0xffffffff, 'x', "PWM Sample Register" },
-{ "PWMP", 0x00208008, 0, 0xffffffff, 'x', "PWM Period Register" },
-{ "PWMCNT", 0x0020800C, 0, 0xffffffff, 'x', "PWM Counter Register" },
-// DMA
-{ "DCR", 0x00209000, 0, 0xffffffff, 'x', "DMA Control Register" },
-{ "DISR", 0x00209004, 0, 0xffffffff, 'x', "DMA Interrupt Status Register" },
-{ "DIMR", 0x00209008, 0, 0xffffffff, 'x', "DMA Interrupt Mask Register" },
-{ "DBTOSR", 0x0020900C, 0, 0xffffffff, 'x', "DMA Burst Time-Out Status Register" },
-{ "DRTOSR", 0x00209010, 0, 0xffffffff, 'x', "DMA Request Time-Out Status Register" },
-{ "DSESR", 0x00209014, 0, 0xffffffff, 'x', "DMA Transfer Error Status Register" },
-{ "DBOSR", 0x00209018, 0, 0xffffffff, 'x', "DMA Buffer Overflow Status Register" },
-{ "DBTOCR", 0x0020901C, 0, 0xffffffff, 'x', "DMA Burst Time-Out Control Register" },
-{ "WSRA", 0x00209040, 0, 0xffffffff, 'x', "W-Size Register A" },
-{ "XSRA", 0x00209044, 0, 0xffffffff, 'x', "X-Size Register A" },
-{ "YSRA", 0x00209048, 0, 0xffffffff, 'x', "Y-Size Register A" },
-{ "WSRB", 0x0020904C, 0, 0xffffffff, 'x', "W-Size Register B" },
-{ "XSRB", 0x00209050, 0, 0xffffffff, 'x', "X-Size Register B" },
-{ "YSRB", 0x00209054, 0, 0xffffffff, 'x', "Y-Size Register B" },
-{ "SAR0", 0x00209080, 0, 0xffffffff, 'x', "Channel 0 Source Address Register" },
-{ "DAR0", 0x00209084, 0, 0xffffffff, 'x', "Channel 0 Destination Address Register" },
-{ "CNTR0", 0x00209088, 0, 0xffffffff, 'x', "Channel 0 Count Register" },
-{ "CCR0", 0x0020908C, 0, 0xffffffff, 'x', "Channel 0 Control Register" },
-{ "RSSR0", 0x00209090, 0, 0xffffffff, 'x', "Channel 0 Request Source Select Register" },
-{ "BLR0", 0x00209094, 0, 0xffffffff, 'x', "Channel 0 Burst Length Register" },
-{ "RTOR0", 0x00209098, 0, 0xffffffff, 'x', "Channel 0 Request Time-Out Register" },
-{ "BUCR0", 0x00209098, 0, 0xffffffff, 'x', "Channel 0 Bus Utilization Control Register" },
-{ "SAR1", 0x002090C0, 0, 0xffffffff, 'x', "Channel 1 Source Address Register" },
-{ "DAR1", 0x002090C4, 0, 0xffffffff, 'x', "Channel 1 Destination Address Register" },
-{ "CNTR1", 0x002090C8, 0, 0xffffffff, 'x', "Channel 1 Count Register" },
-{ "CCR1", 0x002090CC, 0, 0xffffffff, 'x', "Channel 1 Control Register" },
-{ "RSSR1", 0x002090D0, 0, 0xffffffff, 'x', "Channel 1 Request Source Select Register" },
-{ "BLR1", 0x002090D4, 0, 0xffffffff, 'x', "Channel 1 Burst Length Register" },
-{ "RTOR1", 0x002090D8, 0, 0xffffffff, 'x', "Channel 1 Request Time-Out Register" },
-{ "BUCR1", 0x002090D8, 0, 0xffffffff, 'x', "Channel 1 Bus Utilization Control Register" },
-{ "SAR2", 0x00209100, 0, 0xffffffff, 'x', "Channel 2 Source Address Register" },
-{ "DAR2", 0x00209104, 0, 0xffffffff, 'x', "Channel 2 Destination Address Register" },
-{ "CNTR2", 0x00209108, 0, 0xffffffff, 'x', "Channel 2 Count Register" },
-{ "CCR2", 0x0020910C, 0, 0xffffffff, 'x', "Channel 2 Control Register" },
-{ "RSSR2", 0x00209110, 0, 0xffffffff, 'x', "Channel 2 Request Source Select Register" },
-{ "BLR2", 0x00209114, 0, 0xffffffff, 'x', "Channel 2 Burst Length Register" },
-{ "RTOR2", 0x00209118, 0, 0xffffffff, 'x', "Channel 2 Request Time-Out Register" },
-{ "BUCR2", 0x00209118, 0, 0xffffffff, 'x', "Channel 2 Bus Utilization Control Register" },
-{ "SAR3", 0x00209140, 0, 0xffffffff, 'x', "Channel 3 Source Address Register" },
-{ "DAR3", 0x00209144, 0, 0xffffffff, 'x', "Channel 3 Destination Address Register" },
-{ "CNTR3", 0x00209148, 0, 0xffffffff, 'x', "Channel 3 Count Register" },
-{ "CCR3", 0x0020914C, 0, 0xffffffff, 'x', "Channel 3 Control Register" },
-{ "RSSR3", 0x00209150, 0, 0xffffffff, 'x', "Channel 3 Request Source Select Register" },
-{ "BLR3", 0x00209154, 0, 0xffffffff, 'x', "Channel 3 Burst Length Register" },
-{ "RTOR3", 0x00209158, 0, 0xffffffff, 'x', "Channel 3 Request Time-Out Register" },
-{ "BUCR3", 0x0020915C, 0, 0xffffffff, 'x', "Channel 3 Bus Utilization Control Register" },
-{ "SAR4", 0x00209180, 0, 0xffffffff, 'x', "Channel 4 Source Address Register" },
-{ "DAR4", 0x00209184, 0, 0xffffffff, 'x', "Channel 4 Destination Address Register" },
-{ "CNTR4", 0x00209188, 0, 0xffffffff, 'x', "Channel 4 Count Register" },
-{ "CCR4", 0x0020918C, 0, 0xffffffff, 'x', "Channel 4 Control Register" },
-{ "RSSR4", 0x00209190, 0, 0xffffffff, 'x', "Channel 4 Request Source Select Register" },
-{ "BLR4", 0x00209194, 0, 0xffffffff, 'x', "Channel 4 Burst Length Register" },
-{ "RTOR4", 0x00209198, 0, 0xffffffff, 'x', "Channel 4 Request Time-Out Register" },
-{ "BUCR4", 0x0020919C, 0, 0xffffffff, 'x', "Channel 4 Bus Utilization Control Register" },
-{ "SAR5", 0x002091C0, 0, 0xffffffff, 'x', "Channel 5 Source Address Register" },
-{ "DAR5", 0x002091C4, 0, 0xffffffff, 'x', "Channel 5 Destination Address Register" },
-{ "CNTR5", 0x002091C8, 0, 0xffffffff, 'x', "Channel 5 Count Register" },
-{ "CCR5", 0x002091CC, 0, 0xffffffff, 'x', "Channel 5 Control Register" },
-{ "RSSR5", 0x002091D0, 0, 0xffffffff, 'x', "Channel 5 Request Source Select Register" },
-{ "BLR5", 0x002091D4, 0, 0xffffffff, 'x', "Channel 5 Burst Length Register" },
-{ "RTOR5", 0x002091D8, 0, 0xffffffff, 'x', "Channel 5 Request Time-Out Register" },
-{ "BUCR5", 0x002091DC, 0, 0xffffffff, 'x', "Channel 5 Bus Utilization Control Register" },
-{ "SAR6", 0x00209200, 0, 0xffffffff, 'x', "Channel 6 Source Address Register" },
-{ "DAR6", 0x00209204, 0, 0xffffffff, 'x', "Channel 6 Destination Address Register" },
-{ "CNTR6", 0x00209208, 0, 0xffffffff, 'x', "Channel 6 Count Register" },
-{ "CCR6", 0x0020920C, 0, 0xffffffff, 'x', "Channel 6 Control Register" },
-{ "RSSR6", 0x00209210, 0, 0xffffffff, 'x', "Channel 6 Request Source Select Register" },
-{ "BLR6", 0x00209214, 0, 0xffffffff, 'x', "Channel 6 Burst Length Register" },
-{ "RTOR6", 0x00209218, 0, 0xffffffff, 'x', "Channel 6 Request Time-Out Register" },
-{ "BUCR6", 0x00209218, 0, 0xffffffff, 'x', "Channel 6 Bus Utilization Control Register" },
-{ "SAR7", 0x00209240, 0, 0xffffffff, 'x', "Channel 7 Source Address Register" },
-{ "DAR7", 0x00209244, 0, 0xffffffff, 'x', "Channel 7 Destination Address Register" },
-{ "CNTR7", 0x00209248, 0, 0xffffffff, 'x', "Channel 7 Count Register" },
-{ "CCR7", 0x0020924C, 0, 0xffffffff, 'x', "Channel 7 Control Register" },
-{ "RSSR7", 0x00209250, 0, 0xffffffff, 'x', "Channel 7 Request Source Select Register" },
-{ "BLR7", 0x00209254, 0, 0xffffffff, 'x', "Channel 7 Burst Length Register" },
-{ "RTOR7", 0x00209258, 0, 0xffffffff, 'x', "Channel 7 Request Time-Out Register" },
-{ "BUCR7", 0x00209258, 0, 0xffffffff, 'x', "Channel 7 Bus Utilization Control Register" },
-{ "SAR8", 0x00209280, 0, 0xffffffff, 'x', "Channel 8 Source Address Register" },
-{ "DAR8", 0x00209284, 0, 0xffffffff, 'x', "Channel 8 Destination Address Register" },
-{ "CNTR8", 0x00209288, 0, 0xffffffff, 'x', "Channel 8 Count Register" },
-{ "CCR8", 0x0020928C, 0, 0xffffffff, 'x', "Channel 8 Control Register" },
-{ "RSSR8", 0x00209290, 0, 0xffffffff, 'x', "Channel 8 Request Source Select Register" },
-{ "BLR8", 0x00209294, 0, 0xffffffff, 'x', "Channel 8 Burst Length Register" },
-{ "RTOR8", 0x00209298, 0, 0xffffffff, 'x', "Channel 8 Request Time-Out Register" },
-{ "BUCR8", 0x00209298, 0, 0xffffffff, 'x', "Channel 8 Bus Utilization Control Register" },
-{ "SAR9", 0x002092C0, 0, 0xffffffff, 'x', "Channel 9 Source Address Register" },
-{ "DAR9", 0x002092C4, 0, 0xffffffff, 'x', "Channel 9 Destination Address Register" },
-{ "CNTR9", 0x002092C8, 0, 0xffffffff, 'x', "Channel 9 Count Register" },
-{ "CCR9", 0x002092CC, 0, 0xffffffff, 'x', "Channel 9 Control Register" },
-{ "RSSR9", 0x002092D0, 0, 0xffffffff, 'x', "Channel 9 Request Source Select Register" },
-{ "BLR9", 0x002092D4, 0, 0xffffffff, 'x', "Channel 9 Burst Length Register" },
-{ "RTOR9", 0x002092D8, 0, 0xffffffff, 'x', "Channel 9 Request Time-Out Register" },
-{ "BUCR9", 0x002092DC, 0, 0xffffffff, 'x', "Channel 9 Bus Utilization Control Register" },
-{ "SAR10", 0x00209300, 0, 0xffffffff, 'x', "Channel 10 Source Address Register" },
-{ "DAR10", 0x00209304, 0, 0xffffffff, 'x', "Channel 10 Destination Address Register" },
-{ "CNTR10", 0x00209308, 0, 0xffffffff, 'x', "Channel 10 Count Register" },
-// NOT ACCESSIBLE IN USER MODE ??
-/*{ "PSR0_2", 0x00210000, 0, 0xffffffff, 'x', "AIPI2 Peripheral Size Register 0" },
-{ "PSR1_2", 0x00210004, 0, 0xffffffff, 'x', "AIPI2 Peripheral Size Register 1" },
-{ "PAR_2", 0x00210008, 0, 0xffffffff, 'x', "AIPI2 Peripheral Access Register" },
-{ "PCR_2", 0x0021000C, 0, 0xffffffff, 'x', "AIPI2 Peripheral Control Register" },
-{ "TSR_2", 0x00210010, 0, 0xffffffff, 'x', "AIPI2 Time-Out Status Register" },*/
-// USB
-{ "USB_FRAME", 0x00212000, 0, 0xffffffff, 'x', "USB Frame Number and Match Register" },
-{ "USB_SPEC", 0x00212004, 0, 0xffffffff, 'x', "USB Specification and Release Number Register" },
-{ "USB_STAT", 0x00212008, 0, 0xffffffff, 'x', "USB Status Register" },
-{ "USB_CTRL", 0x0021200C, 0, 0xffffffff, 'x', "USB Control Register" },
-{ "USB_DADR", 0x00212010, 0, 0xffffffff, 'x', "USB Descriptor RAM Address Register" },
-{ "USB_DDAT", 0x00212014, 0, 0xffffffff, 'x', "USB Descriptor RAM/Endpoint Buffer Data Register" },
-{ "USB_INTR", 0x00212018, 0, 0xffffffff, 'x', "USB Interrupt Status Register" },
-{ "USB_MASK", 0x0021201C, 0, 0xffffffff, 'x', "USB Interrupt Mask Register" },
-{ "USB_MCTL", 0x00212020, 0, 0xffffffff, 'x', "USB FIFO Memory Control Register" },
-{ "USB_ENAB", 0x00212024, 0, 0xffffffff, 'x', "USB Enable Register" },
-{ "USB_EP0_STAT", 0x00212030, 0, 0xffffffff, 'x', "Endpoint 0 Status/Control Register" },
-{ "USB_EP0_INTR", 0x00212034, 0, 0xffffffff, 'x', "Endpoint 0 Interrupt Status Register" },
-{ "USB_EP0_MASK", 0x00212038, 0, 0xffffffff, 'x', "Endpoint 0 Interrupt Mask Register" },
-{ "USB_EP0_FDAT", 0x0021203C, 0, 0xffffffff, 'x', "Endpoint 0 FIFO Data Register" },
-{ "USB_EP0_FSTAT", 0x00212040, 0, 0xffffffff, 'x', "Endpoint 0 FIFO Status Register" },
-{ "USB_EP0_FCTRL", 0x00212044, 0, 0xffffffff, 'x', "Endpoint 0 FIFO Control Register" },
-{ "USB_EP0_LRFP", 0x00212048, 0, 0xffffffff, 'x', "Endpoint 0 Last Read Frame Pointer Register" },
-{ "USB_EP0_LWFP", 0x0021204C, 0, 0xffffffff, 'x', "Endpoint 0 Last Write Frame Pointer Register" },
-{ "USB_EP0_FALRM", 0x00212050, 0, 0xffffffff, 'x', "Endpoint 0 FIFO Alarm Register" },
-{ "USB_EP0_FRDP", 0x00212054, 0, 0xffffffff, 'x', "Endpoint 0 FIFO Read Pointer Register" },
-{ "USB_EP0_FWRP", 0x00212058, 0, 0xffffffff, 'x', "Endpoint 0 FIFO Write Pointer Register" },
-{ "USB_EP1_STAT", 0x00212060, 0, 0xffffffff, 'x', "Endpoint 1 Status/Control Register" },
-{ "USB_EP1_INTR", 0x00212064, 0, 0xffffffff, 'x', "Endpoint 1 Interrupt Status Register" },
-{ "USB_EP1_MASK", 0x00212068, 0, 0xffffffff, 'x', "Endpoint 1 Interrupt Mask Register" },
-{ "USB_EP1_FDAT", 0x0021206C, 0, 0xffffffff, 'x', "Endpoint 1 FIFO Data Register" },
-{ "USB_EP1_FSTAT", 0x00212070, 0, 0xffffffff, 'x', "Endpoint 1 FIFO Status Register" },
-{ "USB_EP1_FCTRL", 0x00212074, 0, 0xffffffff, 'x', "Endpoint 1 FIFO Control Register" },
-{ "USB_EP1_LRFP", 0x00212078, 0, 0xffffffff, 'x', "Endpoint 1 Last Read Frame Pointer Register" },
-{ "USB_EP1_LWFP", 0x0021207C, 0, 0xffffffff, 'x', "Endpoint 1 Last Write Frame Pointer Register" },
-{ "USB_EP1_FALRM", 0x00212080, 0, 0xffffffff, 'x', "Endpoint 1 FIFO Alarm Register" },
-{ "USB_EP1_FRDP", 0x00212084, 0, 0xffffffff, 'x', "Endpoint 1 FIFO Read Pointer Register" },
-{ "USB_EP1_FWRP", 0x00212088, 0, 0xffffffff, 'x', "Endpoint 1 FIFO Write Pointer Register" },
-{ "USB_EP2_STAT", 0x00212090, 0, 0xffffffff, 'x', "Endpoint 2 Status/Control Register" },
-{ "USB_EP2_INTR", 0x00212094, 0, 0xffffffff, 'x', "Endpoint 2 Interrupt Status Register" },
-{ "USB_EP2_MASK", 0x00212098, 0, 0xffffffff, 'x', "Endpoint 2 Interrupt Mask Register" },
-{ "USB_EP2_FDAT", 0x0021209C, 0, 0xffffffff, 'x', "Endpoint 2 FIFO Data Register" },
-{ "USB_EP2_FSTAT", 0x002120A0, 0, 0xffffffff, 'x', "Endpoint 2 FIFO Status Register" },
-{ "USB_EP2_FCTRL", 0x002120A4, 0, 0xffffffff, 'x', "Endpoint 2 FIFO Control Register" },
-{ "USB_EP2_LRFP", 0x002120A8, 0, 0xffffffff, 'x', "Endpoint 2 Last Read Frame Pointer Register" },
-{ "USB_EP2_LWFP", 0x002120AC, 0, 0xffffffff, 'x', "Endpoint 2 Last Write Frame Pointer Register" },
-{ "USB_EP2_FALRM", 0x002120B0, 0, 0xffffffff, 'x', "Endpoint 2 FIFO Alarm Register" },
-{ "USB_EP2_FRDP", 0x002120B4, 0, 0xffffffff, 'x', "Endpoint 2 FIFO Read Pointer Register" },
-{ "USB_EP2_FWRP", 0x002120B8, 0, 0xffffffff, 'x', "Endpoint 2 FIFO Write Pointer Register" },
-{ "USB_EP3_STAT", 0x002120C0, 0, 0xffffffff, 'x', "Endpoint 3 Status/Control Register" },
-{ "USB_EP3_INTR", 0x002120C4, 0, 0xffffffff, 'x', "Endpoint 3 Interrupt Status Register" },
-{ "USB_EP3_MASK", 0x002120C8, 0, 0xffffffff, 'x', "Endpoint 3 Interrupt Mask Register" },
-{ "USB_EP3_FDAT", 0x002120CC, 0, 0xffffffff, 'x', "Endpoint 3 FIFO Data Register" },
-{ "USB_EP3_FSTAT", 0x002120D0, 0, 0xffffffff, 'x', "Endpoint 3 FIFO Status Register" },
-{ "USB_EP3_FCTRL", 0x002120D4, 0, 0xffffffff, 'x', "Endpoint 3 FIFO Control Register" },
-{ "USB_EP3_LRFP", 0x002120D8, 0, 0xffffffff, 'x', "Endpoint 3 Last Read Frame Pointer Register" },
-{ "USB_EP3_LWFP", 0x002120DC, 0, 0xffffffff, 'x', "Endpoint 3 Last Write Frame Pointer Register" },
-{ "USB_EP3_FALRM", 0x002120E0, 0, 0xffffffff, 'x', "Endpoint 3 FIFO Alarm Register" },
-{ "USB_EP3_FRDP", 0x002120E4, 0, 0xffffffff, 'x', "Endpoint 3 FIFO Read Pointer Register" },
-{ "USB_EP3_FWRP", 0x002120E8, 0, 0xffffffff, 'x', "Endpoint 3 FIFO Write Pointer Register" },
-{ "USB_EP4_STAT", 0x002120F0, 0, 0xffffffff, 'x', "Endpoint 4 Status/Control Register" },
-{ "USB_EP4_INTR", 0x002120F4, 0, 0xffffffff, 'x', "Endpoint 4 Interrupt Status Register" },
-{ "USB_EP4_MASK", 0x002120F8, 0, 0xffffffff, 'x', "Endpoint 4 Interrupt Mask Register" },
-{ "USB_EP4_FDAT", 0x002120FC, 0, 0xffffffff, 'x', "Endpoint 4 FIFO Data Register" },
-{ "USB_EP4_FSTAT", 0x00212100, 0, 0xffffffff, 'x', "Endpoint 4 FIFO Status Register" },
-{ "USB_EP4_FCTRL", 0x00212104, 0, 0xffffffff, 'x', "Endpoint 4 FIFO Control Register" },
-{ "USB_EP4_LRFP", 0x00212108, 0, 0xffffffff, 'x', "Endpoint 4 Last Read Frame Pointer Register" },
-{ "USB_EP4_LWFP", 0x0021210C, 0, 0xffffffff, 'x', "Endpoint 4 Last Write Frame Pointer Register" },
-{ "USB_EP4_FALRM", 0x00212110, 0, 0xffffffff, 'x', "Endpoint 4 FIFO Alarm Register" },
-{ "USB_EP4_FRDP", 0x00212114, 0, 0xffffffff, 'x', "Endpoint 4 FIFO Read Pointer Register" },
-{ "USB_EP4_FWRP", 0x00212118, 0, 0xffffffff, 'x', "Endpoint 4 FIFO Write Pointer Register" },
-{ "USB_EP5_STAT", 0x00212120, 0, 0xffffffff, 'x', "Endpoint 5 Status/Control Register" },
-{ "USB_EP5_INTR", 0x00212124, 0, 0xffffffff, 'x', "Endpoint 5 Interrupt Status Register" },
-{ "USB_EP5_MASK", 0x00212128, 0, 0xffffffff, 'x', "Endpoint 5 Interrupt Mask Register" },
-{ "USB_EP5_FDAT", 0x0021212C, 0, 0xffffffff, 'x', "Endpoint 5 FIFO Data Register" },
-{ "USB_EP5_FSTAT", 0x00212130, 0, 0xffffffff, 'x', "Endpoint 5 FIFO Status Register" },
-{ "USB_EP5_FCTRL", 0x00212134, 0, 0xffffffff, 'x', "Endpoint 5 FIFO Control Register" },
-{ "USB_EP5_LRFP", 0x00212138, 0, 0xffffffff, 'x', "Endpoint 5 Last Read Frame Pointer Register" },
-{ "USB_EP5_LWFP", 0x0021213C, 0, 0xffffffff, 'x', "Endpoint 5 Last Write Frame Pointer Register" },
-{ "USB_EP5_FALRM", 0x00212140, 0, 0xffffffff, 'x', "Endpoint 5 FIFO Alarm Register" },
-{ "USB_EP5_FRDP", 0x00212144, 0, 0xffffffff, 'x', "Endpoint 5 FIFO Read Pointer Register" },
-{ "USB_EP5_FWRP", 0x00212148, 0, 0xffffffff, 'x', "Endpoint 5 FIFO Write Pointer Register" },
-// SPI
-{ "RXDATAREG1", 0x00213000, 0, 0xffffffff, 'x', "SPI 1 Rx Data Register" },
-{ "TXDATAREG1", 0x00213004, 0, 0xffffffff, 'x', "SPI 1 Tx Data Register" },
-{ "CONTROLREG1", 0x00213008, 0, 0xffffffff, 'x', "SPI 1 Control Register" },
-{ "INTREG1", 0x0021300C, 0, 0xffffffff, 'x', "SPI 1 Interrupt Control/Status Register" },
-{ "TESTREG1", 0x00213010, 0, 0xffffffff, 'x', "SPI 1 Test Register" },
-{ "PERIODREG1", 0x00213014, 0, 0xffffffff, 'x', "SPI 1 Sample Period Control Register" },
-{ "DMAREG1", 0x00213018, 0, 0xffffffff, 'x', "SPI 1 DMA Control Register" },
-{ "RESETREG1", 0x0021301C, 0, 0xffffffff, 'x', "SPI 1 Soft Reset Register" },
-// MMC
-{ "STR_STP_CLK", 0x00214000, 0, 0xffffffff, 'x', "MMC/SD Clock Control Register" },
-{ "STR_STP_CLK_ENDIAN", 0x00214000, 5, 1, 'x', "ENDIAN FIFO Mode Selection: setting this bit selects the Endian mode of the FIFO." },
-{ "STR_STP_CLK_RESET", 0x00214000, 3, 1, 'x', "Resets the MMC/SD module. 1 = Reset the MMC/SD module" },
-{ "STR_STP_CLK_ENABLE", 0x00214000, 2, 1, 'x', "Enables/Disables the MMC/SD module. When the module is disabled, the clock source and all internal operations are halted." },
-{ "STR_STP_CLK_START", 0x00214000, 1, 1, 'x', "1 = MMC/SD clock active" },
-{ "STR_STP_CLK_STOP", 0x00214000, 0, 1, 'x', "1 = MMC/SD clock stopped" },
-{ "STATUS", 0x00214004, 0, 0xffffffff, 'x', "MMC/SD Status Register" },
-{ "STATUS_CARD_PRESENCE", 0x00214004, 15, 1, 'x', "1 = At least 1 card is present" },
-{ "STATUS_SDIO_INT_ACTIVE", 0x00214004, 14, 1, 'x', "1 = Interrupt detected via SDIO card bus" },
-{ "STATUS_END_CMD_RESP", 0x00214004, 13, 1, 'x', "1 = Command transmitted successfully (response received)" },
-{ "STATUS_WRITE_OP_DONE", 0x00214004, 12, 1, 'x', "1 = Write operation complete" },
-{ "STATUS_DATA_TRANS_DONE", 0x00214004, 11, 1, 'x', "1 = Data transfer complete" },
-{ "STATUS_WR_CRC_ERROR_CODE", 0x00214004, 9, 3, 'x', "00 = No transmission error, CRC status is 010 (positive)" },
-{ "STATUS_CARD_BUS_CLK_RUN", 0x00214004, 8, 1, 'x', "1 = MMC/SD clock is running" },
-{ "STATUS_APPL_BUFF_FF", 0x00214004, 7, 1, 'x', "1 = Buffer is full" },
-{ "STATUS_APPL_BUFF_FE", 0x00214004, 6, 1, 'x', "1 = Buffer is empty" },
-{ "STATUS_RESP_CRC_ERR", 0x00214004, 5, 1, 'x', "1 = Response CRC error occurred" },
-{ "STATUS_CRC_READ_ERR", 0x00214004, 3, 1, 'x', "1 = CRC read error occurred" },
-{ "STATUS_CRC_WRITE_ERR", 0x00214004, 2, 1, 'x', "1 = CRC write error occurred" },
-{ "STATUS_TIME_OUT_RESP", 0x00214004, 1, 1, 'x', "1 = Time-out response error occurred" },
-{ "STATUS_TIME_OUT_READ", 0x00214004, 0, 1, 'x', "1 = Time-out read data error occurred" },
-{ "CLK_RATE", 0x00214008, 0, 0xffffffff, 'x', "MMC/SD Clock Rate Register" },
-{ "CLK_RATE_PRESCALER", 0x00214008, 3, 0x00000007, 'x', "Specifies the divider value to generate CLK_20M." },
-{ "CLK_RATE_DIV", 0x00214008, 0, 0x00000007, 'x', "Specifies the divider value to generate CLK_DIV" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-/*{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },
-{ "CMD_DAT_CONT", 0x0021400C, 0, 0xffffffff, 'x', "MMC/SD Command and Data Control Register" },*/
-{ "RES_TO", 0x00214010, 0, 0xffffffff, 'x', "MMC/SD Response Time Out Register" },
-{ "READ_TO", 0x00214014, 0, 0xffffffff, 'x', "MMC/SD Read Time Out Register" },
-{ "BLK_LEN", 0x00214018, 0, 0xffffffff, 'x', "MMC/SD Block Length Register" },
-{ "NOB", 0x0021401C, 0, 0xffffffff, 'x', "MMC/SD Number of Blocks Register" },
-{ "REV_NO", 0x00214020, 0, 0xffffffff, 'x', "MMC/SD Revision Number Register" },
-{ "INT_MASK", 0x00214024, 0, 0xffffffff, 'x', "MMC/SD Interrupt Mask Register" },
-{ "CMD", 0x00214028, 0, 0xffffffff, 'x', "MMC/SD Command Number Register" },
-{ "ARGH", 0x0021402C, 0, 0xffffffff, 'x', "MMC/SD Higher Argument Register" },
-{ "ARGL", 0x00214030, 0, 0xffffffff, 'x', "MMC/SD Lower Argument Register" },
-{ "RES_FIFO", 0x00214034, 0, 0xffffffff, 'x', "MMC/SD Response FIFO Register" },
-{ "BUFFER_ACCESS", 0x00214038, 0, 0xffffffff, 'x', "MMC/SD Buffer Access Register" },
-// I2C
-{ "IADR", 0x00217000, 0, 0xffffffff, 'x', "I2C Address Register" },
-{ "IFDR", 0x00217004, 0, 0xffffffff, 'x', "I2C Frequency Divider Register" },
-{ "I2CR", 0x00217008, 0, 0xffffffff, 'x', "I2C Control Register" },
-{ "I2CSR", 0x0021700C, 0, 0xffffffff, 'x', "I2C Status Register" },
-{ "I2DR", 0x00217010, 0, 0xffffffff, 'x', "I2C Data I/O Register" },
-// SSI
-{ "STX", 0x00218000, 0, 0xffffffff, 'x', "SSI Transmit Data Register" },
-{ "SRX", 0x00218004, 0, 0xffffffff, 'x', "SSI Receive Data Register" },
-{ "SCSR", 0x00218008, 0, 0xffffffff, 'x', "SSI Control/Status Register" },
-{ "STCR", 0x0021800C, 0, 0xffffffff, 'x', "SSI Transmit Configuration Register" },
-{ "SRCR", 0x00218010, 0, 0xffffffff, 'x', "SSI Receive Configuration Register" },
-{ "STCCR", 0x00218014, 0, 0xffffffff, 'x', "SSI Transmit Clock Control Register" },
-{ "SRCCR", 0x00218018, 0, 0xffffffff, 'x', "SSI Receive Clock Control Register" },
-{ "STSR", 0x0021801C, 0, 0xffffffff, 'x', "SSI Time Slot Register" },
-{ "SFCSR", 0x00218020, 0, 0xffffffff, 'x', "SSI FIFO Control/Status Register" },
-{ "SOR", 0x00218028, 0, 0xffffffff, 'x', "SSI Option Register" },
-// SPI
-{ "RXDATAREG2", 0x00219000, 0, 0xffffffff, 'x', "SPI 2 Rx Data Register" },
-{ "TXDATAREG2", 0x00219004, 0, 0xffffffff, 'x', "SPI 2 Tx Data Register" },
-{ "CONTROLREG2", 0x00219008, 0, 0xffffffff, 'x', "SPI 2 Control Register" },
-{ "INTREG2", 0x0021900C, 0, 0xffffffff, 'x', "SPI 2 Interrupt Control/Status Register" },
-{ "TESTREG2", 0x00219010, 0, 0xffffffff, 'x', "SPI 2 Test Register" },
-{ "PERIODREG2", 0x00219014, 0, 0xffffffff, 'x', "SPI 2 Sample Period Control Register" },
-{ "DMAREG2", 0x00219018, 0, 0xffffffff, 'x', "SPI 2 DMA Control Register" },
-{ "RESETREG2", 0x0021901C, 0, 0xffffffff, 'x', "SPI 2 Soft Reset Register" },
-// MS
-{ "MSCMD", 0x0021A000, 0, 0xffffffff, 'x', "Memory Stick Command Register" },
-{ "MSCS", 0x0021A002, 0, 0xffffffff, 'x', "Memory Stick Control/Status Register" },
-{ "MSTDATA", 0x0021A004, 0, 0xffffffff, 'x', "Memory Stick Transmit FIFO Data Register" },
-{ "MSRDATA", 0x0021A004, 0, 0xffffffff, 'x', "Memory Stick Receive FIFO Data Register" },
-{ "MSICS", 0x0021A006, 0, 0xffffffff, 'x', "Memory Stick Interrupt Control/Status Register" },
-{ "MSPPCD", 0x0021A008, 0, 0xffffffff, 'x', "Memory Stick Parallel Port Control/Data Register" },
-{ "MSC2", 0x0021A00A, 0, 0xffffffff, 'x', "Memory Stick Control 2 Register" },
-{ "MSACD", 0x0021A00C, 0, 0xffffffff, 'x', "Memory Stick Auto Command Register" },
-{ "MSFAECS", 0x0021A00E, 0, 0xffffffff, 'x', "Memory Stick FIFO Access Error Control/Status Register" },
-{ "MSCLKD", 0x0021A010, 0, 0xffffffff, 'x', "Memory Stick Serial Clock Divider Register" },
-{ "MSDRQC", 0x0021A012, 0, 0xffffffff, 'x', "Memory Stick DMA Request Control Register" },
-//
-{ "CSCR", 0x0021B000, 0, 0xffffffff, 'x', "Clock Source Control Register" },
-{ "MPCTL0", 0x0021B004, 0, 0xffffffff, 'x', "MCU PLL Control Register 0" },
-{ "MPCTL1", 0x0021B008, 0, 0xffffffff, 'x', "MCU PLL and System Clock Control Register 1" },
-{ "SPCTL0", 0x0021B00C, 0, 0xffffffff, 'x', "System PLL Control Register 0" },
-{ "SPCTL1", 0x0021B010, 0, 0xffffffff, 'x', "System PLL Control Register 1" },
-{ "PCDR", 0x0021B020, 0, 0xffffffff, 'x', "Peripheral Clock Divider Register" },
-{ "RSR", 0x0021B800, 0, 0xffffffff, 'x', "Reset Source Register" },
-{ "SIDR", 0x0021B804, 0, 0xffffffff, 'x', "Silicon ID Register" },
-{ "FMCR", 0x0021B808, 0, 0xffffffff, 'x', "Function Multiplexing Control Register" },
-{ "GPCR", 0x0021B80C, 0, 0xffffffff, 'x', "Global Peripheral Control Register" },
-{ "GCCR", 0x0021B810, 0, 0xffffffff, 'x', "Global Clock Control Register" },
-{ "DDIR_A", 0x0021C000, 0, 0xffffffff, 'x', "Port A Data Direction Register" },
-{ "OCR1_A", 0x0021C004, 0, 0xffffffff, 'x', "Port A Output Configuration Register 1" },
-{ "OCR2_A", 0x0021C008, 0, 0xffffffff, 'x', "Port A Output Configuration Register 2" },
-{ "ICONFA1_A", 0x0021C00C, 0, 0xffffffff, 'x', "Port A Input Configuration Register A1" },
-{ "ICONFA2_A", 0x0021C010, 0, 0xffffffff, 'x', "Port A Input Configuration Register A2" },
-{ "ICONFB1_A", 0x0021C014, 0, 0xffffffff, 'x', "Port A Input Configuration Register B1" },
-{ "ICONFB2_A", 0x0021C018, 0, 0xffffffff, 'x', "Port A Input Configuration Register B2" },
-{ "DR_A", 0x0021C01C, 0, 0xffffffff, 'x', "Port A Data Register" },
-{ "GIUS_A", 0x0021C020, 0, 0xffffffff, 'x', "Port A GPIO In Use Register" },
-{ "SSR_A", 0x0021C024, 0, 0xffffffff, 'x', "Port A Sample Status Register" },
-{ "ICR1_A", 0x0021C028, 0, 0xffffffff, 'x', "Port A Interrupt Configuration Register 1" },
-{ "ICR2_A", 0x0021C02C, 0, 0xffffffff, 'x', "Port A Interrupt Configuration Register 2" },
-{ "IMR_A", 0x0021C030, 0, 0xffffffff, 'x', "Port A Interrupt Mask Register" },
-{ "ISR_A", 0x0021C034, 0, 0xffffffff, 'x', "Port A Interrupt Status Register" },
-{ "GPR_A", 0x0021C038, 0, 0xffffffff, 'x', "Port A General Purpose Register" },
-{ "SWR_A", 0x0021C03C, 0, 0xffffffff, 'x', "Port A Software Reset Register" },
-{ "PUEN_A", 0x0021C040, 0, 0xffffffff, 'x', "Port A Pull_Up Enable Register" },
-{ "DDIR_B", 0x0021C100, 0, 0xffffffff, 'x', "Port B Data Direction Register" },
-{ "OCR1_B", 0x0021C104, 0, 0xffffffff, 'x', "Port B Output Configuration Register 1" },
-{ "OCR2_B", 0x0021C108, 0, 0xffffffff, 'x', "Port B Output Configuration Register 2" },
-{ "ICONFA1_B", 0x0021C10C, 0, 0xffffffff, 'x', "Port B Input Configuration Register A1" },
-{ "ICONFA2_B", 0x0021C110, 0, 0xffffffff, 'x', "Port B Input Configuration Register A2" },
-{ "ICONFB1_B", 0x0021C114, 0, 0xffffffff, 'x', "Port B Input Configuration Register B1" },
-{ "ICONFB2_B", 0x0021C118, 0, 0xffffffff, 'x', "Port B Input Configuration Register B2" },
-{ "DR_B", 0x0021C11C, 0, 0xffffffff, 'x', "Port B Data Register" },
-{ "GIUS_B", 0x0021C120, 0, 0xffffffff, 'x', "Port B GPIO In Use Register" },
-{ "SSR_B", 0x0021C124, 0, 0xffffffff, 'x', "Port B Sample Status Register" },
-{ "ICR1_B", 0x0021C128, 0, 0xffffffff, 'x', "Port B Interrupt Configuration Register 1" },
-{ "ICR2_B", 0x0021C12C, 0, 0xffffffff, 'x', "Port B Interrupt Configuration Register 2" },
-{ "IMR_B", 0x0021C130, 0, 0xffffffff, 'x', "Port B Interrupt Mask Register" },
-{ "ISR_B", 0x0021C134, 0, 0xffffffff, 'x', "Port B Interrupt Status Register" },
-{ "GPR_B", 0x0021C138, 0, 0xffffffff, 'x', "Port B General Purpose Register" },
-{ "SWR_B", 0x0021C13C, 0, 0xffffffff, 'x', "Port B Software Reset Register" },
-{ "PUEN_B", 0x0021C140, 0, 0xffffffff, 'x', "Port B Pull_Up Enable Register" },
-{ "DDIR_C", 0x0021C200, 0, 0xffffffff, 'x', "Port C Data Direction Register" },
-{ "OCR1_C", 0x0021C204, 0, 0xffffffff, 'x', "Port C Output Configuration Register 1" },
-{ "OCR2_C", 0x0021C208, 0, 0xffffffff, 'x', "Port C Output Configuration Register 2" },
-{ "ICONFA1_C", 0x0021C20C, 0, 0xffffffff, 'x', "Port C Input Configuration Register A1" },
-{ "ICONFA2_C", 0x0021C210, 0, 0xffffffff, 'x', "Port C Input Configuration Register A2" },
-{ "ICONFB1_C", 0x0021C214, 0, 0xffffffff, 'x', "Port C Input Configuration Register B1" },
-{ "ICONFB2_C", 0x0021C218, 0, 0xffffffff, 'x', "Port C Input Configuration Register B2" },
-{ "DR_C", 0x0021C21C, 0, 0xffffffff, 'x', "Port C Data Register" },
-{ "GIUS_C", 0x0021C220, 0, 0xffffffff, 'x', "Port C GPIO In Use Register" },
-{ "SSR_C", 0x0021C224, 0, 0xffffffff, 'x', "Port C Sample Status Register" },
-{ "ICR1_C", 0x0021C228, 0, 0xffffffff, 'x', "Port C Interrupt Configuration Register 1" },
-{ "ICR2_C", 0x0021C22C, 0, 0xffffffff, 'x', "Port C Interrupt Configuration Register 2" },
-{ "IMR_C", 0x0021C230, 0, 0xffffffff, 'x', "Port C Interrupt Mask Register" },
-{ "ISR_C", 0x0021C234, 0, 0xffffffff, 'x', "Port C Interrupt Status Register" },
-{ "GPR_C", 0x0021C238, 0, 0xffffffff, 'x', "Port C General Purpose Register" },
-{ "SWR_C", 0x0021C23C, 0, 0xffffffff, 'x', "Port C Software Reset Register" },
-{ "PUEN_C", 0x0021C240, 0, 0xffffffff, 'x', "Port C Pull_Up Enable Register" },
-{ "DDIR_D", 0x0021C300, 0, 0xffffffff, 'x', "Port D Data Direction Register" },
-{ "OCR1_D", 0x0021C304, 0, 0xffffffff, 'x', "Port D Output Configuration Register 1" },
-{ "OCR2_D", 0x0021C308, 0, 0xffffffff, 'x', "Port D Output Configuration Register 2" },
-{ "ICONFA1_D", 0x0021C30C, 0, 0xffffffff, 'x', "Port D Input Configuration Register A1" },
-{ "ICONFA2_D", 0x0021C310, 0, 0xffffffff, 'x', "Port D Input Configuration Register A2" },
-{ "ICONFB1_D", 0x0021C314, 0, 0xffffffff, 'x', "Port D Input Configuration Register B1" },
-{ "ICONFB2_D", 0x0021C318, 0, 0xffffffff, 'x', "Port D Input Configuration Register B2" },
-{ "DR_D", 0x0021C31C, 0, 0xffffffff, 'x', "Port D Data Register" },
-{ "GIUS_D", 0x0021C320, 0, 0xffffffff, 'x', "Port D GPIO In Use Register" },
-{ "SSR_D", 0x0021C324, 0, 0xffffffff, 'x', "Port D Sample Status Register" },
-{ "ICR1_D", 0x0021C328, 0, 0xffffffff, 'x', "Port D Interrupt Configuration Register 1" },
-{ "ICR2_D", 0x0021C32C, 0, 0xffffffff, 'x', "Port D Interrupt Configuration Register 2" },
-{ "IMR_D", 0x0021C330, 0, 0xffffffff, 'x', "Port D Interrupt Mask Register" },
-{ "ISR_D", 0x0021C334, 0, 0xffffffff, 'x', "Port D Interrupt Status Register" },
-{ "GPR_D", 0x0021C338, 0, 0xffffffff, 'x', "Port D General Purpose Register" },
-{ "SWR_D", 0x0021C33C, 0, 0xffffffff, 'x', "Port D Software Reset Register" },
-{ "PUEN_D", 0x0021C340, 0, 0xffffffff, 'x', "Port D Pull_Up Enable Register" },
-{ "CS0U", 0x00220000, 0, 0xffffffff, 'x', "Chip Select 0 Upper Control Register" },
-{ "CS0L", 0x00220004, 0, 0xffffffff, 'x', "Chip Select 0 Lower Control Register" },
-{ "CS1U", 0x00220008, 0, 0xffffffff, 'x', "Chip Select 1 Upper Control Register" },
-{ "CS1L", 0x0022000C, 0, 0xffffffff, 'x', "Chip Select 1 Lower Control Register" },
-{ "CS2U", 0x00220010, 0, 0xffffffff, 'x', "Chip Select 2 Upper Control Register" },
-{ "CS2L", 0x00220014, 0, 0xffffffff, 'x', "Chip Select 2 Lower Control Register" },
-{ "CS3U", 0x00220018, 0, 0xffffffff, 'x', "Chip Select 3 Upper Control Register" },
-{ "CS3L", 0x0022001C, 0, 0xffffffff, 'x', "Chip Select 3 Lower Control Register" },
-{ "CS4U", 0x00220020, 0, 0xffffffff, 'x', "Chip Select 4 Upper Control Register" },
-{ "CS4L", 0x00220024, 0, 0xffffffff, 'x', "Chip Select 4 Lower Control Register" },
-{ "CS5U", 0x00220028, 0, 0xffffffff, 'x', "Chip Select 5 Upper Control Register" },
-{ "CS5L", 0x0022002C, 0, 0xffffffff, 'x', "Chip Select 5 Lower Control Register" },
-{ "EIM", 0x00220030, 0, 0xffffffff, 'x', "EIM Configuration Register" },
-{ "SDCTL0", 0x00221000, 0, 0xffffffff, 'x', "SDRAM 0 Control Register" },
-{ "SDCTL1", 0x00221004, 0, 0xffffffff, 'x', "SDRAM 1 Control Register" },
-{ "MISCELLANEOUS", 0x00221014, 0, 0xffffffff, 'x', "Miscellaneous Register" },
-{ "SDRST", 0x00221018, 0, 0xffffffff, 'x', "SDRAM Reset Register" },
-{ "MMA_MAC_MOD", 0x00222000, 0, 0xffffffff, 'x', "MMA MAC Module Register" },
-{ "MMA_MAC_CTRL", 0x00222004, 0, 0xffffffff, 'x', "MMA MAC Control Register" },
-{ "MMA_MAC_MULT", 0x00222008, 0, 0xffffffff, 'x', "MMA MAC Multiply Counter Register" },
-{ "MMA_MAC_ACCU", 0x0022200C, 0, 0xffffffff, 'x', "MMA MAC Accumulate Counter Register" },
-{ "MMA_MAC_INTR", 0x00222010, 0, 0xffffffff, 'x', "MMA MAC Interrupt Register" },
-{ "MMA_MAC_INTR_MASK", 0x00222014, 0, 0xffffffff, 'x', "MMA MAC Interrupt Mask Register" },
-{ "MMA_MAC_FIFO", 0x00222018, 0, 0xffffffff, 'x', "MMA MAC FIFO Register" },
-{ "MMA_MAC_FIFO_STAT", 0x0022201C, 0, 0xffffffff, 'x', "MMA MAC FIFO Status Register" },
-{ "MMA_MAC_BURST", 0x00222020, 0, 0xffffffff, 'x', "MMA MAC Burst Count Register" },
-{ "MMA_MAC_BITSEL", 0x00222024, 0, 0xffffffff, 'x', "MMA MAC Bit Select Register" },
-{ "MMA_MAC_XYACCU", 0x00222040, 0, 0xffffffff, 'x', "MMA MAC XY Count Accumulate Register" },
-{ "MMA_MAC_XBASE", 0x00222200, 0, 0xffffffff, 'x', "MMA MAC X Base Address Register" },
-{ "MMA_MAC_XINDEX", 0x00222204, 0, 0xffffffff, 'x', "MMA MAC X Index Register" },
-{ "MMA_MAC_XLENGTH", 0x00222208, 0, 0xffffffff, 'x', "MMA MAC X Length Register" },
-{ "MMA_MAC_XMODIFY", 0x0022220C, 0, 0xffffffff, 'x', "MMA MAC X Modify Register" },
-{ "MMA_MAC_XINCR", 0x00222210, 0, 0xffffffff, 'x', "MMA MAC X Increment Register" },
-{ "MMA_MAC_XCOUNT", 0x00222214, 0, 0xffffffff, 'x', "MMA MAC X Count Register" },
-{ "MMA_MAC_YBASE", 0x00222300, 0, 0xffffffff, 'x', "MMA MAC Y Base Address Register" },
-{ "MMA_MAC_YINDEX", 0x00222304, 0, 0xffffffff, 'x', "MMA MAC Y Index Register" },
-{ "MMA_MAC_YLENGTH", 0x00222308, 0, 0xffffffff, 'x', "MMA MAC Y Length Register" },
-{ "MMA_MAC_YMODIFY", 0x0022230C, 0, 0xffffffff, 'x', "MMA MAC Y Modify Register" },
-{ "MMA_MAC_YINCR", 0x00222310, 0, 0xffffffff, 'x', "MMA MAC Y Increment Register" },
-{ "MMA_MAC_YCOUNT", 0x00222314, 0, 0xffffffff, 'x', "MMA MAC Y Count Register" },
-{ "MMA_DCTCTRL", 0x00222400, 0, 0xffffffff, 'x', "DCT/iDCT Control Register" },
-{ "MMA_DCTVERSION", 0x00222404, 0, 0xffffffff, 'x', "DCT/iDCT Version Register" },
-{ "MMA_DCTIRQENA", 0x00222408, 0, 0xffffffff, 'x', "DCT/iDCT IRQ Enable Register" },
-{ "MMA_DCTIRQSTAT", 0x0022240C, 0, 0xffffffff, 'x', "DCT/iDCT IRQ Status Register" },
-{ "DSA_DCTSRCDATA", 0x00222410, 0, 0xffffffff, 'x', "DCT/iDCT Source Data Address" },
-{ "MMA_DCTDESDATA", 0x00222414, 0, 0xffffffff, 'x', "DCT/iDCT Destination Data Address" },
-{ "MMA_DCTXOFF", 0x00222418, 0, 0xffffffff, 'x', "DCT/iDCT X-Offset Address" },
-{ "MMA_DCTYOFF", 0x0022241C, 0, 0xffffffff, 'x', "DCT/iDCT Y-Offset Address" },
-{ "MMA_DCTXYCNT", 0x00222420, 0, 0xffffffff, 'x', "DCT/iDCT XY Count" },
-{ "MMA_DCTSKIP", 0x00222424, 0, 0xffffffff, 'x', "DCT/iDCT Skip Address" },
-{ "MMA_DCTFIFO", 0x00222500, 0, 0xffffffff, 'x', "DCT/iDCT Data FIFO" },
-{ "INTCNTL", 0x00223000, 0, 0xffffffff, 'x', "Interrupt Control Register" },
-{ "NIMASK", 0x00223004, 0, 0xffffffff, 'x', "Normal Interrupt Mask Register" },
-{ "INTENNUM", 0x00223008, 0, 0xffffffff, 'x', "Interrupt Enable Number Register" },
-{ "INTDISNUM", 0x0022300C, 0, 0xffffffff, 'x', "Interrupt Disable Number Register" },
-{ "INTENABLEH", 0x00223010, 0, 0xffffffff, 'x', "Interrupt Enable Register High" },
-{ "INTENABLEL", 0x00223014, 0, 0xffffffff, 'x', "Interrupt Enable Register Low" },
-{ "INTTYPEH", 0x00223018, 0, 0xffffffff, 'x', "Interrupt Type Register High" },
-{ "INTTYPEL", 0x0022301C, 0, 0xffffffff, 'x', "Interrupt Type Register Low" },
-{ "NIPRIORITY7", 0x00223020, 0, 0xffffffff, 'x', "Normal Interrupt Priority Level Register 7" },
-{ "NIPRIORITY6", 0x00223024, 0, 0xffffffff, 'x', "Normal Interrupt Priority Level Register 6" },
-{ "NIPRIORITY5", 0x00223028, 0, 0xffffffff, 'x', "Normal Interrupt Priority Level Register 5" },
-{ "NIPRIORITY4", 0x0022302C, 0, 0xffffffff, 'x', "Normal Interrupt Priority Level Register 4" },
-{ "NIPRIORITY3", 0x00223030, 0, 0xffffffff, 'x', "Normal Interrupt Priority Level Register 3" },
-{ "NIPRIORITY2", 0x00223034, 0, 0xffffffff, 'x', "Normal Interrupt Priority Level Register 2" },
-{ "NIPRIORITY1", 0x00223038, 0, 0xffffffff, 'x', "Normal Interrupt Priority Level Register 1" },
-{ "NIPRIORITY0", 0x0022303C, 0, 0xffffffff, 'x', "Normal Interrupt Priority Level Register 0" },
-{ "NIVECSR", 0x00223040, 0, 0xffffffff, 'x', "Normal Interrupt Vector and Status Register" },
-{ "FIVECSR", 0x00223044, 0, 0xffffffff, 'x', "Fast Interrupt Vector and Status Register" },
-{ "INTSRCH", 0x00223048, 0, 0xffffffff, 'x', "Interrupt Source Register High" },
-{ "INTSRCL", 0x0022304C, 0, 0xffffffff, 'x', "Interrupt Source Register Low" },
-{ "INTFRCH", 0x00223050, 0, 0xffffffff, 'x', "Interrupt Force Register High" },
-{ "INTFRCL", 0x00223054, 0, 0xffffffff, 'x', "Interrupt Force Register Low" },
-{ "NIPNDH", 0x00223058, 0, 0xffffffff, 'x', "Normal Interrupt Pending Register High" },
-{ "NIPNDL", 0x0022305C, 0, 0xffffffff, 'x', "Normal Interrupt Pending Register Low" },
-{ "FIPNDH", 0x00223060, 0, 0xffffffff, 'x', "Fast Interrupt Pending Register High" },
-{ "FIPNDL", 0x00223064, 0, 0xffffffff, 'x', "Fast Interrupt Pending Register Low" },
-{ "CSICR1", 0x00224000, 0, 0xffffffff, 'x', "CSI Control Register 1" },
-{ "CSICR2", 0x00224004, 0, 0xffffffff, 'x', "CSI Control Register 2" },
-{ "CSISR", 0x00224008, 0, 0xffffffff, 'x', "CSI Status Register 1" },
-{ "CSISTATR", 0x0022400C, 0, 0xffffffff, 'x', "CSI Statistic FIFO Register 1" },
-{ "CSIRXR", 0x00224010, 0, 0xffffffff, 'x', "CSI RxFIFO Register 1" },
-};
-
-// Size of mmapping:
-#define MAP_SIZE 4096
-#define MAP_MASK ( MAP_SIZE - 1 )
Modified: trunk/target/linux/debug/imxssi/imxssi.c
===================================================================
--- trunk/target/linux/debug/imxssi/imxssi.c 2008-12-15 15:19:39 UTC (rev 959)
+++ trunk/target/linux/debug/imxssi/imxssi.c 2008-12-15 16:37:15 UTC (rev 960)
@@ -35,7 +35,7 @@
/*#include <linux/i2c.h>
#include <linux/i2c-dev.h>*/
-#include "imxregs.h"
+#include "../imxregs/imxregs.h"
#define DEBUG TRUE
@@ -138,10 +138,10 @@
switch (regs[i].type)
{
// Hexa printing
- case 'x':
+ case 'x':
printf("%8x", shiftdata);
break;
- case '<':
+ case '<':
printf("%8u", 1 << shiftdata);
break;
// Decimal printing
@@ -317,34 +317,6 @@
char *p;
u32 val;
- // No arguments -> dump all known registers
- if (argc == 1) {
- dumpall();
- return 0;
- }
-
- // Uppercase first argument (register name)
- if (argc >= 2) {
- p = argv[1];
- while (*p) {
- *p = toupper(*p);
- p++;
- }
- }
-
- // Dump the content of the provided register
- if (argc == 2) {
- dumpmatching(argv[1]);
- return 0;
- }
-
- // Put value to given register
- if (argc == 3) {
- sscanf(argv[2],"%i",&val);
- setreg(argv[1], val);
- return 0;
- }
-
if (argc == 4) {
u32 type;
float level;
@@ -362,16 +334,12 @@
return 0;
}
// In all other cases, print Usage
- printf("Usage: %s - to dump all known registers\n"
- " %s <name> - to dump named register\n"
- " %s <name> <value> - to set named register\n",
- " %s <signal_type> <samples> <scale> - to audio signal:\n",
- " <signal_type> 0:triangular 1:sinusoid",
- " <samples> nb sample per period",
- " <scale> 0.0 .. 1.0 signal amplitude\n",
- " tsc2102 has to be configured in master mode",
+ printf("Usage: %s <signal_type> <samples> <scale> - to audio signal:\n"
+ " <signal_type> 0:triangular 1:sinusoid\n"
+ " <samples> nb sample per period\n"
+ " <scale> 0.0 .. 1.0 signal amplitude\n"
+ " !! tsc210x has to be configured in master mode !!\n",
argv[0], argv[0], argv[0], argv[0]);
return 1;
}
-
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