[Armadeus-commitlog] SF.net SVN: armadeus:[916] trunk/target/linux/modules/fpga/dev_tools/ fpga_dev
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[Armadeus-commitlog] SF.net SVN: armadeus:[916] trunk/target/linux/modules/fpga/dev_tools/ fpga_devtools
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From: <ar...@us...> - 2008-12-04 09:40:48
|
Revision: 916
http://armadeus.svn.sourceforge.net/armadeus/?rev=916&view=rev
Author: artemys
Date: 2008-12-04 09:40:44 +0000 (Thu, 04 Dec 2008)
Log Message:
-----------
[MERGE] Correct wrong file format of fpgaloader files
Modified Paths:
--------------
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.c
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/target-fpga-loader.c
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/target-fpga-loader.h
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.c
trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.h
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.c
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.c 2008-12-04 07:26:29 UTC (rev 915)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/fpga-loader.c 2008-12-04 09:40:44 UTC (rev 916)
@@ -1,284 +1,284 @@
-/*
- ***********************************************************************
- *
- * (c) Copyright 2006 Armadeus project
- * Julien Boibessot <jul...@ar...>
- * Nicolas Colombain <nic...@ar...>
- * Generic Xilinx FPGA loader
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- **********************************************************************
- */
-#include <linux/version.h>
-#include "fpga-loader.h"
-#include "xilinx-fpga-loader.h"
-#include <asm/arch/imx-regs.h>
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
-#include <linux/config.h>
-#endif
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/fs.h>
-#include <linux/errno.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/fcntl.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
-
-//static unsigned long init_map;
-struct semaphore fpga_sema;
-
-/* global variables */
-static int fpga_major = FPGA_MAJOR;
-Xilinx_desc* g_current_desc = NULL;
-
-static unsigned char fpga_descriptor = 0; // use default target_fpga_desc
-module_param( fpga_descriptor, byte, 0 );
-
-#define FPGA_BUFFER_SIZE 4096
-static unsigned char g_buffer[FPGA_BUFFER_SIZE];
-static unsigned char g_nb_users = 0;
-
-
-void __exit armadeus_fpga_cleanup(void);
-
-
-//------------------------------------------------
-//
-// Handles write() done on /dev/fpgaxx
-//
-static ssize_t armadeus_fpga_write(struct file *file, const char* pData, size_t count, loff_t *f_pos)
-{
- ssize_t ret = 0;
-
- // Get exclusive access
- if (down_interruptible(&fpga_sema))
- return -ERESTARTSYS;
-
- if( count > FPGA_BUFFER_SIZE ) {
- count = FPGA_BUFFER_SIZE;
- }
-
- // Get value to write from user space
- ret = __copy_from_user( g_buffer, pData, count);
- if (ret != 0) {
- ret = -EFAULT;
- goto out;
- }
-
- ret = xilinx_load( g_current_desc, g_buffer, count );
-
-out:
- // Release exclusive access
- up(&fpga_sema);
-
- return( ret );
-}
-
-static int armadeus_fpga_open(struct inode *inode, struct file *file)
-{
- int ret;
-
- // Only one access at a time is permitted
- if( g_nb_users > 0 )
- return( -EBUSY );
-
- g_nb_users++;
- ret = xilinx_init_load( g_current_desc );
-
- PRINTF("Opening /dev/fpga/loader%d file, %d %d\n", MINOR(inode->i_rdev), fpga_descriptor, ret);
- return ret;
-}
-
-static int armadeus_fpga_release(struct inode *inode, struct file *file)
-{
- if( g_nb_users > 0 )
- g_nb_users--;
-
- PRINTF("Closing access to /dev/fpga/loader%d\n", MINOR(inode->i_rdev));
- return 0;
-}
-
-//------------------------------------------------
-// PROC file
-//
-static int procfile_fpga_read( char *buffer, __attribute__ ((unused)) char **start, off_t offset, int buffer_length, int *eof, __attribute__ ((unused)) void* data)
-{
- int ret;
-
- // We give all of our information in one go, so if the user asks us if we have more information the answer should always be no.
- // This is important because the standard read function from the library would continue to issue the read system call until
- // the kernel replies that it has no more information, or until its buffer is filled.
- if( offset > 0 ) {
- /* we have finished to read, return 0 */
- ret = 0;
- } else {
- if ( data == NULL ){
- ret = xilinx_get_descriptor_info( -1, buffer );
- }
- else {
- ret = xilinx_get_descriptor_info( *((unsigned char*)data), buffer );
- }
- }
-
- return ret;
-}
-
-
-static int procfile_fpga_write( __attribute__ ((unused)) struct file *file, const char *buf, unsigned long count, void *data)
-{
- return count;
-}
-
-//------------------------------------------------
-// Handling of IOCTL calls
-//
-int armadeus_fpga_ioctl( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg )
-{
- int err = 0; int ret = 0;
- unsigned int minor;
-
- PRINTF( DRIVER_NAME " ## IOCTL received: (0x%x) ##\n", cmd );
-
- // Extract the type and number bitfields, and don't decode wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok()
- if (_IOC_TYPE(cmd) != FPGA_IOCTL) return -ENOTTY;
-
- // The direction is a bitmask, and VERIFY_WRITE catches R/W transfers. `Type' is user-oriented, while access_ok is kernel-oriented,
- // so the concept of "read" and "write" is reversed
- if (_IOC_DIR(cmd) & _IOC_READ)
- err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
- else if (_IOC_DIR(cmd) & _IOC_WRITE)
- err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
-
- if (err) return -EFAULT;
-
- // Obtain exclusive access
- if (down_interruptible(&fpga_sema))
- return -ERESTARTSYS;
- // Extract and test minor
- minor = MINOR(inode->i_rdev);
- if( minor > FPGA_MAX_MINOR ) {
- printk("Minor outside range: %d !\n", minor);
- return -EFAULT;
- }
-
- switch(cmd)
- {
- default:
- return -ENOTTY;
- break;
- }
- // Release exclusive access
- up(&fpga_sema);
-
- return ret;
-}
-
-//
-// Create /proc entries for direct access (with echo/cat) to GPIOs config
-//
-static int createProcEntries( void )
-{
- static struct proc_dir_entry *fpga_Proc_File;
-
- // Create main directory
- proc_mkdir(FPGA_PROC_DIRNAME, NULL);
- // Create proc file to handle GPIO values
- fpga_Proc_File = create_proc_entry( FPGA_PROC_FILENAME, S_IWUSR |S_IRUSR | S_IRGRP | S_IROTH, NULL );
-
- if( fpga_Proc_File == NULL )
- {
- printk(FPGA_DRIVER_NAME ": Could not register a" FPGA_PROC_FILENAME ". Terminating\n");
- armadeus_fpga_cleanup();
- return -ENOMEM;
- }
- else
- {
- fpga_Proc_File->read_proc = procfile_fpga_read;
- fpga_Proc_File->write_proc = procfile_fpga_write;
- }
-
- return(0);
-}
-
-static struct file_operations fpga_fops = {
- .owner = THIS_MODULE,
- .write = armadeus_fpga_write,
-// .read = armadeus_fpga_read,
- .open = armadeus_fpga_open,
- .release = armadeus_fpga_release,
- .ioctl = armadeus_fpga_ioctl,
-};
-
-//
-// Module's initialization function
-//
-int __init armadeus_fpga_init(void)
-{
- static int result;
-
- // Register the driver by getting a major number
- result = register_chrdev(fpga_major, FPGA_DRIVER_NAME, &fpga_fops);
- if (result < 0)
- {
- printk(KERN_WARNING FPGA_DRIVER_NAME ": can't get major %d\n", fpga_major);
- return result;
- }
- if( fpga_major == 0 ) fpga_major = result; // dynamic Major allocation
-
- // Creating /proc entries
- result = createProcEntries();
- if( result < 0 ) return( result );
-
- // Initialise FPGA semaphore
- sema_init(&fpga_sema, 1);
-
- // initialize the current fpga descriptor with the one by default
- g_current_desc = xilinx_get_descriptor(fpga_descriptor);
- if( g_current_desc == NULL ){
- return -EINVAL;
- }
-
- printk(FPGA_DRIVER_NAME " module " FPGA_DRIVER_VERSION " successfully loaded !\n");
- return(0);
-}
-
-//
-// Module's cleanup function
-//
-void __exit armadeus_fpga_cleanup(void)
-{
- PRINTF("Removing " FPGA_DRIVER_NAME " module: ");
-
- // Remove /proc entries
- remove_proc_entry(FPGA_PROC_FILENAME, NULL);
- // De-register /dev interface
- unregister_chrdev(fpga_major, FPGA_DRIVER_NAME);
-
- PRINTF("Ok !\n ");
-}
-
-//------------------------------------------------
-
-module_init(armadeus_fpga_init);
-module_exit(armadeus_fpga_cleanup);
-
-MODULE_AUTHOR("JB / NC");
-MODULE_DESCRIPTION("Armadeus fpga's loading driver");
-MODULE_LICENSE("GPL");
+/*
+ ***********************************************************************
+ *
+ * (c) Copyright 2006 Armadeus project
+ * Julien Boibessot <jul...@ar...>
+ * Nicolas Colombain <nic...@ar...>
+ * Generic Xilinx FPGA loader
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
+ */
+#include <linux/version.h>
+#include "fpga-loader.h"
+#include "xilinx-fpga-loader.h"
+#include <asm/arch/imx-regs.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
+#include <linux/config.h>
+#endif
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/fcntl.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+//static unsigned long init_map;
+struct semaphore fpga_sema;
+
+/* global variables */
+static int fpga_major = FPGA_MAJOR;
+Xilinx_desc* g_current_desc = NULL;
+
+static unsigned char fpga_descriptor = 0; // use default target_fpga_desc
+module_param( fpga_descriptor, byte, 0 );
+
+#define FPGA_BUFFER_SIZE 4096
+static unsigned char g_buffer[FPGA_BUFFER_SIZE];
+static unsigned char g_nb_users = 0;
+
+
+void __exit armadeus_fpga_cleanup(void);
+
+
+//------------------------------------------------
+//
+// Handles write() done on /dev/fpgaxx
+//
+static ssize_t armadeus_fpga_write(struct file *file, const char* pData, size_t count, loff_t *f_pos)
+{
+ ssize_t ret = 0;
+
+ // Get exclusive access
+ if (down_interruptible(&fpga_sema))
+ return -ERESTARTSYS;
+
+ if( count > FPGA_BUFFER_SIZE ) {
+ count = FPGA_BUFFER_SIZE;
+ }
+
+ // Get value to write from user space
+ ret = __copy_from_user( g_buffer, pData, count);
+ if (ret != 0) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ ret = xilinx_load( g_current_desc, g_buffer, count );
+
+out:
+ // Release exclusive access
+ up(&fpga_sema);
+
+ return( ret );
+}
+
+static int armadeus_fpga_open(struct inode *inode, struct file *file)
+{
+ int ret;
+
+ // Only one access at a time is permitted
+ if( g_nb_users > 0 )
+ return( -EBUSY );
+
+ g_nb_users++;
+ ret = xilinx_init_load( g_current_desc );
+
+ PRINTF("Opening /dev/fpga/loader%d file, %d %d\n", MINOR(inode->i_rdev), fpga_descriptor, ret);
+ return ret;
+}
+
+static int armadeus_fpga_release(struct inode *inode, struct file *file)
+{
+ if( g_nb_users > 0 )
+ g_nb_users--;
+
+ PRINTF("Closing access to /dev/fpga/loader%d\n", MINOR(inode->i_rdev));
+ return 0;
+}
+
+//------------------------------------------------
+// PROC file
+//
+static int procfile_fpga_read( char *buffer, __attribute__ ((unused)) char **start, off_t offset, int buffer_length, int *eof, __attribute__ ((unused)) void* data)
+{
+ int ret;
+
+ // We give all of our information in one go, so if the user asks us if we have more information the answer should always be no.
+ // This is important because the standard read function from the library would continue to issue the read system call until
+ // the kernel replies that it has no more information, or until its buffer is filled.
+ if( offset > 0 ) {
+ /* we have finished to read, return 0 */
+ ret = 0;
+ } else {
+ if ( data == NULL ){
+ ret = xilinx_get_descriptor_info( -1, buffer );
+ }
+ else {
+ ret = xilinx_get_descriptor_info( *((unsigned char*)data), buffer );
+ }
+ }
+
+ return ret;
+}
+
+
+static int procfile_fpga_write( __attribute__ ((unused)) struct file *file, const char *buf, unsigned long count, void *data)
+{
+ return count;
+}
+
+//------------------------------------------------
+// Handling of IOCTL calls
+//
+int armadeus_fpga_ioctl( struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg )
+{
+ int err = 0; int ret = 0;
+ unsigned int minor;
+
+ PRINTF( DRIVER_NAME " ## IOCTL received: (0x%x) ##\n", cmd );
+
+ // Extract the type and number bitfields, and don't decode wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok()
+ if (_IOC_TYPE(cmd) != FPGA_IOCTL) return -ENOTTY;
+
+ // The direction is a bitmask, and VERIFY_WRITE catches R/W transfers. `Type' is user-oriented, while access_ok is kernel-oriented,
+ // so the concept of "read" and "write" is reversed
+ if (_IOC_DIR(cmd) & _IOC_READ)
+ err = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd));
+ else if (_IOC_DIR(cmd) & _IOC_WRITE)
+ err = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd));
+
+ if (err) return -EFAULT;
+
+ // Obtain exclusive access
+ if (down_interruptible(&fpga_sema))
+ return -ERESTARTSYS;
+ // Extract and test minor
+ minor = MINOR(inode->i_rdev);
+ if( minor > FPGA_MAX_MINOR ) {
+ printk("Minor outside range: %d !\n", minor);
+ return -EFAULT;
+ }
+
+ switch(cmd)
+ {
+ default:
+ return -ENOTTY;
+ break;
+ }
+ // Release exclusive access
+ up(&fpga_sema);
+
+ return ret;
+}
+
+//
+// Create /proc entries for direct access (with echo/cat) to GPIOs config
+//
+static int createProcEntries( void )
+{
+ static struct proc_dir_entry *fpga_Proc_File;
+
+ // Create main directory
+ proc_mkdir(FPGA_PROC_DIRNAME, NULL);
+ // Create proc file to handle GPIO values
+ fpga_Proc_File = create_proc_entry( FPGA_PROC_FILENAME, S_IWUSR |S_IRUSR | S_IRGRP | S_IROTH, NULL );
+
+ if( fpga_Proc_File == NULL )
+ {
+ printk(FPGA_DRIVER_NAME ": Could not register a" FPGA_PROC_FILENAME ". Terminating\n");
+ armadeus_fpga_cleanup();
+ return -ENOMEM;
+ }
+ else
+ {
+ fpga_Proc_File->read_proc = procfile_fpga_read;
+ fpga_Proc_File->write_proc = procfile_fpga_write;
+ }
+
+ return(0);
+}
+
+static struct file_operations fpga_fops = {
+ .owner = THIS_MODULE,
+ .write = armadeus_fpga_write,
+// .read = armadeus_fpga_read,
+ .open = armadeus_fpga_open,
+ .release = armadeus_fpga_release,
+ .ioctl = armadeus_fpga_ioctl,
+};
+
+//
+// Module's initialization function
+//
+int __init armadeus_fpga_init(void)
+{
+ static int result;
+
+ // Register the driver by getting a major number
+ result = register_chrdev(fpga_major, FPGA_DRIVER_NAME, &fpga_fops);
+ if (result < 0)
+ {
+ printk(KERN_WARNING FPGA_DRIVER_NAME ": can't get major %d\n", fpga_major);
+ return result;
+ }
+ if( fpga_major == 0 ) fpga_major = result; // dynamic Major allocation
+
+ // Creating /proc entries
+ result = createProcEntries();
+ if( result < 0 ) return( result );
+
+ // Initialise FPGA semaphore
+ sema_init(&fpga_sema, 1);
+
+ // initialize the current fpga descriptor with the one by default
+ g_current_desc = xilinx_get_descriptor(fpga_descriptor);
+ if( g_current_desc == NULL ){
+ return -EINVAL;
+ }
+
+ printk(FPGA_DRIVER_NAME " module " FPGA_DRIVER_VERSION " successfully loaded !\n");
+ return(0);
+}
+
+//
+// Module's cleanup function
+//
+void __exit armadeus_fpga_cleanup(void)
+{
+ PRINTF("Removing " FPGA_DRIVER_NAME " module: ");
+
+ // Remove /proc entries
+ remove_proc_entry(FPGA_PROC_FILENAME, NULL);
+ // De-register /dev interface
+ unregister_chrdev(fpga_major, FPGA_DRIVER_NAME);
+
+ PRINTF("Ok !\n ");
+}
+
+//------------------------------------------------
+
+module_init(armadeus_fpga_init);
+module_exit(armadeus_fpga_cleanup);
+
+MODULE_AUTHOR("JB / NC");
+MODULE_DESCRIPTION("Armadeus fpga's loading driver");
+MODULE_LICENSE("GPL");
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/target-fpga-loader.c
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/target-fpga-loader.c 2008-12-04 07:26:29 UTC (rev 915)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/target-fpga-loader.c 2008-12-04 09:40:44 UTC (rev 916)
@@ -15,102 +15,102 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
**********************************************************************
- (c) Copyright 2006 Armadeus project
- Eric Jarrige <eri...@ar...>
- Nicolas Colombain <nic...@ar...>
- Target Xilinx FPGA support
+ (c) Copyright 2006 Armadeus project
+ Eric Jarrige <eri...@ar...>
+ Nicolas Colombain <nic...@ar...>
+ Target Xilinx FPGA support
*/
-
-#include "target-fpga-loader.h"
-#include "xilinx-fpga-loader.h"
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#define GPIO_PORT(x) ((x >> 5) & 3)
-#define GPIO_SET(x) (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
-#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
-#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
-#define GPIO_READ(x) ((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
-
-/*
- * Set the FPGA's active-low program line to the specified level
- */
-int fpga_pgm_fn( int assert )
-{
- GPIO_WRITE( FPGA_PROGRAM, !assert);
- return assert;
-}
-
-/*
- * Set the FPGA's active-high clock line to the specified level
- */
-int fpga_clk_fn( int assert_clk )
-{
- GPIO_WRITE( FPGA_CLOCK, assert_clk);
- return assert_clk;
-}
-
-/*
- * Test the state of the active-low FPGA INIT line. Return 1 on INIT
- * asserted (low).
- */
-int fpga_init_fn( void )
-{
- return(!GPIO_READ(FPGA_INIT));
-}
-
-/*
- * Test the state of the active-high FPGA DONE pin
- */
-int fpga_done_fn( void )
-{
- return(GPIO_READ(FPGA_DONE));
-}
-
-/*
- * Set the FPGA's data line to the specified level
- */
-int fpga_wr_fn( int assert_write )
-{
- GPIO_WRITE( FPGA_DIN, assert_write);
- return assert_write;
-}
-
-int fpga_pre_fn( void )
-{
- // Initialize GPIO pins
- imx_gpio_mode (FPGA_INIT | GPIO_GIUS | GPIO_DR | GPIO_IN );
- imx_gpio_mode (FPGA_DONE | GPIO_GIUS | GPIO_DR | GPIO_IN );
- imx_gpio_mode (FPGA_DIN | GPIO_GIUS | GPIO_DR | GPIO_OUT );
- imx_gpio_mode (FPGA_PROGRAM | GPIO_GIUS | GPIO_DR | GPIO_OUT );
- imx_gpio_mode (FPGA_CLOCK | GPIO_GIUS | GPIO_DR | GPIO_OUT );
- return 1;
-}
-
-
-Xilinx_Spartan_Slave_Serial_fns fpga_fns = {
- fpga_pre_fn,
- fpga_pgm_fn,
- fpga_clk_fn,
- fpga_init_fn,
- fpga_done_fn,
- fpga_wr_fn,
-};
-
-Xilinx_desc target_fpga_desc[NB_TARGET_DESC] = {
-
- { // first supported configuration (default)
- Xilinx_Spartan,
- slave_serial,
- XILINX_XC3S200_SIZE,
- (void *) &fpga_fns
- },
-
- { // second one
- Xilinx_Spartan,
- slave_serial,
- XILINX_XC3S400_SIZE,
- (void *) &fpga_fns
- }
-};
+#include "target-fpga-loader.h"
+#include "xilinx-fpga-loader.h"
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define GPIO_PORT(x) ((x >> 5) & 3)
+#define GPIO_SET(x) (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
+#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
+#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
+#define GPIO_READ(x) ((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
+
+/*
+ * Set the FPGA's active-low program line to the specified level
+ */
+int fpga_pgm_fn( int assert )
+{
+ GPIO_WRITE( FPGA_PROGRAM, !assert);
+ return assert;
+}
+
+/*
+ * Set the FPGA's active-high clock line to the specified level
+ */
+int fpga_clk_fn( int assert_clk )
+{
+ GPIO_WRITE( FPGA_CLOCK, assert_clk);
+ return assert_clk;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn( void )
+{
+ return(!GPIO_READ(FPGA_INIT));
+}
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn( void )
+{
+ return(GPIO_READ(FPGA_DONE));
+}
+
+/*
+ * Set the FPGA's data line to the specified level
+ */
+int fpga_wr_fn( int assert_write )
+{
+ GPIO_WRITE( FPGA_DIN, assert_write);
+ return assert_write;
+}
+
+int fpga_pre_fn( void )
+{
+ // Initialize GPIO pins
+ imx_gpio_mode (FPGA_INIT | GPIO_GIUS | GPIO_DR | GPIO_IN );
+ imx_gpio_mode (FPGA_DONE | GPIO_GIUS | GPIO_DR | GPIO_IN );
+ imx_gpio_mode (FPGA_DIN | GPIO_GIUS | GPIO_DR | GPIO_OUT );
+ imx_gpio_mode (FPGA_PROGRAM | GPIO_GIUS | GPIO_DR | GPIO_OUT );
+ imx_gpio_mode (FPGA_CLOCK | GPIO_GIUS | GPIO_DR | GPIO_OUT );
+ return 1;
+}
+
+
+Xilinx_Spartan_Slave_Serial_fns fpga_fns = {
+ fpga_pre_fn,
+ fpga_pgm_fn,
+ fpga_clk_fn,
+ fpga_init_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+};
+
+Xilinx_desc target_fpga_desc[NB_TARGET_DESC] = {
+
+ { // first supported configuration (default)
+ Xilinx_Spartan,
+ slave_serial,
+ XILINX_XC3S200_SIZE,
+ (void *) &fpga_fns
+ },
+
+ { // second one
+ Xilinx_Spartan,
+ slave_serial,
+ XILINX_XC3S400_SIZE,
+ (void *) &fpga_fns
+ }
+};
+
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/target-fpga-loader.h
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/target-fpga-loader.h 2008-12-04 07:26:29 UTC (rev 915)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/target-fpga-loader.h 2008-12-04 09:40:44 UTC (rev 916)
@@ -15,26 +15,26 @@
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
**********************************************************************
- (c) Copyright 2006 Armadeus project
- Eric Jarrige <eri...@ar...>
- Nicolas Colombain <nic...@ar...>
- Target Xilinx FPGA support
+ (c) Copyright 2006 Armadeus project
+ Eric Jarrige <eri...@ar...>
+ Nicolas Colombain <nic...@ar...>
+ Target Xilinx FPGA support
*/
-#ifndef __TARGET_FPGA_LOADER_H__
-#define __TARGET_FPGA_LOADER_H__
-
-
-#include "xilinx-fpga-loader.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/io.h>
-
-#define FPGA_INIT (GPIO_PORTB | 15) /* FPGA init pin (SSI input) */
-#define FPGA_DONE (GPIO_PORTB | 16) /* FPGA done pin (SSI input) */
-#define FPGA_DIN (GPIO_PORTB | 17) /* FPGA data pin (SSI output) */
-#define FPGA_PROGRAM (GPIO_PORTB | 18) /* FPGA prog pin (SSI output) */
-#define FPGA_CLOCK (GPIO_PORTB | 19) /* FPGA clk pin (SSI output) */
-
-#define NB_TARGET_DESC 2
-
-#endif // __TARGET_FPGA_LOADER_H__
+#ifndef __TARGET_FPGA_LOADER_H__
+#define __TARGET_FPGA_LOADER_H__
+
+
+#include "xilinx-fpga-loader.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+
+#define FPGA_INIT (GPIO_PORTB | 15) /* FPGA init pin (SSI input) */
+#define FPGA_DONE (GPIO_PORTB | 16) /* FPGA done pin (SSI input) */
+#define FPGA_DIN (GPIO_PORTB | 17) /* FPGA data pin (SSI output) */
+#define FPGA_PROGRAM (GPIO_PORTB | 18) /* FPGA prog pin (SSI output) */
+#define FPGA_CLOCK (GPIO_PORTB | 19) /* FPGA clk pin (SSI output) */
+
+#define NB_TARGET_DESC 2
+
+#endif // __TARGET_FPGA_LOADER_H__
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.c
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.c 2008-12-04 07:26:29 UTC (rev 915)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.c 2008-12-04 09:40:44 UTC (rev 916)
@@ -1,277 +1,277 @@
-/*
- * (c) Copyright 2006 Armadeus project
- * Nicolas Colombain <nic...@ar...>
- * Xilinx FPGA support
- *
- * Based on the implementation(uBoot) of:
- * Rich Ireland, Enterasys Networks, rir...@en....
- * Keith Outwater, kei...@mv...
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include "xilinx-fpga-loader.h"
-#include "target-fpga-loader.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/io.h>
-#include <linux/time.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-
-#define CONFIG_FPGA_DELAY()
-#define CFG_FPGA_WAIT 4000 // uS
-
-size_t bytecount = 0; // total bytes received
-extern Xilinx_desc target_fpga_desc[]; // target descriptor table
-
-/*
- * Timeout function
- */
-static unsigned long get_timer(unsigned long initTime)
-{
- struct timeval tv;
- do_gettimeofday(&tv);
- if( tv.tv_usec > initTime ) // avoid overflow pb
- return tv.tv_usec - initTime;
- else
- return initTime - tv.tv_usec;
-}
-
-/*
- * dump the given descriptor infos
- */
-static int xilinx_dump_descriptor_info( Xilinx_desc *desc, char* buffer )
-{
- int len;
- len = sprintf( buffer, "%s %s %u\n",
- (desc->family == Xilinx_Spartan) ? "spartan":"unknown",
- (desc->iface == slave_serial) ? "slave serial":"unknown",
- desc->size );
- return len;
-}
-
-/**
- * program the FPGA.
- * return 0 if success, >0 while programming, <0 if error detected
- */
-static size_t spartan_serial_load (Xilinx_desc *desc, const char* buf, size_t bsize)
-{
- Xilinx_Spartan_Slave_Serial_fns *fn = desc->iface_fns;
- if (fn) {
- unsigned long ts; /* timestamp */
-
- /* Load the data */
- if( bytecount<=desc->size ) {
- int i;
- unsigned char val;
- size_t nbbyte = 0; // init local counter
-
- while (nbbyte < bsize) {
-
- /* Xilinx detects an error if INIT goes low (active)
- while DONE is low (inactive) */
- if ((*fn->done)() == 0 && (*fn->init)()) {
- PRINTF ("** CRC error during FPGA load.\n");
- return -ETIMEDOUT;
- }
- val = buf[nbbyte ++];
- bytecount++;
- i = 8;
- do {
- /* Deassert the clock */
- (*fn->clk)(0);
- CONFIG_FPGA_DELAY ();
- /* Write data */
- (*fn->wr)(val & 0x80);
- CONFIG_FPGA_DELAY ();
- /* Assert the clock */
- (*fn->clk)(1);
- CONFIG_FPGA_DELAY ();
- val <<= 1;
- i --;
- } while (i > 0);
- }
- }
- if( bytecount>=desc->size )
- {
- CONFIG_FPGA_DELAY ();
-
- /* now check for done signal */
- ts = get_timer(0); /* get current time */
- (*fn->wr)(1);
-
- while (! (*fn->done)()) {
- CONFIG_FPGA_DELAY ();
- (*fn->clk)(0); /* Deassert the clock pin */
- CONFIG_FPGA_DELAY ();
- (*fn->clk)(1); /* Assert the clock pin */
-
- if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
- PRINTF ("** Timeout waiting for DONE.\n");
- return -ETIMEDOUT;
- }
- }
- }
- return bsize;
- }
- return -EINVAL;
-}
-
-/**
- * initialize the FPGA programming interface.
- * return 0 if success, <0 if error detected
- */
-static int spartan_serial_init (Xilinx_desc *desc)
-{
- Xilinx_Spartan_Slave_Serial_fns *fn = desc->iface_fns;
- if (fn) {
- unsigned long ts; /* timestamp */
-
- if(*fn->pre){
- (*fn->pre)(); //Run the pre configuration function if there is one.
- }
-
- /* Establish the initial state */
- (*fn->pgm)(1); /* Assert the program, commit */
-
- /* Wait for INIT state (init low) */
- ts = get_timer(0); /* get current time */
- do {
- CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
- PRINTF ("** Timeout waiting for INIT to start.\n");
- return -ETIMEDOUT;
- }
- } while (!(*fn->init)());
-
- /* Get ready for the burn */
- CONFIG_FPGA_DELAY ();
- (*fn->pgm)(0); /* Deassert the program, commit */
-
- ts = get_timer(0); /* get current time */
- /* Now wait for INIT to go high */
- do {
- CONFIG_FPGA_DELAY ();
- if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
- PRINTF ("** Timeout waiting for INIT to clear.\n");
- return -ETIMEDOUT;
- }
- } while ((*fn->init)());
-
- bytecount = 0; // reset byte count
- return 0; // success
- }
- return -EINVAL;
-}
-
-/**
- * program the FPGA.
- * return 0 if success, >0 while programming, <0 if error detected
- */
-size_t xilinx_load( Xilinx_desc *desc, const char *buf, size_t bsize )
-{
- int ret = 0;
-
- if( desc ) {
- switch( desc->family ) // check family
- {
- case Xilinx_Spartan:
- {
- switch( desc->iface ) // check donwload hardware interface
- {
- case slave_serial: ret = spartan_serial_load( desc, buf, bsize ); break;
- default: PRINTF("interface not supported!\n"); ret = -ENOSYS; break;
- }
- }
- break;
- default: PRINTF("family not supported!\n"); ret = -ENOSYS; break;
- }
- }
- else {
- PRINTF("invalid FPGA descriptor!\n");
- ret = -EINVAL;
- }
- return ret;
-}
-
-/**
- * initialize the FPGA programming interface.
- * return 0 if success, <0 if error detected
- */
-int xilinx_init_load( Xilinx_desc *desc )
-{
- int ret = 0;
-
- if( desc ) {
- switch( desc->family ) // check family
- {
- case Xilinx_Spartan:
- {
- switch( desc->iface ) // check donwload hardware interface
- {
- case slave_serial: ret = spartan_serial_init( desc ); break;
- default: PRINTF("interface not supported!\n"); ret = -ENOSYS; break;
- }
- }
- break;
- default: PRINTF("family not supported!\n"); ret = -ENOSYS; break;
- }
- }
- else {
- PRINTF("invalid FPGA descriptor!\n");
- ret = -EINVAL;
- }
- return ret;
-}
-
-/**
- * get the descriptor corresponding to desc_id
- * return NULL if error
- */
-Xilinx_desc * xilinx_get_descriptor( unsigned char desc_id )
-{
- if( desc_id < NB_TARGET_DESC ){
- return &(target_fpga_desc[desc_id]);
- }
- return NULL;
-}
-
-/**
- * get the descriptor infos
- */
-int xilinx_get_descriptor_info( int desc_id, char* buffer )
-{
- int len = 0;
-
- if( desc_id >= 0 ) {
- len = xilinx_dump_descriptor_info( &target_fpga_desc[desc_id], buffer );
- }
- else { // all desc requested
- unsigned char i;
- for( i=0; i<NB_TARGET_DESC; i++ ) {
- len += xilinx_dump_descriptor_info( &target_fpga_desc[i], buffer+len );
- }
- }
-
- return len;
-}
-
-
+/*
+ * (c) Copyright 2006 Armadeus project
+ * Nicolas Colombain <nic...@ar...>
+ * Xilinx FPGA support
+ *
+ * Based on the implementation(uBoot) of:
+ * Rich Ireland, Enterasys Networks, rir...@en....
+ * Keith Outwater, kei...@mv...
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include "xilinx-fpga-loader.h"
+#include "target-fpga-loader.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+#include <linux/time.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+
+#define CONFIG_FPGA_DELAY()
+#define CFG_FPGA_WAIT 4000 // uS
+
+size_t bytecount = 0; // total bytes received
+extern Xilinx_desc target_fpga_desc[]; // target descriptor table
+
+/*
+ * Timeout function
+ */
+static unsigned long get_timer(unsigned long initTime)
+{
+ struct timeval tv;
+ do_gettimeofday(&tv);
+ if( tv.tv_usec > initTime ) // avoid overflow pb
+ return tv.tv_usec - initTime;
+ else
+ return initTime - tv.tv_usec;
+}
+
+/*
+ * dump the given descriptor infos
+ */
+static int xilinx_dump_descriptor_info( Xilinx_desc *desc, char* buffer )
+{
+ int len;
+ len = sprintf( buffer, "%s %s %u\n",
+ (desc->family == Xilinx_Spartan) ? "spartan":"unknown",
+ (desc->iface == slave_serial) ? "slave serial":"unknown",
+ desc->size );
+ return len;
+}
+
+/**
+ * program the FPGA.
+ * return 0 if success, >0 while programming, <0 if error detected
+ */
+static size_t spartan_serial_load (Xilinx_desc *desc, const char* buf, size_t bsize)
+{
+ Xilinx_Spartan_Slave_Serial_fns *fn = desc->iface_fns;
+ if (fn) {
+ unsigned long ts; /* timestamp */
+
+ /* Load the data */
+ if( bytecount<=desc->size ) {
+ int i;
+ unsigned char val;
+ size_t nbbyte = 0; // init local counter
+
+ while (nbbyte < bsize) {
+
+ /* Xilinx detects an error if INIT goes low (active)
+ while DONE is low (inactive) */
+ if ((*fn->done)() == 0 && (*fn->init)()) {
+ PRINTF ("** CRC error during FPGA load.\n");
+ return -ETIMEDOUT;
+ }
+ val = buf[nbbyte ++];
+ bytecount++;
+ i = 8;
+ do {
+ /* Deassert the clock */
+ (*fn->clk)(0);
+ CONFIG_FPGA_DELAY ();
+ /* Write data */
+ (*fn->wr)(val & 0x80);
+ CONFIG_FPGA_DELAY ();
+ /* Assert the clock */
+ (*fn->clk)(1);
+ CONFIG_FPGA_DELAY ();
+ val <<= 1;
+ i --;
+ } while (i > 0);
+ }
+ }
+ if( bytecount>=desc->size )
+ {
+ CONFIG_FPGA_DELAY ();
+
+ /* now check for done signal */
+ ts = get_timer(0); /* get current time */
+ (*fn->wr)(1);
+
+ while (! (*fn->done)()) {
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk)(0); /* Deassert the clock pin */
+ CONFIG_FPGA_DELAY ();
+ (*fn->clk)(1); /* Assert the clock pin */
+
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ PRINTF ("** Timeout waiting for DONE.\n");
+ return -ETIMEDOUT;
+ }
+ }
+ }
+ return bsize;
+ }
+ return -EINVAL;
+}
+
+/**
+ * initialize the FPGA programming interface.
+ * return 0 if success, <0 if error detected
+ */
+static int spartan_serial_init (Xilinx_desc *desc)
+{
+ Xilinx_Spartan_Slave_Serial_fns *fn = desc->iface_fns;
+ if (fn) {
+ unsigned long ts; /* timestamp */
+
+ if(*fn->pre){
+ (*fn->pre)(); //Run the pre configuration function if there is one.
+ }
+
+ /* Establish the initial state */
+ (*fn->pgm)(1); /* Assert the program, commit */
+
+ /* Wait for INIT state (init low) */
+ ts = get_timer(0); /* get current time */
+ do {
+ CONFIG_FPGA_DELAY ();
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ PRINTF ("** Timeout waiting for INIT to start.\n");
+ return -ETIMEDOUT;
+ }
+ } while (!(*fn->init)());
+
+ /* Get ready for the burn */
+ CONFIG_FPGA_DELAY ();
+ (*fn->pgm)(0); /* Deassert the program, commit */
+
+ ts = get_timer(0); /* get current time */
+ /* Now wait for INIT to go high */
+ do {
+ CONFIG_FPGA_DELAY ();
+ if (get_timer (ts) > CFG_FPGA_WAIT) { /* check the time */
+ PRINTF ("** Timeout waiting for INIT to clear.\n");
+ return -ETIMEDOUT;
+ }
+ } while ((*fn->init)());
+
+ bytecount = 0; // reset byte count
+ return 0; // success
+ }
+ return -EINVAL;
+}
+
+/**
+ * program the FPGA.
+ * return 0 if success, >0 while programming, <0 if error detected
+ */
+size_t xilinx_load( Xilinx_desc *desc, const char *buf, size_t bsize )
+{
+ int ret = 0;
+
+ if( desc ) {
+ switch( desc->family ) // check family
+ {
+ case Xilinx_Spartan:
+ {
+ switch( desc->iface ) // check donwload hardware interface
+ {
+ case slave_serial: ret = spartan_serial_load( desc, buf, bsize ); break;
+ default: PRINTF("interface not supported!\n"); ret = -ENOSYS; break;
+ }
+ }
+ break;
+ default: PRINTF("family not supported!\n"); ret = -ENOSYS; break;
+ }
+ }
+ else {
+ PRINTF("invalid FPGA descriptor!\n");
+ ret = -EINVAL;
+ }
+ return ret;
+}
+
+/**
+ * initialize the FPGA programming interface.
+ * return 0 if success, <0 if error detected
+ */
+int xilinx_init_load( Xilinx_desc *desc )
+{
+ int ret = 0;
+
+ if( desc ) {
+ switch( desc->family ) // check family
+ {
+ case Xilinx_Spartan:
+ {
+ switch( desc->iface ) // check donwload hardware interface
+ {
+ case slave_serial: ret = spartan_serial_init( desc ); break;
+ default: PRINTF("interface not supported!\n"); ret = -ENOSYS; break;
+ }
+ }
+ break;
+ default: PRINTF("family not supported!\n"); ret = -ENOSYS; break;
+ }
+ }
+ else {
+ PRINTF("invalid FPGA descriptor!\n");
+ ret = -EINVAL;
+ }
+ return ret;
+}
+
+/**
+ * get the descriptor corresponding to desc_id
+ * return NULL if error
+ */
+Xilinx_desc * xilinx_get_descriptor( unsigned char desc_id )
+{
+ if( desc_id < NB_TARGET_DESC ){
+ return &(target_fpga_desc[desc_id]);
+ }
+ return NULL;
+}
+
+/**
+ * get the descriptor infos
+ */
+int xilinx_get_descriptor_info( int desc_id, char* buffer )
+{
+ int len = 0;
+
+ if( desc_id >= 0 ) {
+ len = xilinx_dump_descriptor_info( &target_fpga_desc[desc_id], buffer );
+ }
+ else { // all desc requested
+ unsigned char i;
+ for( i=0; i<NB_TARGET_DESC; i++ ) {
+ len += xilinx_dump_descriptor_info( &target_fpga_desc[i], buffer+len );
+ }
+ }
+
+ return len;
+}
+
+
+
Modified: trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.h
===================================================================
--- trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.h 2008-12-04 07:26:29 UTC (rev 915)
+++ trunk/target/linux/modules/fpga/dev_tools/fpga_devtools/xilinx-fpga-loader.h 2008-12-04 09:40:44 UTC (rev 916)
@@ -1,117 +1,117 @@
-/*
- * (c) Copyright 2006 Armadeus project
- * Nicolas Colombain <nic...@ar...>
- * Xilinx FPGA support
- *
- * Based on the implementation(uBoot) of:
- * Rich Ireland, Enterasys Networks, rir...@en....
- * Keith Outwater, kei...@mv...
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+/*
+ * (c) Copyright 2006 Armadeus project
+ * Nicolas Colombain <nic...@ar...>
+ * Xilinx FPGA support
+ *
+ * Based on the implementation(uBoot) of:
+ * Rich Ireland, Enterasys Networks, rir...@en....
+ * Keith Outwater, kei...@mv...
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
*/
#ifndef __XILINX_FPGA_H__
#define __XILINX_FPGA_H__
-
-#include <linux/types.h>
-
-//#define FPGA_DEBUG
-#undef FPGA_DEBUG
-
-#ifdef FPGA_DEBUG
-#define PRINTF(fmt,args...) printk (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-
-
-/* Spartan-III */
-#define XILINX_XC3S50_SIZE 439264/8
-#define XILINX_XC3S200_SIZE 1047616/8
-#define XILINX_XC3S400_SIZE 1699136/8
-#define XILINX_XC3S1000_SIZE 3223488/8
-#define XILINX_XC3S1500_SIZE 5214784/8
-#define XILINX_XC3S2000_SIZE 7673024/8
-#define XILINX_XC3S4000_SIZE 11316864/8
-#define XILINX_XC3S5000_SIZE 13271936/8
-
-
-typedef enum { /* typedef Xilinx_iface */
- min_xilinx_iface_type, /* low range check value */
- slave_serial, /* serial data and external clock */
- max_xilinx_iface_type /* insert all new types before this */
-} Xilinx_iface; /* end, typedef Xilinx_iface */
-
-typedef enum { /* typedef Xilinx_Family */
- min_xilinx_type, /* low range check value */
- Xilinx_Spartan, /* Spartan-II Family */
- max_xilinx_type /* insert all new types before this */
-} Xilinx_Family; /* end, typedef Xilinx_Family */
-
-typedef struct { /* typedef Xilinx_desc */
- Xilinx_Family family; /* part type */
- Xilinx_iface iface; /* interface type */
- size_t size; /* bytes of data part can accept */
- void * iface_fns; /* interface function table */
-} Xilinx_desc; /* end, typedef Xilinx_desc */
-
-
-/** pointer to target specific low level function */
-typedef int (*Xilinx_pgm_fn)( int assert_pgm );
-typedef int (*Xilinx_init_fn)(void);
-typedef int (*Xilinx_done_fn)(void);
-typedef int (*Xilinx_clk_fn)( int assert_clk );
-typedef int (*Xilinx_wr_fn)( int assert_write );
-typedef int (*Xilinx_pre_fn)(void);
-
-/** struct of target specific low level functions */
-typedef struct {
- Xilinx_pre_fn pre;
- Xilinx_pgm_fn pgm;
- Xilinx_clk_fn clk;
- Xilinx_init_fn init;
- Xilinx_done_fn done;
- Xilinx_wr_fn wr;
-} Xilinx_Spartan_Slave_Serial_fns;
-
-/**
- * program the FPGA.
- * return 0 if success, >0 while programming, <0 if error detected
- */
-size_t xilinx_load( Xilinx_desc *desc, const char *buf, size_t bsize );
-
-/**
- * initialize the FPGA programming interface.
- * return 0 if success, <0 if error detected
- */
-int xilinx_init_load( Xilinx_desc *desc );
-
-/**
- * get the descriptor infos, return the number of char placed in the buffer
- */
-int xilinx_get_descriptor_info( int desc_id, char* buffer);
-
-/**
- * get the descriptor corresponding to desc_id
- * return NULL if error
- */
-Xilinx_desc * xilinx_get_descriptor( unsigned char desc_id );
-
+
+#include <linux/types.h>
+
+//#define FPGA_DEBUG
+#undef FPGA_DEBUG
+
+#ifdef FPGA_DEBUG
+#define PRINTF(fmt,args...) printk (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+
+
+/* Spartan-III */
+#define XILINX_XC3S50_SIZE 439264/8
+#define XILINX_XC3S200_SIZE 1047616/8
+#define XILINX_XC3S400_SIZE 1699136/8
+#define XILINX_XC3S1000_SIZE 3223488/8
+#define XILINX_XC3S1500_SIZE 5214784/8
+#define XILINX_XC3S2000_SIZE 7673024/8
+#define XILINX_XC3S4000_SIZE 11316864/8
+#define XILINX_XC3S5000_SIZE 13271936/8
+
+
+typedef enum { /* typedef Xilinx_iface */
+ min_xilinx_iface_type, /* low range check value */
+ slave_serial, /* serial data and external clock */
+ max_xilinx_iface_type /* insert all new types before this */
+} Xilinx_iface; /* end, typedef Xilinx_iface */
+
+typedef enum { /* typedef Xilinx_Family */
+ min_xilinx_type, /* low range check value */
+ Xilinx_Spartan, /* Spartan-II Family */
+ max_xilinx_type /* insert all new types before this */
+} Xilinx_Family; /* end, typedef Xilinx_Family */
+
+typedef struct { /* typedef Xilinx_desc */
+ Xilinx_Family family; /* part type */
+ Xilinx_iface iface; /* interface type */
+ size_t size; /* bytes of data part can accept */
+ void * iface_fns; /* interface function table */
+} Xilinx_desc; /* end, typedef Xilinx_desc */
+
+
+/** pointer to target specific low level function */
+typedef int (*Xilinx_pgm_fn)( int assert_pgm );
+typedef int (*Xilinx_init_fn)(void);
+typedef int (*Xilinx_done_fn)(void);
+typedef int (*Xilinx_clk_fn)( int assert_clk );
+typedef int (*Xilinx_wr_fn)( int assert_write );
+typedef int (*Xilinx_pre_fn)(void);
+
+/** struct of target specific low level functions */
+typedef struct {
+ Xilinx_pre_fn pre;
+ Xilinx_pgm_fn pgm;
+ Xilinx_clk_fn clk;
+ Xilinx_init_fn init;
+ Xilinx_done_fn done;
+ Xilinx_wr_fn wr;
+} Xilinx_Spartan_Slave_Serial_fns;
+
+/**
+ * program the FPGA.
+ * return 0 if success, >0 while programming, <0 if error detected
+ */
+size_t xilinx_load( Xilinx_desc *desc, const char *buf, size_t bsize );
+
+/**
+ * initialize the FPGA programming interface.
+ * return 0 if success, <0 if error detected
+ */
+int xilinx_init_load( Xilinx_desc *desc );
+
+/**
+ * get the descriptor infos, return the number of char placed in the buffer
+ */
+int xilinx_get_descriptor_info( int desc_id, char* buffer);
+
+/**
+ * get the descriptor corresponding to desc_id
+ * return NULL if error
+ */
+Xilinx_desc * xilinx_get_descriptor( unsigned char desc_id );
+
#endif // __XILINX_FPGA_H__
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