[Armadeus-commitlog] SF.net SVN: armadeus:[895] trunk/target/linux/modules/fpga/others/i2ctest
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[Armadeus-commitlog] SF.net SVN: armadeus:[895] trunk/target/linux/modules/fpga/others/i2ctest
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From: <Fa...@us...> - 2008-10-17 16:52:27
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Revision: 895
http://armadeus.svn.sourceforge.net/armadeus/?rev=895&view=rev
Author: FabM
Date: 2008-10-17 16:52:24 +0000 (Fri, 17 Oct 2008)
Log Message:
-----------
[DRIVER][FPGA] Unit test driver for i2c_ocores IP
Modified Paths:
--------------
trunk/target/linux/modules/fpga/others/i2ctest/README
trunk/target/linux/modules/fpga/others/i2ctest/i2ctest.c
trunk/target/linux/modules/fpga/others/i2ctest/i2ctest.h
Modified: trunk/target/linux/modules/fpga/others/i2ctest/README
===================================================================
--- trunk/target/linux/modules/fpga/others/i2ctest/README 2008-10-16 11:38:03 UTC (rev 894)
+++ trunk/target/linux/modules/fpga/others/i2ctest/README 2008-10-17 16:52:24 UTC (rev 895)
@@ -1,6 +1,9 @@
This is a really simple driver to test reading and writing
-a value on i2c bus throught ocore-irq_mng FPGA IP.
+a value on i2c memory component throught ocore-irq_mng FPGA IP.
+Frames are like :
+START+ADDR+ACK+SUBADDR+ACK+REPSTART+ADDR+ACK+VALUE+ACK+STOP
+
To use it load i2ctest.ko module with insmod
>insmod i2ctest.ko
Modified: trunk/target/linux/modules/fpga/others/i2ctest/i2ctest.c
===================================================================
--- trunk/target/linux/modules/fpga/others/i2ctest/i2ctest.c 2008-10-16 11:38:03 UTC (rev 894)
+++ trunk/target/linux/modules/fpga/others/i2ctest/i2ctest.c 2008-10-17 16:52:24 UTC (rev 895)
@@ -23,203 +23,230 @@
#include "i2ctest.h"
-#define VALUE 0xbb
-#define ADDR 0x1D
-#define SUBADDR 0x16
-
-
/***************************
* interrupt management
* *************************/
static irqreturn_t fpga_interrupt(int irq,void *stuff,struct pt_regs *reg){
- static int count = 0;
- u16 data;
+ static int count = 0;
+ u16 data;
- /**************/
- /* write 0xbb */
- /**************/
- if(count == 0){
- /*read RxACK bit from Status Register, should be 0 */
- ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
- /* write to Transmit sub address, set WR bit acknowledge interrupt*/
- iowrite16(SUBADDR<<8|I2C_WR|I2C_IACK,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
- /* acknowledge irq in irq manager*/
- iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
- count++;
- }else if(count == 1){
- ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
- /* write to Transmit sub address, set WR bit acknowledge interrupt*/
- iowrite16(VALUE<<8|I2C_STO|I2C_WR|I2C_IACK,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
- /* acknowledge irq in irq manager*/
- iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
- count ++;
- }else if(count == 2){
- ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
- iowrite16(0x0000|I2C_IACK|I2C_STO,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
- /* acknowledge irq in irq manager*/
- iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
- count++;
+ /***************/
+ /* write VALUE */
+ /***************/
+ if(count == 0){
+ /*read RxACK bit from Status Register, should be 0 */
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_SR);
+ /* write to Transmit sub address, set WR bit acknowledge interrupt*/
+ iowrite16(SUBADDR,i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR);
+ iowrite16(I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
- /***********************/
- /* read the same value */
- /***********************/
- }else if(count == 3){
- /*read RxACK bit from Status Register, should be 0 */
- ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
- /* write 0x2C to Transmit sub address, set WR bit acknowledge interrupt*/
- iowrite16(SUBADDR<<8|I2C_WR|I2C_IACK,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
- /* acknowledge irq in irq manager*/
- iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
- count++;
- }else if(count == 4){
- ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
- /* write adress on TXR and CTR register repeated start, acknowledge interrupt*/
- iowrite16(ADDR<<9|I2C_ADD_READ|I2C_STA|I2C_WR|I2C_IACK,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
- /* acknowledge irq in irq manager*/
- iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
- count++;
- }else if(count == 5){
- /* write on TXR and CTR register, set read bit,acknowledge interrupt*/
+ /* acknowledge irq in irq manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 1){
+ /*read RxACK bit from Status Register, should be 0 */
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_SR);
+
+ /* write to Transmit sub address, set WR bit acknowledge interrupt*/
+ iowrite16(ADDR<<1|I2C_ADD_WRITE,i2cdev->fpga_virtual_base_address+FPGA_I2C_TXR);
+ iowrite16(I2C_STA|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
+
+ /* acknowledge irq in irq manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count ++;
+ }else if(count == 2){
+ /*read RxACK bit from Status Register, should be 0 */
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_SR);
+ /* write VALUE, set WR bit acknowledge interrupt*/
+ iowrite16(VALUE,i2cdev->fpga_virtual_base_address+FPGA_I2C_TXR);
+ iowrite16(I2C_IACK|I2C_WR|I2C_STO,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
+
+ /* acknowledge irq in irq manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 3){
+ /*read RxACK bit from Status Register, should be 0 */
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_SR);
+ /* acknowledge interruption */
+ iowrite16(I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
+ /* acknowledge irq in irq manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+
+ }else if(count == 4){/**************READ THE VALUE ****************/
+ /*read RxACK bit from Status Register, should be 0 */
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_SR);
+
+ /* write 0x2C to Transmit sub address, set WR bit acknowledge interrupt*/
+ iowrite16(SUBADDR,i2cdev->fpga_virtual_base_address+FPGA_I2C_TXR);
+ iowrite16(I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
+
+ /* acknowledge irq in irq manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 5){
+ /*read RxACK bit from Status Register, should be 0 */
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_SR);
+ /* write adress on TXR and CTR register repeated start, acknowledge interrupt*/
+ iowrite16(ADDR<<1|I2C_ADD_READ,i2cdev->fpga_virtual_base_address+FPGA_I2C_TXR);
+ iowrite16(I2C_STA|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
+
+ /* acknowledge irq in irq manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 6){
+ /* write on TXR and CTR register, set read bit,acknowledge interrupt*/
iowrite16(I2C_RD|I2C_ACK|I2C_IACK|I2C_STO,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
- /* acknowledge irq in irq manager*/
- iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
- count++;
- }else if(count == 6){
- data = ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
- /* write on TXR and CTR register, set read bit,acknowledge interrupt*/
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
+
+ /* acknowledge irq in irq manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 7){
+ /*read RxACK bit from Status Register, should be 0 */
+ data = ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_SR);
+ /* read the value */
+ data = ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXR);
+ /* write on TXR and CTR register, set read bit,acknowledge interrupt*/
iowrite16(I2C_IACK,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
- /* acknowledge irq in irq manager*/
- iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ /* acknowledge irq in irq manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
- printk(KERN_INFO "read %04x\n",data);
- count++;
- }
- return IRQ_HANDLED;
+ printk(KERN_INFO "read %04x\n",data);
+ count++;
+ }
+ return IRQ_HANDLED;
}
/****************************
* read proc
* **************************/
-static int read_proc(char *page,char **start,off_t offset,int count,int *eof,void *data){
- /* if(down_interruptible(&i2cdev->sem))
- return -ERESTARTSYS;*/
+static int read_proc(char *page,char **start,off_t offset,
+ int count,int *eof,void *data)
+{
+ PDEBUG("Trying to write %04x on i2c slave\n",VALUE);
- PDEBUG("Trying to write %04x on i2c slave\n",VALUE);
-
- /* unmask interrupt for i2c in interrupt manager*/
- iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_MASK);
- /* set prescale for 400kHz*/
- iowrite16(0x00BF,i2cdev->fpga_virtual_base_address + FPGA_I2C_PRESC);
- PDEBUG("Write %04x at %04x\n",0x00BF,FPGA_I2C_PRESC);
- /* set core enable and interrupt enable*/
- iowrite16(I2C_EN|I2C_IEN,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_CTR);
- PDEBUG("Write %04x at %04x\n",I2C_EN|I2C_IEN,FPGA_I2C_CTR);
- /* write slave adresse on TXR and CTR register*/
- iowrite16(ADDR<<9|I2C_STA|I2C_WR|I2C_IACK,i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ /* unmask interrupt for i2c in interrupt manager*/
+ iowrite16(IRQ,i2cdev->fpga_virtual_base_address + FPGA_IRQ_MASK);
- PDEBUG("Write %04x at %04x\n",ADDR<<9|I2C_ADD_WRITE|I2C_STA|I2C_WR,FPGA_I2C_TXR_CR);
+ /* set prescale */
+ iowrite16(PRELo,i2cdev->fpga_virtual_base_address + FPGA_I2C_PRESCLo);
+ PDEBUG("Write %04x at %04x\n",PRELo,FPGA_I2C_PRESCLo);
+ iowrite16(PREHi,i2cdev->fpga_virtual_base_address + FPGA_I2C_PRESCHi);
+ PDEBUG("Write %04x at %04x\n",PRELo,FPGA_I2C_PRESCHi);
- /* PDEBUG("Wrote ?\n");*/
-
-/* up(&i2cdev->sem);*/
- return 0;
+ /* set core enable and interrupt enable*/
+ iowrite16(I2C_EN|I2C_IEN,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CTR);
+ PDEBUG("Write %04x at %04x\n",I2C_EN|I2C_IEN,FPGA_I2C_CTR);
+
+ /* write slave adresse on TXR */
+ iowrite16(ADDR<<1|I2C_ADD_WRITE,i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR);
+ /* and CTR register*/
+ iowrite16(I2C_STA|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address+FPGA_I2C_CR);
+ PDEBUG("Write %04x at %04x\n",I2C_STA|I2C_WR,FPGA_I2C_TXR);
+
+ return 0;
}
-static int read_proc2(char *page,char **start,off_t offset,int count,int *eof,void *data){
+static int read_proc2(char *page,char **start,off_t offset,int count,
+ int *eof,void *data)
+{
+ PDEBUG("Trying to read on i2c slave\n");
- PDEBUG("Trying to read on i2c slave\n");
-
- /* write slave adresse on TXR and CTR register*/
- iowrite16(ADDR<<9|I2C_ADD_WRITE|I2C_STA|I2C_WR|I2C_IACK,
- i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
- return 0;
+ /* write slave adresse on TXR*/
+ iowrite16(ADDR<<1|I2C_ADD_WRITE,i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR);
+ /* write ctr register*/
+ iowrite16(I2C_ADD_WRITE|I2C_STA|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CR);
+ return 0;
}
/****************************
-* Module management
-* **************************/
+ * Module management
+ * **************************/
static int __init i2ctest_init(void){
- int result;
- u16 data;
- result = 0;
+ int result;
+ u16 data;
+ result = 0;
- mem = NULL;
+ mem = NULL;
- /* Allocate a private structure and reference it as driver's data */
- PDEBUG("Allocate a private structure and reference it as driver s data\n");
- i2cdev = (struct i2ctest_dev *)kmalloc(sizeof(struct i2ctest_dev),GFP_KERNEL);
- if(i2cdev == NULL){
- printk(KERN_WARNING "I2CDEV: unable to allocate private structure\n");
- return -ENOMEM;
- }
+ /* Allocate a private structure and reference it as driver's data */
+ PDEBUG("Allocate a private structure and reference it as driver s data\n");
+ i2cdev = (struct i2ctest_dev *)kmalloc(sizeof(struct i2ctest_dev),GFP_KERNEL);
+ if(i2cdev == NULL){
+ printk(KERN_WARNING "I2CDEV: unable to allocate private structure\n");
+ return -ENOMEM;
+ }
- /* Requested I/O memory */
- if((i2cdev->fpga_virtual_base_address = ioremap(IMX_CS1_PHYS,IMX_CS1_SIZE))==NULL){
- printk(KERN_ERR "ioremap error\n");
- goto error;
- }
+ /* Requested I/O memory */
+ if((i2cdev->fpga_virtual_base_address = ioremap(IMX_CS1_PHYS,IMX_CS1_SIZE))==NULL){
+ printk(KERN_ERR "ioremap error\n");
+ goto error;
+ }
- /* irq registering */
- if(request_irq(IRQ_GPIOA(1),(irq_handler_t)fpga_interrupt,IRQF_SHARED,"fpga",i2cdev)<0){
- printk(KERN_ERR "Can't request fpga irq\n");
- goto error;
- }
- //ioread16(i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
- /* irq ack */
- data=1;
- if((result=iowrite16(data,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK))<0)
- goto error;
+ /* irq registering */
+ if(request_irq(IRQ_GPIOA(1),(irq_handler_t)fpga_interrupt,IRQF_SHARED,"fpga",i2cdev)<0){
+ printk(KERN_ERR "Can't request fpga irq\n");
+ goto error;
+ }
+ //ioread16(i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ /* irq ack */
+ data=IRQ;
+ if((result=iowrite16(data,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK))<0)
+ goto error;
- /* create proc entry */
- create_proc_read_entry("i2c_test",0 /* default mode */,
- NULL /* parent dir */, read_proc,
- NULL /* client data */);
+ /* create proc entry */
+ create_proc_read_entry("i2c_test",0 /* default mode */,
+ NULL /* parent dir */, read_proc,
+ NULL /* client data */);
- /* create proc entry */
- create_proc_read_entry("i2c_test2",0 /* default mode */,
- NULL /* parent dir */, read_proc2,
- NULL /* client data */);
+ /* create proc entry */
+ create_proc_read_entry("i2c_test2",0 /* default mode */,
+ NULL /* parent dir */, read_proc2,
+ NULL /* client data */);
- /* OK module inserted ! */
- printk(KERN_INFO "i2ctest module insered\n");
- return 0;
+ /* OK module inserted ! */
+ printk(KERN_INFO "i2ctest module insered\n");
+ return 0;
error:
- printk(KERN_ERR "%s: not inserted\n",DRIVER_NAME);
- free_all();
- return result;
+ printk(KERN_ERR "%s: not inserted\n",DRIVER_NAME);
+ free_all();
+ return result;
}
static void __exit i2ctest_exit(void){
- free_all();
+ free_all();
}
static void free_all(void){
-
- /* free irq*/
- free_irq(IRQ_GPIOA(1),i2cdev);
- /* Free the allocated memory */
- kfree(i2cdev);
+ /* free irq*/
+ free_irq(IRQ_GPIOA(1),i2cdev);
- /* remove proc entry */
- remove_proc_entry("i2c_test",0);
+ /* Free the allocated memory */
+ kfree(i2cdev);
- printk(KERN_INFO "i2ctest module deleted\n");
+ /* remove proc entry */
+ remove_proc_entry("i2c_test",0);
+
+ printk(KERN_INFO "i2ctest module deleted\n");
}
Modified: trunk/target/linux/modules/fpga/others/i2ctest/i2ctest.h
===================================================================
--- trunk/target/linux/modules/fpga/others/i2ctest/i2ctest.h 2008-10-16 11:38:03 UTC (rev 894)
+++ trunk/target/linux/modules/fpga/others/i2ctest/i2ctest.h 2008-10-17 16:52:24 UTC (rev 895)
@@ -73,38 +73,51 @@
# define PDEBUG(fmt,args...) /* no debbuging message */
#endif
-#define FPGA_BUTTON 8
-#define FPGA_LED 4
-#define FPGA_IRQ_MASK 0
-#define FPGA_IRQ_PEND 2
-#define FPGA_IRQ_ACK 2
+/* Addresses */
+#define FPGA_IRQ_MASK (0x0)
+#define FPGA_IRQ_PEND (0x2)
+#define FPGA_IRQ_ACK (0x2)
-#define FPGA_I2C_PRESC 0x10
-#define FPGA_I2C_CTR 0x12
-#define FPGA_I2C_TXR_CR 0x14
-#define FPGA_I2C_RXT_SR 0x16
+#define FPGA_BASE_ADDR (0x20)
+#define FPGA_I2C_PRESCLo (FPGA_BASE_ADDR+0x0)
+#define FPGA_I2C_PRESCHi (FPGA_BASE_ADDR+0x2)
+#define FPGA_I2C_CTR (FPGA_BASE_ADDR+0x4)
+#define FPGA_I2C_TXR (FPGA_BASE_ADDR+0xA)
+#define FPGA_I2C_RXR (FPGA_BASE_ADDR+0xE)
+#define FPGA_I2C_CR (FPGA_BASE_ADDR+0x8)
+#define FPGA_I2C_SR (FPGA_BASE_ADDR+0xC)
+/* Values */
+#define PRELo (0xBF)
+#define PREHi (0x00)
+/* read/write (accelerometer)*/
+#define ADDR (0x1D) /* lis3lv02dl */
+#define SUBADDR (0x16) /* OFFSET_X */
+#define VALUE (0xBB)
+
+/* irq position in irqmngr */
+#define IRQ (0x01)
+
+
/* CTR register */
-#define I2C_EN 0x80
-#define I2C_IEN 0x40
+#define I2C_EN (0x80)
+#define I2C_IEN (0x40)
+
/* CR register */
-#define I2C_STA 0x80
-#define I2C_STO 0x40
-#define I2C_RD 0x20
-#define I2C_WR 0x10
-#define I2C_ACK 0x08
-#define I2C_IACK 0x01
+#define I2C_STA (0x80)
+#define I2C_STO (0x40)
+#define I2C_RD (0x20)
+#define I2C_WR (0x10)
+#define I2C_ACK (0x08)
+#define I2C_IACK (0x01)
-#define I2C_ADD_READ 0x0100
-#define I2C_ADD_WRITE 0
+/* read/write bit */
+#define I2C_ADD_READ (0x01)
+#define I2C_ADD_WRITE (0x00)
#define DRIVER_NAME "i2ctest"
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Fabien Marteau <fab...@ar...> - ARMadeus Systems");
-MODULE_DESCRIPTION("I2C tester");
-
struct i2ctest_dev {
struct semaphore sem;
void * fpga_virtual_base_address;
@@ -117,11 +130,19 @@
static int __init i2ctest_init(void);
static void __exit i2ctest_exit(void);
-static int read_proc(char *page,char **start,off_t offset,int count,int *eof,void *data);
-static int read_proc2(char *page,char **start,off_t offset,int count,int *eof,void *data);
+static int read_proc(char *page, char **start, off_t offset,
+ int count,int *eof,void *data);
+static int read_proc2(char *page,char **start,off_t offset,
+ int count,int *eof,void *data);
static void free_all(void);
-static irqreturn_t fpga_interrupt(int irq,void *stuff,struct pt_regs *reg);
-
+static irqreturn_t fpga_interrupt(int irq,void *stuff,
+ struct pt_regs *reg);
module_init(i2ctest_init);
module_exit(i2ctest_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Fabien Marteau <fab...@ar...> - ARMadeus Systems");
+MODULE_DESCRIPTION("I2C tester");
+
+
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