[Armadeus-commitlog] SF.net SVN: armadeus:[878] branches/apf2/target/linux/debug/imxregs
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[Armadeus-commitlog] SF.net SVN: armadeus:[878] branches/apf2/target/linux/debug/imxregs
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From: <ar...@us...> - 2008-09-10 14:04:26
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Revision: 878
http://armadeus.svn.sourceforge.net/armadeus/?rev=878&view=rev
Author: artemys
Date: 2008-09-10 14:04:36 +0000 (Wed, 10 Sep 2008)
Log Message:
-----------
[LINUX_DEBUG] Add i.MX27 support to imxregs tool
Modified Paths:
--------------
branches/apf2/target/linux/debug/imxregs/Makefile
branches/apf2/target/linux/debug/imxregs/imxregs.c
branches/apf2/target/linux/debug/imxregs/imxregs.h
Added Paths:
-----------
branches/apf2/target/linux/debug/imxregs/README
branches/apf2/target/linux/debug/imxregs/definitions.h
branches/apf2/target/linux/debug/imxregs/imx27regs.h
branches/apf2/target/linux/debug/imxregs/txt_copy_of_pdf_to_include.sh
Modified: branches/apf2/target/linux/debug/imxregs/Makefile
===================================================================
--- branches/apf2/target/linux/debug/imxregs/Makefile 2008-09-09 20:40:58 UTC (rev 877)
+++ branches/apf2/target/linux/debug/imxregs/Makefile 2008-09-10 14:04:36 UTC (rev 878)
@@ -1,9 +1,15 @@
+ifeq ($(CC),cc)
+ CC=arm-linux-gcc
+endif
-all: imxregs
+all: imxregs imx27regs
-imxregs: imxregs.c imxregs.h
- arm-linux-gcc imxregs.c -o $@
-
+imxregs: imxregs.c imxregs.h definitions.h
+ $(CC) imxregs.c -o $@
+
+imx27regs: imxregs.c imx27regs.h definitions.h
+ $(CC) -DIMX27 imxregs.c -o $@
+
clean:
rm -f *.o
- rm -f imxregs
+ rm -f imxregs imx27regs
Added: branches/apf2/target/linux/debug/imxregs/README
===================================================================
--- branches/apf2/target/linux/debug/imxregs/README (rev 0)
+++ branches/apf2/target/linux/debug/imxregs/README 2008-09-10 14:04:36 UTC (rev 878)
@@ -0,0 +1,3 @@
+To compile:
+ $ make CC=../../../../buildroot/build_arm/staging_dir/bin/arm-linux-gcc
+
Added: branches/apf2/target/linux/debug/imxregs/definitions.h
===================================================================
--- branches/apf2/target/linux/debug/imxregs/definitions.h (rev 0)
+++ branches/apf2/target/linux/debug/imxregs/definitions.h 2008-09-10 14:04:36 UTC (rev 878)
@@ -0,0 +1,36 @@
+/*
+ * definitions.h - imxregs common definitions
+ *
+ * Copyright (C) 2008 armadeus systems
+ * Author: Julien Boibessot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+typedef unsigned int u32;
+
+struct reg_info {
+ char *name;
+ u32 addr;
+ int shift;
+ u32 mask;
+ char type;
+ char *desc;
+};
+
+// Size of mmapping:
+#define MAP_SIZE 4096
+#define MAP_MASK ( MAP_SIZE - 1 )
Added: branches/apf2/target/linux/debug/imxregs/imx27regs.h
===================================================================
--- branches/apf2/target/linux/debug/imxregs/imx27regs.h (rev 0)
+++ branches/apf2/target/linux/debug/imxregs/imx27regs.h 2008-09-10 14:04:36 UTC (rev 878)
@@ -0,0 +1,1297 @@
+/*
+ * imx27regs.h - i.MX27 registers definition
+ *
+ * Copyright (C) 2008 armadeus systems
+ * Derivated from pxaregs (c) Copyright 2002 by M&N Logistik-Loesungen Online GmbH
+ * Author: Julien Boibessot
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include "definitions.h"
+
+static struct reg_info regs[] =
+{
+// AIPI1
+{ "PSR0", 0x10000000, 0, 0xffffffff, 'x', "Peripheral Size Register 0" },
+{ "PSR1", 0x10000004, 0, 0xffffffff, 'x', "Peripheral Size Register 1" },
+{ "PAR", 0x10000008, 0, 0xffffffff, 'x', "Peripheral Access Register" },
+{ "AAOR", 0x1000000C, 0, 0xffffffff, 'x', "Atomic Access Only Register" },
+// DMAC
+{ "DCR", 0x10001000, 0, 0xffffffff, 'x', "DMA Control Register" },
+{ "DISR", 0x10001004, 0, 0xffffffff, 'x', "DMA Interrupt Status Register" },
+{ "DIMR", 0x10001008, 0, 0xffffffff, 'x', "DMA Interrupt Mask Register" },
+{ "DBTOSR", 0x1000100C, 0, 0xffffffff, 'x', "DMA Burst Time-Out Status Register" },
+{ "DRTOSR", 0x10001010, 0, 0xffffffff, 'x', "DMA Request Time-Out Status Register" },
+{ "DSESR", 0x10001014, 0, 0xffffffff, 'x', "DMA Transfer Error Status Register" },
+{ "DBOSR", 0x10001018, 0, 0xffffffff, 'x', "DMA Buffer Overflow Status Register" },
+{ "DBTOCR", 0x1000101C, 0, 0xffffffff, 'x', "DMA Burst Time-Out Control Register" },
+{ "WSRA", 0x10001040, 0, 0xffffffff, 'x', "W-Size Register A" },
+{ "XSRA", 0x10001044, 0, 0xffffffff, 'x', "X-Size Register A" },
+{ "YSRA", 0x10001048, 0, 0xffffffff, 'x', "Y-Size Register A" },
+{ "WSRB", 0x1000104C, 0, 0xffffffff, 'x', "W-Size Register B" },
+{ "XSRB", 0x10001050, 0, 0xffffffff, 'x', "X-Size Register B" },
+{ "YSRB", 0x10001054, 0, 0xffffffff, 'x', "Y-Size Register B" },
+{ "SAR0", 0x10001080, 0, 0xffffffff, 'x', "Channel 0 Source Address Register" },
+{ "DAR0", 0x10001084, 0, 0xffffffff, 'x', "Channel 0 Destination Address Register" },
+{ "CNTR0", 0x10001088, 0, 0xffffffff, 'x', "Channel 0 Count Register" },
+{ "CCR0", 0x1000108C, 0, 0xffffffff, 'x', "Channel 0 Control Register" },
+{ "RSSR0", 0x10001090, 0, 0xffffffff, 'x', "Channel 0 Request Source Select Register" },
+{ "BLR0", 0x10001094, 0, 0xffffffff, 'x', "Channel 0 Burst Length Register" },
+{ "RTOR0", 0x10001098, 0, 0xffffffff, 'x', "Channel 0 Request Time-Out Register" },
+{ "BUCR0", 0x10001098, 0, 0xffffffff, 'x', "Channel 0 Bus Utilization Control Register" },
+{ "CCNR0", 0x1000109C, 0, 0xffffffff, 'x', "Channel 0 Channel Counter Register" },
+{ "SAR1", 0x100010C0, 0, 0xffffffff, 'x', "Channel 1 Source Address Register" },
+{ "DAR1", 0x100010C4, 0, 0xffffffff, 'x', "Channel 1 Destination Address Register" },
+{ "CNTR1", 0x100010C8, 0, 0xffffffff, 'x', "Channel 1 Count Register" },
+{ "CCR1", 0x100010CC, 0, 0xffffffff, 'x', "Channel 1 Control Register" },
+{ "RSSR1", 0x100010D0, 0, 0xffffffff, 'x', "Channel 1 Request Source Select Register" },
+{ "BLR1", 0x100010D4, 0, 0xffffffff, 'x', "Channel 1 Burst Length Register" },
+{ "RTOR1", 0x100010D8, 0, 0xffffffff, 'x', "Channel 1 Request Time-Out Register" },
+{ "BUCR1", 0x100010D8, 0, 0xffffffff, 'x', "Channel 1 Bus Utilization Control Register" },
+{ "CCNR1", 0x100010DC, 0, 0xffffffff, 'x', "Channel 1 Channel Counter Register" },
+{ "SAR2", 0x10001100, 0, 0xffffffff, 'x', "Channel 2 Source Address Register" },
+{ "DAR2", 0x10001104, 0, 0xffffffff, 'x', "Channel 2 Destination Address Register" },
+{ "CNTR2", 0x10001108, 0, 0xffffffff, 'x', "Channel 2 Count Register" },
+{ "CCR2", 0x1000110C, 0, 0xffffffff, 'x', "Channel 2 Control Register" },
+{ "RSSR2", 0x10001110, 0, 0xffffffff, 'x', "Channel 2 Request Source Select Register" },
+{ "BLR2", 0x10001114, 0, 0xffffffff, 'x', "Channel 2 Burst Length Register" },
+{ "RTOR2", 0x10001118, 0, 0xffffffff, 'x', "Channel 2 Request Time-Out Register" },
+{ "BUCR2", 0x10001118, 0, 0xffffffff, 'x', "Channel 2 Bus Utilization Control Register" },
+{ "CCNR2", 0x1000111C, 0, 0xffffffff, 'x', "Channel 2 Channel Counter Register" },
+{ "SAR3", 0x10001140, 0, 0xffffffff, 'x', "Channel 3 Source Address Register" },
+{ "DAR3", 0x10001144, 0, 0xffffffff, 'x', "Channel 3 Destination Address Register" },
+{ "CNTR3", 0x10001148, 0, 0xffffffff, 'x', "Channel 3 Count Register" },
+{ "CCR3", 0x1000114C, 0, 0xffffffff, 'x', "Channel 3 Control Register" },
+{ "RSSR3", 0x10001150, 0, 0xffffffff, 'x', "Channel 3 Request Source Select Register" },
+{ "BLR3", 0x10001154, 0, 0xffffffff, 'x', "Channel 3 Burst Length Register" },
+{ "RTOR3", 0x10001158, 0, 0xffffffff, 'x', "Channel 3 Request Time-Out Register" },
+{ "BUCR3", 0x10001158, 0, 0xffffffff, 'x', "Channel 3 Bus Utilization Control Register" },
+{ "CCNR3", 0x1000115C, 0, 0xffffffff, 'x', "Channel 3 Channel Counter Register" },
+{ "SAR4", 0x10001180, 0, 0xffffffff, 'x', "Channel 4 Source Address Register" },
+{ "DAR4", 0x10001184, 0, 0xffffffff, 'x', "Channel 4 Destination Address Register" },
+{ "CNTR4", 0x10001188, 0, 0xffffffff, 'x', "Channel 4 Count Register" },
+{ "CCR4", 0x1000118C, 0, 0xffffffff, 'x', "Channel 4 Control Register" },
+{ "RSSR4", 0x10001190, 0, 0xffffffff, 'x', "Channel 4 Request Source Select Register" },
+{ "BLR4", 0x10001194, 0, 0xffffffff, 'x', "Channel 4 Burst Length Register" },
+{ "RTOR4", 0x10001198, 0, 0xffffffff, 'x', "Channel 4 Request Time-Out Register" },
+{ "BUCR4", 0x10001198, 0, 0xffffffff, 'x', "Channel 4 Bus Utilization Control Register" },
+{ "CCNR", 0x1000119C, 0, 0xffffffff, 'x', "4 Channel 4 Channel Counter Register" },
+{ "SAR5", 0x100011C0, 0, 0xffffffff, 'x', "Channel 5 Source Address Register" },
+{ "DAR5", 0x100011C4, 0, 0xffffffff, 'x', "Channel 5 Destination Address Register" },
+{ "CNTR5", 0x100011C8, 0, 0xffffffff, 'x', "Channel 5 Count Register" },
+{ "CCR5", 0x100011CC, 0, 0xffffffff, 'x', "Channel 5 Control Register" },
+{ "RSSR5", 0x100011D0, 0, 0xffffffff, 'x', "Channel 5 Request Source Select Register" },
+{ "BLR5", 0x100011D4, 0, 0xffffffff, 'x', "Channel 5 Burst Length Register" },
+{ "RTOR5", 0x100011D8, 0, 0xffffffff, 'x', "Channel 5 Request Time-Out Register" },
+{ "BUCR5", 0x100011D8, 0, 0xffffffff, 'x', "Channel 5 Bus Utilization Control Register" },
+{ "CCNR5", 0x100011DC, 0, 0xffffffff, 'x', "Channel 5 Channel Counter Register" },
+{ "SAR6", 0x10001200, 0, 0xffffffff, 'x', "Channel 6 Source Address Register" },
+{ "DAR6", 0x10001204, 0, 0xffffffff, 'x', "Channel 6 Destination Address Register" },
+{ "CNTR6", 0x10001208, 0, 0xffffffff, 'x', "Channel 6 Count Register" },
+{ "CCR6", 0x1000120C, 0, 0xffffffff, 'x', "Channel 6 Control Register" },
+{ "RSSR6", 0x10001210, 0, 0xffffffff, 'x', "Channel 6 Request Source Select Register" },
+{ "BLR6", 0x10001214, 0, 0xffffffff, 'x', "Channel 6 Burst Length Register" },
+{ "RTOR6", 0x10001218, 0, 0xffffffff, 'x', "Channel 6 Request Time-Out Register" },
+{ "BUCR6", 0x10001218, 0, 0xffffffff, 'x', "Channel 6 Bus Utilization Control Register" },
+{ "CCNR6", 0x1000121C, 0, 0xffffffff, 'x', "Channel 6 Channel Counter Register" },
+{ "SAR7", 0x10001240, 0, 0xffffffff, 'x', "Channel 7 Source Address Register" },
+{ "DAR7", 0x10001244, 0, 0xffffffff, 'x', "Channel 7 Destination Address Register" },
+{ "CNTR7", 0x10001248, 0, 0xffffffff, 'x', "Channel 7 Count Register" },
+{ "CCR7", 0x1000124C, 0, 0xffffffff, 'x', "Channel 7 Control Register" },
+{ "RSSR7", 0x10001250, 0, 0xffffffff, 'x', "Channel 7 Request Source Select Register" },
+{ "BLR7", 0x10001254, 0, 0xffffffff, 'x', "Channel 7 Burst Length Register" },
+{ "RTOR7", 0x10001258, 0, 0xffffffff, 'x', "Channel 7 Request Time-Out Register" },
+{ "BUCR7", 0x10001258, 0, 0xffffffff, 'x', "Channel 7 Bus Utilization Control Register" },
+{ "CCNR7", 0x1000125C, 0, 0xffffffff, 'x', "Channel 7 Channel Counter Register" },
+{ "SAR8", 0x10001280, 0, 0xffffffff, 'x', "Channel 8 Source Address Register" },
+{ "DAR8", 0x10001284, 0, 0xffffffff, 'x', "Channel 8 Destination Address Register" },
+{ "CNTR8", 0x10001288, 0, 0xffffffff, 'x', "Channel 8 Count Register" },
+{ "CCR8", 0x1000128C, 0, 0xffffffff, 'x', "Channel 8 Control Register" },
+{ "RSSR8", 0x10001290, 0, 0xffffffff, 'x', "Channel 8 Request Source Select Register" },
+{ "BLR8", 0x10001294, 0, 0xffffffff, 'x', "Channel 8 Burst Length Register" },
+{ "RTOR8", 0x10001298, 0, 0xffffffff, 'x', "Channel 8 Request Time-Out Register" },
+{ "BUCR8", 0x10001298, 0, 0xffffffff, 'x', "Channel 8 Bus Utilization Control Register" },
+{ "CCNR8", 0x1000129C, 0, 0xffffffff, 'x', "Channel 8 Channel Counter Register" },
+{ "SAR9", 0x100012C0, 0, 0xffffffff, 'x', "Channel 9 Source Address Register" },
+{ "DAR9", 0x100012C4, 0, 0xffffffff, 'x', "Channel 9 Destination Address Register" },
+{ "CNTR9", 0x100012C8, 0, 0xffffffff, 'x', "Channel 9 Count Register" },
+{ "CCR9", 0x100012CC, 0, 0xffffffff, 'x', "Channel 9 Control Register" },
+{ "RSSR9", 0x100012D0, 0, 0xffffffff, 'x', "Channel 9 Request Source Select Register" },
+{ "BLR9", 0x100012D4, 0, 0xffffffff, 'x', "Channel 9 Burst Length Register" },
+{ "RTOR9", 0x100012D8, 0, 0xffffffff, 'x', "Channel 9 Request Time-Out Register" },
+{ "BUCR9", 0x100012D8, 0, 0xffffffff, 'x', "Channel 9 Bus Utilization Control Register" },
+{ "CCNR9", 0x100012DC, 0, 0xffffffff, 'x', "Channel 9 Channel Counter Register" },
+{ "SAR10", 0x10001300, 0, 0xffffffff, 'x', "Channel 10 Source Address Register" },
+{ "DAR10", 0x10001304, 0, 0xffffffff, 'x', "Channel 10 Destination Address Register" },
+{ "CNTR10", 0x10001308, 0, 0xffffffff, 'x', "Channel 10 Count Register" },
+{ "CCR10", 0x1000130C, 0, 0xffffffff, 'x', "Channel 10 Control Register" },
+{ "RSSR10", 0x10001310, 0, 0xffffffff, 'x', "Channel 10 Request Source Select Register" },
+{ "BLR10", 0x10001314, 0, 0xffffffff, 'x', "Channel 10 Burst Length Register" },
+{ "RTOR10", 0x10001318, 0, 0xffffffff, 'x', "Channel 10 Request Time-Out Register" },
+{ "BUCR10", 0x10001318, 0, 0xffffffff, 'x', "Channel 10 Bus Utilization Control Register" },
+{ "CCNR10", 0x1000131C, 0, 0xffffffff, 'x', "Channel 10 Channel Counter Register" },
+{ "SAR11", 0x10001340, 0, 0xffffffff, 'x', "Channel 11 Source Address Register" },
+{ "DAR11", 0x10001344, 0, 0xffffffff, 'x', "Channel 11 Destination Address Register" },
+{ "CNTR11", 0x10001348, 0, 0xffffffff, 'x', "Channel 11 Count Register" },
+{ "CCR11", 0x1000134C, 0, 0xffffffff, 'x', "Channel 11 Control Register" },
+{ "RSSR11", 0x10001350, 0, 0xffffffff, 'x', "Channel 11 Request Source Select Register" },
+{ "BLR11", 0x10001354, 0, 0xffffffff, 'x', "Channel 11 Burst Length Register" },
+{ "RTOR11", 0x10001358, 0, 0xffffffff, 'x', "Channel 11 Request Time-Out Register" },
+{ "BUCR11", 0x10001358, 0, 0xffffffff, 'x', "Channel 11 Bus Utilization Control Register" },
+{ "CCNR11", 0x1000135C, 0, 0xffffffff, 'x', "Channel 11 Channel Counter Register" },
+{ "SAR12", 0x10001380, 0, 0xffffffff, 'x', "Channel 12 Source Address Register" },
+{ "DAR12", 0x10001384, 0, 0xffffffff, 'x', "Channel 12 Destination Address Register" },
+{ "CNTR12", 0x10001388, 0, 0xffffffff, 'x', "Channel 12 Count Register" },
+{ "CCR12", 0x1000138C, 0, 0xffffffff, 'x', "Channel 12 Control Register" },
+{ "RSSR12", 0x10001390, 0, 0xffffffff, 'x', "Channel 12 Request Source Select Register" },
+{ "BLR12", 0x10001394, 0, 0xffffffff, 'x', "Channel 12 Burst Length Register" },
+{ "RTOR12", 0x10001398, 0, 0xffffffff, 'x', "Channel 12 Request Time-Out Register" },
+{ "BUCR12", 0x10001398, 0, 0xffffffff, 'x', "Channel 12 Bus Utilization Control Register" },
+{ "CCNR12", 0x1000139C, 0, 0xffffffff, 'x', "Channel 14 Channel Counter Register" },
+{ "SAR13", 0x100013C0, 0, 0xffffffff, 'x', "Channel 13 Source Address Register" },
+{ "DAR13", 0x100013C4, 0, 0xffffffff, 'x', "Channel 13 Destination Address Register" },
+{ "CNTR13", 0x100013C8, 0, 0xffffffff, 'x', "Channel 13 Count Register" },
+{ "CCR13", 0x100013CC, 0, 0xffffffff, 'x', "Channel 13 Control Register" },
+{ "RSSR13", 0x100013D0, 0, 0xffffffff, 'x', "Channel 13 Request Source Select Register" },
+{ "BLR13", 0x100013D4, 0, 0xffffffff, 'x', "Channel 13 Burst Length Register" },
+{ "RTOR13", 0x100013D8, 0, 0xffffffff, 'x', "Channel 13 Request Time-Out Register" },
+{ "BUCR13", 0x100013D8, 0, 0xffffffff, 'x', "Channel 13 Bus Utilization Control Register" },
+{ "CCNR13", 0x100013DC, 0, 0xffffffff, 'x', "Channel 13 Channel Counter Register" },
+{ "SAR14", 0x10001400, 0, 0xffffffff, 'x', "Channel 14 Source Address Register" },
+{ "DAR14", 0x10001404, 0, 0xffffffff, 'x', "Channel 14 Destination Address Register" },
+{ "CNTR14", 0x10001408, 0, 0xffffffff, 'x', "Channel 14 Count Register" },
+{ "CCR14", 0x1000140C, 0, 0xffffffff, 'x', "Channel 14 Control Register" },
+{ "RSSR14", 0x10001410, 0, 0xffffffff, 'x', "Channel 14 Request Source Select Register" },
+{ "BLR14", 0x10001414, 0, 0xffffffff, 'x', "Channel 14 Burst Length Register" },
+{ "RTOR14", 0x10001418, 0, 0xffffffff, 'x', "Channel 14 Request Time-Out Register" },
+{ "BUCR14", 0x10001418, 0, 0xffffffff, 'x', "Channel 14 Bus Utilization Control Register" },
+{ "CCNR14", 0x1000141C, 0, 0xffffffff, 'x', "Channel 14 Channel Counter Register" },
+{ "SAR15", 0x10001440, 0, 0xffffffff, 'x', "Channel 15 Source Address Register" },
+{ "DAR15", 0x10001444, 0, 0xffffffff, 'x', "Channel 15 Destination Address Register" },
+{ "CNTR15", 0x10001448, 0, 0xffffffff, 'x', "Channel 15 Count Register" },
+{ "CCR15", 0x1000144C, 0, 0xffffffff, 'x', "Channel 15 Control Register" },
+{ "RSSR15", 0x10001450, 0, 0xffffffff, 'x', "Channel 15 Request Source Select Register" },
+{ "BLR15", 0x10001454, 0, 0xffffffff, 'x', "Channel 15 Burst Length Register" },
+{ "RTOR15", 0x10001458, 0, 0xffffffff, 'x', "Channel 15 Request Time-Out Register" },
+{ "BUCR15", 0x10001458, 0, 0xffffffff, 'x', "Channel 15 Bus Utilization Control Register" },
+{ "CCNR15", 0x1000145C, 0, 0xffffffff, 'x', "Channel 15 Channel Counter Register" },
+{ "TCR", 0x10001480, 0, 0xffffffff, 'x', "Test Control Register" },
+{ "TFIFOAR", 0x10001484, 0, 0xffffffff, 'x', "Test FIFO A Register" },
+{ "TDIPR", 0x1000148C, 0, 0xffffffff, 'x', "Test DMA In Progress Register" },
+{ "TFIFOBR", 0x10001490, 0, 0xffffffff, 'x', "Test FIFO B Register" },
+{ "TDRR_L", 0x10001498, 0, 0xffffffff, 'x', "Low 32 DMA Request Register" },
+{ "TDRR_H", 0x1000149C, 0, 0xffffffff, 'x', "High 32 DMA Request Register" },
+// WDOG
+{ "WCR", 0x10002000, 0, 0xffffffff, 'x', "Watchdog Control Register" },
+{ "WSR", 0x10002002, 0, 0xffffffff, 'x', "Watchdog Service Register" },
+{ "WRSR", 0x10002004, 0, 0xffffffff, 'x', "Watchdog Reset Status Register" },
+// GPT1
+{ "TCTL1", 0x10003000, 0, 0xffffffff, 'x', "GPT Control Register 1" },
+{ "TPRER1", 0x10003004, 0, 0xffffffff, 'x', "GPT Prescaler Register 1" },
+{ "TCMP1", 0x10003008, 0, 0xffffffff, 'x', "GPT Compare Register 1" },
+{ "TCR1", 0x1000300C, 0, 0xffffffff, 'x', "GPT Capture Register 1" },
+{ "TCN1", 0x10003010, 0, 0xffffffff, 'x', "GPT Counter Register 1" },
+{ "TSTAT1", 0x10003014, 0, 0xffffffff, 'x', "GPT Status Register 1" },
+// GPT2
+{ "TCTL2", 0x10004000, 0, 0xffffffff, 'x', "GPT Control Register 2" },
+{ "TPRER2", 0x10004004, 0, 0xffffffff, 'x', "GPT Prescaler Register 2" },
+{ "TCMP2", 0x10004008, 0, 0xffffffff, 'x', "GPT Compare Register 2" },
+{ "TCR2", 0x1000400C, 0, 0xffffffff, 'x', "GPT Capture Register 2" },
+{ "TCN2", 0x10004010, 0, 0xffffffff, 'x', "GPT Counter Register 2" },
+{ "TSTAT2", 0x10004014, 0, 0xffffffff, 'x', "GPT Status Register 2" },
+// GPT3
+{ "TCTL3", 0x10005000, 0, 0xffffffff, 'x', "GPT Control Register 3" },
+{ "TPRER3", 0x10005004, 0, 0xffffffff, 'x', "GPT Prescaler Register 3" },
+{ "TCMP3", 0x10005008, 0, 0xffffffff, 'x', "GPT Compare Register 3" },
+{ "TCR3", 0x1000500C, 0, 0xffffffff, 'x', "GPT Capture Register 3" },
+{ "TCN3", 0x10005010, 0, 0xffffffff, 'x', "GPT Counter Register 3" },
+{ "TSTAT3", 0x10005014, 0, 0xffffffff, 'x', "GPT Status Register 3" },
+// PWM
+{ "PWMCR", 0x10006000, 0, 0xffffffff, 'x', "PWM Control Register" },
+{ "PWMSR", 0x10006004, 0, 0xffffffff, 'x', "PWM Status Register" },
+{ "PWMIR", 0x10006008, 0, 0xffffffff, 'x', "PWM Interrupt Register" },
+{ "PWMSAR", 0x1000600C, 0, 0xffffffff, 'x', "PWM Sample Register" },
+{ "PWMPR", 0x10006010, 0, 0xffffffff, 'x', "PWM Period Register" },
+{ "PWMCNR", 0x10006014, 0, 0xffffffff, 'x', "PWM Counter Register" },
+// RTC
+{ "HOURMIN", 0x10007000, 0, 0xffffffff, 'x', "RTC Hours and Minutes Counter Register" },
+{ "SECONDS", 0x10007004, 0, 0xffffffff, 'x', "RTC Seconds Counter Register" },
+{ "ALRM_HM", 0x10007008, 0, 0xffffffff, 'x', "RTC Hours and Minutes Alarm Register" },
+{ "ALRM_SEC", 0x1000700C, 0, 0xffffffff, 'x', "RTC Seconds Alarm Register" },
+{ "RCCTL", 0x10007010, 0, 0xffffffff, 'x', "RTC Control Register" },
+{ "RTCISR", 0x10007014, 0, 0xffffffff, 'x', "RTC Interrupt Status Register" },
+{ "RTCIENR", 0x10007018, 0, 0xffffffff, 'x', "RTC Interrupt Enable Register" },
+{ "STPWCH", 0x1000701C, 0, 0xffffffff, 'x', "Stopwatch Minutes Register" },
+{ "DAYR", 0x10007020, 0, 0xffffffff, 'x', "RTC Days Counter Register" },
+{ "DAYALARM", 0x10007024, 0, 0xffffffff, 'x', "RTC Day Alarm Register" },
+// KPP
+{ "KPCR", 0x10008000, 0, 0xffffffff, 'x', "Keypad Control Register" },
+{ "KPSR", 0x10008002, 0, 0xffffffff, 'x', "Keypad Status Register" },
+{ "KDDR", 0x10008004, 0, 0xffffffff, 'x', "Keypad Data Direction Register" },
+{ "KPDR", 0x10008006, 0, 0xffffffff, 'x', "Keypad Data Register" },
+// O-Wire
+{ "CONTROL", 0x10009000, 0, 0xffffffff, 'x', "1-Wire Control Register" },
+{ "TIME_DIVIDER", 0x10009002, 0, 0xffffffff, 'x', "1-Wire Time Divider Register" },
+{ "RESET", 0x10009004, 0, 0xffffffff, 'x', "1-Wire Reset Register" },
+// UART1
+{ "UXRD_1", 0x1000A000, 0, 0xffffffff, 'x', "UART1 Receiver Register" },
+{ "UTXD_1", 0x1000A040, 0, 0xffffffff, 'x', "UART1 Transmitter Register" },
+{ "UCR1_1", 0x1000A080, 0, 0xffffffff, 'x', "UART1 Control Register" },
+{ "UCR2_1", 0x1000A084, 0, 0xffffffff, 'x', "UART1 Control Register 2" },
+{ "UCR3_1", 0x1000A088, 0, 0xffffffff, 'x', "UART1 Control Register 3" },
+{ "UCR4_1", 0x1000A08C, 0, 0xffffffff, 'x', "UART1 Control Register 4" },
+{ "UFCR_1", 0x1000A090, 0, 0xffffffff, 'x', "UART1 FIFO Control Register" },
+{ "USR1_1", 0x1000A094, 0, 0xffffffff, 'x', "UART1 Status Register 1" },
+{ "USR2_1", 0x1000A098, 0, 0xffffffff, 'x', "UART1 Status Register 2" },
+{ "UESC_1", 0x1000A09C, 0, 0xffffffff, 'x', "UART1 Escape Character Register" },
+{ "UTIM_1", 0x1000A0A0, 0, 0xffffffff, 'x', "UART1 Escape Timer Register" },
+{ "UBIR_1", 0x1000A0A4, 0, 0xffffffff, 'x', "UART1 BRM Incremental Register" },
+{ "UBMR_1", 0x1000A0A8, 0, 0xffffffff, 'x', "UART1 BRM Modulator Register" },
+{ "UBRC_1", 0x1000A0AC, 0, 0xffffffff, 'x', "UART1 Baud Rate Count Register" },
+{ "ONEMS_1", 0x1000A0B0, 0, 0xffffffff, 'x', "UART1 One Millisecond Register" },
+{ "UTS_1", 0x1000A0B4, 0, 0xffffffff, 'x', "UART1 Test Register 1" },
+// UART2
+{ "UXRD_2", 0x1000B000, 0, 0xffffffff, 'x', "UART2 Receiver Register" },
+{ "UTXD_2", 0x1000B040, 0, 0xffffffff, 'x', "UART2 Transmitter Register" },
+{ "UCR1_2", 0x1000B080, 0, 0xffffffff, 'x', "UART2 Control Register" },
+{ "UCR2_2", 0x1000B084, 0, 0xffffffff, 'x', "UART2 Control Register 2" },
+{ "UCR3_2", 0x1000B088, 0, 0xffffffff, 'x', "UART2 Control Register 3" },
+{ "UCR4_2", 0x1000B08C, 0, 0xffffffff, 'x', "UART2 Control Register 4" },
+{ "UFCR_2", 0x1000B090, 0, 0xffffffff, 'x', "UART2 FIFO Control Register" },
+{ "USR1_2", 0x1000B094, 0, 0xffffffff, 'x', "UART2 Status Register 1" },
+{ "USR2_2", 0x1000B098, 0, 0xffffffff, 'x', "UART2 Status Register 2" },
+{ "UESC_2", 0x1000B09C, 0, 0xffffffff, 'x', "UART2 Escape Character Register" },
+{ "UTIM_2", 0x1000B0A0, 0, 0xffffffff, 'x', "UART2 Escape Timer Register" },
+{ "UBIR_2", 0x1000B0A4, 0, 0xffffffff, 'x', "UART2 BRM Incremental Register" },
+{ "UBMR_2", 0x1000B0A8, 0, 0xffffffff, 'x', "UART2 BRM Modulator Register" },
+{ "UBRC_2", 0x1000B0AC, 0, 0xffffffff, 'x', "UART2 Baud Rate Count Register" },
+{ "ONEMS_2", 0x1000B0B0, 0, 0xffffffff, 'x', "UART2 One Millisecond Register" },
+{ "UTS_2", 0x1000B0B4, 0, 0xffffffff, 'x', "UART2 Test Register 1" },
+// UART3
+{ "UXRD_3", 0x1000C000, 0, 0xffffffff, 'x', "UART3 Receiver Register" },
+{ "UTXD_3", 0x1000C040, 0, 0xffffffff, 'x', "UART3 Transmitter Register" },
+{ "UCR1_3", 0x1000C080, 0, 0xffffffff, 'x', "UART3 Control Register" },
+{ "UCR2_3", 0x1000C084, 0, 0xffffffff, 'x', "UART3 Control Register 2" },
+{ "UCR3_3", 0x1000C088, 0, 0xffffffff, 'x', "UART3 Control Register 3" },
+{ "UCR4_3", 0x1000C08C, 0, 0xffffffff, 'x', "UART3 Control Register 4" },
+{ "UFCR_3", 0x1000C090, 0, 0xffffffff, 'x', "UART3 FIFO Control Register" },
+{ "USR1_3", 0x1000C094, 0, 0xffffffff, 'x', "UART3 Status Register 1" },
+{ "USR2_3", 0x1000C098, 0, 0xffffffff, 'x', "UART3 Status Register 2" },
+{ "UESC_3", 0x1000C09C, 0, 0xffffffff, 'x', "UART3 Escape Character Register" },
+{ "UTIM_3", 0x1000C0A0, 0, 0xffffffff, 'x', "UART3 Escape Timer Register" },
+{ "UBIR_3", 0x1000C0A4, 0, 0xffffffff, 'x', "UART3 BRM Incremental Register" },
+{ "UBMR_3", 0x1000C0A8, 0, 0xffffffff, 'x', "UART3 BRM Modulator Register" },
+{ "UBRC_3", 0x1000C0AC, 0, 0xffffffff, 'x', "UART3 Baud Rate Count Register" },
+{ "ONEMS_3", 0x1000C0B0, 0, 0xffffffff, 'x', "UART3 One Millisecond Register" },
+{ "UTS_3", 0x1000C0B4, 0, 0xffffffff, 'x', "UART3 Test Register 1" },
+// UART4
+{ "UXRD_4", 0x1000D000, 0, 0xffffffff, 'x', "UART4 Receiver Register" },
+{ "UTXD_4", 0x1000D040, 0, 0xffffffff, 'x', "UART4 Transmitter Register" },
+{ "UCR1_4", 0x1000D080, 0, 0xffffffff, 'x', "UART4 Control Register" },
+{ "UCR2_4", 0x1000D084, 0, 0xffffffff, 'x', "UART4 Control Register 2" },
+{ "UCR3_4", 0x1000D088, 0, 0xffffffff, 'x', "UART4 Control Register 3" },
+{ "UCR4_4", 0x1000D08C, 0, 0xffffffff, 'x', "UART4 Control Register 4" },
+{ "UFCR_4", 0x1000D090, 0, 0xffffffff, 'x', "UART4 FIFO Control Register" },
+{ "USR1_4", 0x1000D094, 0, 0xffffffff, 'x', "UART4 Status Register 1" },
+{ "USR2_4", 0x1000D098, 0, 0xffffffff, 'x', "UART4 Status Register 2" },
+{ "UESC_4", 0x1000D09C, 0, 0xffffffff, 'x', "UART4 Escape Character Register" },
+{ "UTIM_4", 0x1000D0A0, 0, 0xffffffff, 'x', "UART4 Escape Timer Register" },
+{ "UBIR_4", 0x1000D0A4, 0, 0xffffffff, 'x', "UART4 BRM Incremental Register" },
+{ "UBMR_4", 0x1000D0A8, 0, 0xffffffff, 'x', "UART4 BRM Modulator Register" },
+{ "UBRC_4", 0x1000D0AC, 0, 0xffffffff, 'x', "UART4 Baud Rate Count Register" },
+{ "ONEMS_4", 0x1000D0B0, 0, 0xffffffff, 'x', "UART4 One Millisecond Register" },
+{ "UTS_4", 0x1000D0B4, 0, 0xffffffff, 'x', "UART4 Test Register 1" },
+// CSPI1
+{ "RXDATA1", 0x1000E000, 0, 0xffffffff, 'x', "Receive Data Register 1" },
+{ "TXDATA1", 0x1000E004, 0, 0xffffffff, 'x', "Transmit Data Register 1" },
+{ "CONTROL_REG1", 0x1000E008, 0, 0xffffffff, 'x', "CSPI Control Register 1" },
+{ "INT_REG1", 0x1000E00C, 0, 0xffffffff, 'x', "Interrupt Control/Status Register 1" },
+{ "TEST_REG", 0x1000E010, 0, 0xffffffff, 'x', "CSPI Test Register 1" },
+{ "PERIOD1", 0x1000E014, 0, 0xffffffff, 'x', "CSPI Sample Period Control Register 1" },
+{ "CSPI_DMA1", 0x1000E018, 0, 0xffffffff, 'x', "CSPI DMA Register 1" },
+{ "CSPI_RESET1", 0x1000E01C, 0, 0xffffffff, 'x', "CSPI 1 Soft Reset Register" },
+// CSPI2
+{ "RXDATA2", 0x1000F000, 0, 0xffffffff, 'x', "Receive Data Register 2" },
+{ "TXDATA2", 0x1000F004, 0, 0xffffffff, 'x', "Transmit Data Register 2" },
+{ "CONTROL_REG2", 0x1000F008, 0, 0xffffffff, 'x', "CSPI Control Register 2" },
+{ "INT_REG2", 0x1000F00C, 0, 0xffffffff, 'x', "Interrupt Control/Status Register 2" },
+{ "TEST_REG", 0x1000F010, 0, 0xffffffff, 'x', "2 CSPI Test Register 2" },
+{ "PERIOD2", 0x1000F014, 0, 0xffffffff, 'x', "CSPI Sample Period Control Register 2" },
+{ "CSPI_DMA2", 0x1000F018, 0, 0xffffffff, 'x', "CSPI DMA Register 2" },
+{ "CSPI_RESET2", 0x1000F01C, 0, 0xffffffff, 'x', "CSPI 2 Soft Reset Register" },
+// SSI1
+{ "STX0", 0x10010000, 0, 0xffffffff, 'x', "SSI Transmit Data Register 0" },
+{ "STX1", 0x10010004, 0, 0xffffffff, 'x', "SSI Transmit Data Register 1" },
+{ "SRX0", 0x10010008, 0, 0xffffffff, 'x', "SSI Receive Data Register 0" },
+{ "SRX1", 0x1001000C, 0, 0xffffffff, 'x', "SSI Receive Data Register 1" },
+{ "SCR", 0x10010010, 0, 0xffffffff, 'x', "SSI Control Register" },
+{ "SISR", 0x10010014, 0, 0xffffffff, 'x', "SSI Interrupt Status Register" },
+{ "SIER", 0x10010018, 0, 0xffffffff, 'x', "SSI Interrupt Enable Register" },
+{ "STCR", 0x1001001C, 0, 0xffffffff, 'x', "SSI Transmit Configuration Register" },
+{ "SRCR", 0x10010020, 0, 0xffffffff, 'x', "SSI Receive Configuration Register" },
+{ "STCCR", 0x10010024, 0, 0xffffffff, 'x', "SSI Transmit Clock Control Register" },
+{ "SRCCR", 0x10010028, 0, 0xffffffff, 'x', "SSI Receive Clock Control Register" },
+{ "SFCSR", 0x1001002C, 0, 0xffffffff, 'x', "SSI FIFO Control/Status Register" },
+{ "STR", 0x10010030, 0, 0xffffffff, 'x', "SSI Test Register" },
+{ "SOR", 0x10010034, 0, 0xffffffff, 'x', "SSI Option Register" },
+{ "SACNT", 0x10010038, 0, 0xffffffff, 'x', "SSI AC97 Control Register" },
+{ "SACADD", 0x1001003C, 0, 0xffffffff, 'x', "SSI AC97 Command Address Register" },
+{ "SACDAT", 0x10010040, 0, 0xffffffff, 'x', "SSI AC97 Command Data Register" },
+{ "SATAG", 0x10010044, 0, 0xffffffff, 'x', "SSI AC97 Tag Register" },
+{ "STMSK", 0x10010048, 0, 0xffffffff, 'x', "SSI Transmit Time Slot Mask Register" },
+{ "SRMSK", 0x1001004C, 0, 0xffffffff, 'x', "SSI Receive Time Slot Mask Register" },
+{ "SACCST", 0x10010050, 0, 0xffffffff, 'x', "SSI AC97 Channel Status Register" },
+{ "SACCEN", 0x10010054, 0, 0xffffffff, 'x', "SSI AC97 Channel Enable Register" },
+{ "SACCDIS", 0x10010058, 0, 0xffffffff, 'x', "SSI AC97 Channel Disable Register" },
+// SSI2
+{ "STX0", 0x10011000, 0, 0xffffffff, 'x', "SSI Transmit Data Register 0" },
+{ "STX1", 0x10011004, 0, 0xffffffff, 'x', "SSI Transmit Data Register 1" },
+{ "SRX0", 0x10011008, 0, 0xffffffff, 'x', "SSI Receive Data Register 0" },
+{ "SRX1", 0x1001100C, 0, 0xffffffff, 'x', "SSI Receive Data Register 1" },
+{ "SCR", 0x10011010, 0, 0xffffffff, 'x', "SSI Control Register" },
+{ "SISR", 0x10011014, 0, 0xffffffff, 'x', "SSI Interrupt Status Register" },
+{ "SIER", 0x10011018, 0, 0xffffffff, 'x', "SSI Interrupt Enable Register" },
+{ "STCR", 0x1001101C, 0, 0xffffffff, 'x', "SSI Transmit Configuration Register" },
+{ "SRCR", 0x10011020, 0, 0xffffffff, 'x', "SSI Receive Configuration Register" },
+{ "STCCR", 0x10011024, 0, 0xffffffff, 'x', "SSI Transmit Clock Control Register" },
+{ "SRCCR", 0x10011028, 0, 0xffffffff, 'x', "SSI Receive Clock Control Register" },
+{ "SFCSR", 0x1001102C, 0, 0xffffffff, 'x', "SSI FIFO Control/Status Register" },
+{ "STR", 0x10011030, 0, 0xffffffff, 'x', "SSI Test Register" },
+{ "SOR", 0x10011034, 0, 0xffffffff, 'x', "SSI Option Register" },
+{ "SACNT", 0x10011038, 0, 0xffffffff, 'x', "SSI AC97 Control Register" },
+{ "SACADD", 0x1001103C, 0, 0xffffffff, 'x', "SSI AC97 Command Address Register" },
+{ "SACDAT", 0x10011040, 0, 0xffffffff, 'x', "SSI AC97 Command Data Register" },
+{ "SATAG", 0x10011044, 0, 0xffffffff, 'x', "SSI AC97 Tag Register" },
+{ "STMSK", 0x10011048, 0, 0xffffffff, 'x', "SSI Transmit Time Slot Mask Register" },
+{ "SRMSK", 0x1001104C, 0, 0xffffffff, 'x', "SSI Receive Time Slot Mask Register" },
+{ "SACCST", 0x10011050, 0, 0xffffffff, 'x', "SSI AC97 Channel Status Register" },
+{ "SACCEN", 0x10011054, 0, 0xffffffff, 'x', "SSI AC97 Channel Enable Register" },
+{ "SACCDIS", 0x10011058, 0, 0xffffffff, 'x', "SSI AC97 Channel Disable Register" },
+// I2C1
+{ "IADR", 0x10012000, 0, 0xffffffff, 'x', "I2C Address Register" },
+{ "IFDR", 0x10012004, 0, 0xffffffff, 'x', "I2C Frequency Divider Register" },
+{ "I2CR", 0x10012008, 0, 0xffffffff, 'x', "I2C Control Register" },
+{ "I2SR", 0x1001200C, 0, 0xffffffff, 'x', "I2C Status Register" },
+{ "I2DR", 0x10012010, 0, 0xffffffff, 'x', "I2C Data I/O Register" },
+// SDHC1
+{ "STR_STP_CLK", 0x10013000, 0, 0xffffffff, 'x', "MMC/SD1 Clock Control Register" },
+{ "STATUS", 0x10013004, 0, 0xffffffff, 'x', "(Read Only) MMC/SD1 Status Register" },
+{ "CLK_RATE", 0x10013008, 0, 0xffffffff, 'x', "MMC/SD1 Clock Rate Register" },
+{ "CMD_DAT_CONT", 0x1001300C, 0, 0xffffffff, 'x', "MMC/SD1 Command and Data Control Register" },
+{ "RESPONSE_TO", 0x10013010, 0, 0xffffffff, 'x', "MMC/SD1 Response Time Out Register" },
+{ "READ_TO", 0x10013014, 0, 0xffffffff, 'x', "MMC/SD1 Read Time Out Register" },
+{ "BLK_LEN", 0x10013018, 0, 0xffffffff, 'x', "MMC/SD1 Block Length Register" },
+{ "NOB", 0x1001301C, 0, 0xffffffff, 'x', "MMC/SD1 Number of Block Register" },
+{ "REV_NO", 0x10013020, 0, 0xffffffff, 'x', "MMC/SD1 Revision Number Register" },
+{ "INT_CNTL", 0x10013024, 0, 0xffffffff, 'x', "MMC/SD1 Interrupt Control Register" },
+{ "CMD", 0x10013028, 0, 0xffffffff, 'x', "MMC/SD1 Command Number Register" },
+{ "ARGH", 0x1001302C, 0, 0xffffffff, 'x', "MMC/SD1 Higher Argument Register" },
+{ "ARGL", 0x10013030, 0, 0xffffffff, 'x', "MMC/SD1 Lower Argument Register" },
+{ "RES_FIFO", 0x10013034, 0, 0xffffffff, 'x', "(Read Only) MMC/SD1 Response FIFO Register" },
+{ "BUFFER_ACCESS", 0x10013038, 0, 0xffffffff, 'x', "MMC/SD1 Buffer Access Register" },
+// SDHC2
+{ "STR_STP_CLK", 0x10014000, 0, 0xffffffff, 'x', "MMC/SD2 Clock Control Register" },
+{ "STATUS", 0x10014004, 0, 0xffffffff, 'x', "(Read Only) MMC/SD2 Status Register" },
+{ "CLK_RATE", 0x10014008, 0, 0xffffffff, 'x', "MMC/SD2 Clock Rate Register" },
+{ "CMD_DAT_CONT", 0x1001400C, 0, 0xffffffff, 'x', "MMC/SD2 Command and Data Control Register" },
+{ "RESPONSE_TO", 0x10014010, 0, 0xffffffff, 'x', "MMC/SD2 Response Time Out Register" },
+{ "READ_TO", 0x10014014, 0, 0xffffffff, 'x', "MMC/SD2 Read Time Out Register" },
+{ "BLK_LEN", 0x10014018, 0, 0xffffffff, 'x', "MMC/SD2 Block Length Register" },
+{ "NOB", 0x1001401C, 0, 0xffffffff, 'x', "MMC/SD2 Number of Block Register" },
+{ "REV_NO", 0x10014020, 0, 0xffffffff, 'x', "MMC/SD2 Revision Number Register" },
+{ "INT_CNTL", 0x10014024, 0, 0xffffffff, 'x', "MMC/SD2 Interrupt Control Register" },
+{ "CMD", 0x10014028, 0, 0xffffffff, 'x', "MMC/SD2 Command Number Register" },
+{ "ARGH", 0x1001402C, 0, 0xffffffff, 'x', "MMC/SD2 Higher Argument Register" },
+{ "ARGL", 0x10014030, 0, 0xffffffff, 'x', "MMC/SD2 Lower Argument Register" },
+{ "RES_FIFO", 0x10014034, 0, 0xffffffff, 'x', "(Read Only) MMC/SD2 Response FIFO Register" },
+{ "BUFFER_ACCESS", 0x10014038, 0, 0xffffffff, 'x', "MMC/SD2 Buffer Access Register" },
+// GPIO
+{ "PTA_DDIR", 0x10015000, 0, 0xffffffff, 'x', "Data Direction Register, Port A" },
+{ "PTA_OCR1", 0x10015004, 0, 0xffffffff, 'x', "Output Configuration Register 1 (OCR1), Port" },
+{ "PTA_OCR2", 0x10015008, 0, 0xffffffff, 'x', "Output Configuration Register 2 (OCR2), Port" },
+{ "PTA_ICONFA1", 0x1001500C, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA1), Port" },
+{ "PTA_ICONFA2", 0x10015010, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA2), Port" },
+{ "PTA_ICONFB1", 0x10015014, 0, 0xffffffff, 'x', "Input Configuration Register B1 (ICONFB1), Port" },
+{ "PTA_ICONFB2", 0x10015018, 0, 0xffffffff, 'x', "Input Configuration Register B2 (ICONFB2), Port" },
+{ "PTA_DR", 0x1001501c, 0, 0xffffffff, 'x', "Data Register, Port A" },
+{ "PTA_GIUS", 0x10015020, 0, 0xffffffff, 'x', "GPIO In Use Register, Port A" },
+{ "PTA_SSR", 0x10015024, 0, 0xffffffff, 'x', "Sample Status Register, Port A" },
+{ "PTA_ICR1", 0x10015028, 0, 0xffffffff, 'x', "Interrupt Configuration Register 1, Port A" },
+{ "PTA_ICR2", 0x1001502C, 0, 0xffffffff, 'x', "Interrupt Configuration Register 2, Port A" },
+{ "PTA_IMR", 0x10015030, 0, 0xffffffff, 'x', "Interrupt Mask Register, Port A" },
+{ "PTA_ISR", 0x10015034, 0, 0xffffffff, 'x', "Interrupt Status Register, Port A" },
+{ "PTA_GPR", 0x10015038, 0, 0xffffffff, 'x', "General Purpose Register, Port A" },
+{ "PTA_SWR", 0x1001503c, 0, 0xffffffff, 'x', "Software Reset Register, Port A" },
+{ "PTA_PUEN", 0x10015040, 0, 0xffffffff, 'x', "Pull_up Enable Register, Port A" },
+{ "PTB_DDIR", 0x10015100, 0, 0xffffffff, 'x', "Data Direction Register, Port B" },
+{ "PTB_OCR1", 0x10015104, 0, 0xffffffff, 'x', "Output Configuration Register 1 (OCR1), Port" },
+{ "PTB_OCR2", 0x10015108, 0, 0xffffffff, 'x', "Output Configuration Register 2 (OCR2), Port" },
+{ "PTB_ICONFA1", 0x1001510c, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA1), Port" },
+{ "PTB_ICONFA2", 0x10015110, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA2), Port" },
+{ "PTB_ICONFB1", 0x10015114, 0, 0xffffffff, 'x', "Input Configuration Register B1 (ICONFB1), Port" },
+{ "PTB_ICONFB2", 0x10015118, 0, 0xffffffff, 'x', "Input Configuration Register B2 (ICONFB2), Port" },
+{ "PTB_DR", 0x1001511c, 0, 0xffffffff, 'x', "Data Register, Port B" },
+{ "PTB_GIUS", 0x10015120, 0, 0xffffffff, 'x', "GPIO In Use Register, Port B" },
+{ "PTB_SSR", 0x10015124, 0, 0xffffffff, 'x', "Sample Status Register, Port B" },
+{ "PTB_ICR1", 0x10015128, 0, 0xffffffff, 'x', "Interrupt Configuration Register 1, Port B" },
+{ "PTB_ICR2", 0x1001512C, 0, 0xffffffff, 'x', "Interrupt Configuration Register 2, Port B" },
+{ "PTB_IMR", 0x10015130, 0, 0xffffffff, 'x', "Interrupt Mask Register, Port B" },
+{ "PTB_ISR", 0x10015134, 0, 0xffffffff, 'x', "Interrupt Status Register, Port B" },
+{ "PTB_GPR", 0x10015138, 0, 0xffffffff, 'x', "General Purpose Register, Port B" },
+{ "PTB_SWR", 0x1001513c, 0, 0xffffffff, 'x', "Software Reset Register, Port B" },
+{ "PTB_PUEN", 0x10015140, 0, 0xffffffff, 'x', "Pull_up Enable Register, Port B" },
+{ "PTC_DDIR", 0x10015200, 0, 0xffffffff, 'x', "Data Direction Register, Port C" },
+{ "PTC_OCR1", 0x10015204, 0, 0xffffffff, 'x', "Output Configuration Register 1 (OCR1), Port" },
+{ "PTC_OCR2", 0x10015208, 0, 0xffffffff, 'x', "Output Configuration Register 2 (OCR2), Port" },
+{ "PTC_ICONFA1", 0x1001520c, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA1), Port" },
+{ "PTC_ICONFA2", 0x10015210, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA2), Port" },
+{ "PTC_ICONFB1", 0x10015214, 0, 0xffffffff, 'x', "Input Configuration Register B1 (ICONFB1), Port" },
+{ "PTC_ICONFB2", 0x10015218, 0, 0xffffffff, 'x', "Input Configuration Register B2 (ICONFB2), Port" },
+{ "PTC_DR", 0x1001521C, 0, 0xffffffff, 'x', "Data Register, Port C" },
+{ "PTC_GIUS", 0x10015220, 0, 0xffffffff, 'x', "GPIO In Use Register, Port C" },
+{ "PTC_SSR", 0x10015224, 0, 0xffffffff, 'x', "Sample Status Register, Port C" },
+{ "PTC_ICR1", 0x10015228, 0, 0xffffffff, 'x', "Interrupt Configuration Register 1, Port C" },
+{ "PTC_ICR2", 0x1001522C, 0, 0xffffffff, 'x', "Interrupt Configuration Register 2, Port C" },
+{ "PTC_IMR", 0x10015230, 0, 0xffffffff, 'x', "Interrupt Mask Register, Port C" },
+{ "PTC_ISR", 0x10015234, 0, 0xffffffff, 'x', "Interrupt Status Register, Port C" },
+{ "PTC_GPR", 0x10015238, 0, 0xffffffff, 'x', "General Purpose Register, Port C" },
+{ "PTC_SWR", 0x1001523c, 0, 0xffffffff, 'x', "Software Reset Register, Port C" },
+{ "PTC_PUEN", 0x10015240, 0, 0xffffffff, 'x', "Pull_up Enable Register, Port C" },
+{ "PTD_DDIR", 0x10015300, 0, 0xffffffff, 'x', "Data Direction Register, Port D" },
+{ "PTD_OCR1", 0x10015304, 0, 0xffffffff, 'x', "Output Configuration Register 1 (OCR1), Port" },
+{ "PTD_OCR2", 0x10015308, 0, 0xffffffff, 'x', "Output Configuration Register 2 (OCR2), Port" },
+{ "PTD_ICONFA1", 0x1001530c, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA1), Port" },
+{ "PTD_ICONFA2", 0x10015310, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA2), Port" },
+{ "PTD_ICONFB1", 0x10015314, 0, 0xffffffff, 'x', "Input Configuration Register B1 (ICONFB1), Port" },
+{ "PTD_ICONFB2", 0x10015318, 0, 0xffffffff, 'x', "Input Configuration Register B2 (ICONFB2), Port" },
+{ "PTD_DR", 0x1001531c, 0, 0xffffffff, 'x', "Data Register, Port D" },
+{ "PTD_GIUS", 0x10015320, 0, 0xffffffff, 'x', "GPIO In Use Register, Port D" },
+{ "PTD_SSR", 0x10015324, 0, 0xffffffff, 'x', "Sample Status Register, Port D" },
+{ "PTD_ICR1", 0x10015328, 0, 0xffffffff, 'x', "Interrupt Configuration Register 1, Port D" },
+{ "PTD_ICR2", 0x1001532C, 0, 0xffffffff, 'x', "Interrupt Configuration Register 2, Port D" },
+{ "PTD_IMR", 0x10015330, 0, 0xffffffff, 'x', "Interrupt Mask Register, Port D" },
+{ "PTD_ISR", 0x10015334, 0, 0xffffffff, 'x', "Interrupt Status Register, Port D" },
+{ "PTD_GPR", 0x10015338, 0, 0xffffffff, 'x', "General Purpose Register, Port D" },
+{ "PTD_SWR", 0x1001533c, 0, 0xffffffff, 'x', "Software Reset Register, Port D" },
+{ "PTD_PUEN", 0x10015340, 0, 0xffffffff, 'x', "Pull_up Enable Register, Port D" },
+{ "PTE_DDIR", 0x10015400, 0, 0xffffffff, 'x', "Data Direction Register, Port E" },
+{ "PTE_OCR1", 0x10015404, 0, 0xffffffff, 'x', "Output Configuration Register 1 (OCR1), Port" },
+{ "PTE_OCR2", 0x10015408, 0, 0xffffffff, 'x', "Output Configuration Register 2 (OCR2), Port" },
+{ "PTE_ICONFA1", 0x1001540c, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA1), Port" },
+{ "PTE_ICONFA2", 0x10015410, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA2), Port" },
+{ "PTE_ICONFB1", 0x10015414, 0, 0xffffffff, 'x', "Input Configuration Register B1 (ICONFB1), Port" },
+{ "PTE_ICONFB2", 0x10015418, 0, 0xffffffff, 'x', "Input Configuration Register B2 (ICONFB2), Port" },
+{ "PTE_DR", 0x1001541c, 0, 0xffffffff, 'x', "Data Register, Port E" },
+{ "PTE_GIUS", 0x10015420, 0, 0xffffffff, 'x', "GPIO In Use Register, Port E" },
+{ "PTE_SSR", 0x10015424, 0, 0xffffffff, 'x', "Sample Status Register, Port E" },
+{ "PTE_ICR1", 0x10015428, 0, 0xffffffff, 'x', "Interrupt Configuration Register 1, Port E" },
+{ "PTE_ICR2", 0x1001542C, 0, 0xffffffff, 'x', "Interrupt Configuration Register 2, Port E" },
+{ "PTE_IMR", 0x10015430, 0, 0xffffffff, 'x', "Interrupt Mask Register, Port E" },
+{ "PTE_ISR", 0x10015434, 0, 0xffffffff, 'x', "Interrupt Status Register, Port E" },
+{ "PTE_GPR", 0x10015438, 0, 0xffffffff, 'x', "General Purpose Register, Port E" },
+{ "PTE_SWR", 0x1001543c, 0, 0xffffffff, 'x', "Software Reset Register, Port E" },
+{ "PTE_PUEN", 0x10015440, 0, 0xffffffff, 'x', "Pull_up Enable Register, Port E" },
+{ "PTF_DDIR", 0x10015500, 0, 0xffffffff, 'x', "Data Direction Register, Port F" },
+{ "PTF_OCR1", 0x10015504, 0, 0xffffffff, 'x', "Output Configuration Register 1 (OCR1), Port" },
+{ "PTF_OCR2", 0x10015508, 0, 0xffffffff, 'x', "Output Configuration Register 2 (OCR2), Port" },
+{ "PTF_ICONFA1", 0x1001550C, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA1), Port" },
+{ "PTF_ICONFA2", 0x10015510, 0, 0xffffffff, 'x', "Input Configuration Register A1 (ICONFA2), Port" },
+{ "PTF_ICONFB1", 0x10015514, 0, 0xffffffff, 'x', "Input Configuration Register B1 (ICONFB1), Port" },
+{ "PTF_ICONFB2", 0x10015518, 0, 0xffffffff, 'x', "Input Configuration Register B2 (ICONFB2), Port" },
+{ "PTF_DR", 0x1001551c, 0, 0xffffffff, 'x', "Data Register, Port F" },
+{ "PTF_GIUS", 0x10015520, 0, 0xffffffff, 'x', "GPIO In Use Register, Port F" },
+{ "PTF_SSR", 0x10015524, 0, 0xffffffff, 'x', "Sample Status Register, Port F" },
+{ "PTF_ICR1", 0x10015528, 0, 0xffffffff, 'x', "Interrupt Configuration Register 1, Port F" },
+{ "PTF_ICR2", 0x1001552C, 0, 0xffffffff, 'x', "Interrupt Configuration Register 2, Port F" },
+{ "PTF_IMR", 0x10015530, 0, 0xffffffff, 'x', "Interrupt Mask Register, Port F" },
+{ "PTF_ISR", 0x10015534, 0, 0xffffffff, 'x', "Interrupt Status Register, Port F" },
+{ "PTF_GPR", 0x10015538, 0, 0xffffffff, 'x', "General Purpose Register, Port F" },
+{ "PTF_SWR", 0x1001553c, 0, 0xffffffff, 'x', "Software Reset Register, Port F" },
+{ "PTF_PUEN", 0x10015540, 0, 0xffffffff, 'x', "Pull_up Enable Register, Port F" },
+{ "PMASK", 0x10015600, 0, 0xffffffff, 'x', "GPIO Port Interrupt Mask" },
+// AUDMUX
+{ "HPCR1", 0x10016000, 0, 0xffffffff, 'x', "Host Port Configuration Register 1" },
+{ "HPCR2", 0x10016004, 0, 0xffffffff, 'x', "Host Port Configuration Register 2" },
+{ "HPCR3", 0x10016008, 0, 0xffffffff, 'x', "Host Port Configuration Register 3" },
+{ "PPCR1", 0x10016010, 0, 0xffffffff, 'x', "Peripheral Port Configuration Register 1" },
+{ "PPCR2", 0x10016014, 0, 0xffffffff, 'x', "Peripheral Port Configuration Register 2" },
+{ "PPCR3", 0x1001601C, 0, 0xffffffff, 'x', "Peripheral Port Configuration Register 3" },
+// CSPI3
+{ "RXDATA3", 0x10017000, 0, 0xffffffff, 'x', "Receive Data Register 3" },
+{ "TXDATA3", 0x10017004, 0, 0xffffffff, 'x', "Transmit Data Register 3" },
+{ "CONTROL_REG3", 0x10017008, 0, 0xffffffff, 'x', "CSPI Control Register 3" },
+{ "INT_REG3", 0x1001700C, 0, 0xffffffff, 'x', "Interrupt Control/Status Register 3" },
+{ "TEST_REG3", 0x10017010, 0, 0xffffffff, 'x', "CSPI Test Register 3" },
+{ "PERIOD3", 0x10017014, 0, 0xffffffff, 'x', "CSPI Sample Period Control Register 3" },
+{ "CSPI_DMA3", 0x10017018, 0, 0xffffffff, 'x', "CSPI DMA Register 3" },
+{ "CSPI_RESET3", 0x1001701C, 0, 0xffffffff, 'x', "CSPI Soft Reset Register 3" },
+// MSHC
+{ "COMMAND_REG", 0x10018000, 0, 0xffffffff, 'x', "MSHC Command Register" },
+{ "DATA_REG", 0x10018008, 0, 0xffffffff, 'x', "MSHC Data Register" },
+{ "STATUS_REG", 0x10018010, 0, 0xffffffff, 'x', "MSHC Status Register" },
+{ "SYSTEM_REG", 0x10018018, 0, 0xffffffff, 'x', "MSHC System Register" },
+// GPT4
+{ "TCTL4", 0x10019000, 0, 0xffffffff, 'x', "GPT Control Register 4" },
+{ "TPRER4", 0x10019004, 0, 0xffffffff, 'x', "GPT Prescaler Register 4" },
+{ "TCMP4", 0x10019008, 0, 0xffffffff, 'x', "GPT Compare Register 4" },
+{ "TCR4", 0x1001900C, 0, 0xffffffff, 'x', "GPT Capture Register 4" },
+{ "TCN4", 0x10019010, 0, 0xffffffff, 'x', "GPT Counter Register 4" },
+{ "TSTAT4", 0x10019014, 0, 0xffffffff, 'x', "GPT Status Register 4" },
+// GPT5
+{ "TCTL5", 0x1001A000, 0, 0xffffffff, 'x', "GPT Control Register 5" },
+{ "TPRER5", 0x1001A004, 0, 0xffffffff, 'x', "GPT Prescaler Register 5" },
+{ "TCMP5", 0x1001A008, 0, 0xffffffff, 'x', "GPT Compare Register 5" },
+{ "TCR5", 0x1001A00C, 0, 0xffffffff, 'x', "GPT Capture Register 5" },
+{ "TCN5", 0x1001A010, 0, 0xffffffff, 'x', "GPT Counter Register 5" },
+{ "TSTAT5", 0x1001A014, 0, 0xffffffff, 'x', "GPT Status Register 5" },
+// UART5
+{ "UXRD_5", 0x1001B000, 0, 0xffffffff, 'x', "UART5 Receiver Register" },
+{ "UTXD_5", 0x1001B040, 0, 0xffffffff, 'x', "UART5 Transmitter Register" },
+{ "UCR1_5", 0x1001B080, 0, 0xffffffff, 'x', "UART5 Control Register" },
+{ "UCR2_5", 0x1001B084, 0, 0xffffffff, 'x', "UART5 Control Register 2" },
+{ "UCR3_5", 0x1001B088, 0, 0xffffffff, 'x', "UART5 Control Register 3" },
+{ "UCR4_5", 0x1001B08C, 0, 0xffffffff, 'x', "UART5 Control Register 4" },
+{ "UFCR_5", 0x1001B090, 0, 0xffffffff, 'x', "UART5 FIFO Control Register" },
+{ "USR1_5", 0x1001B094, 0, 0xffffffff, 'x', "UART5 Status Register 1" },
+{ "USR2_5", 0x1001B098, 0, 0xffffffff, 'x', "UART5 Status Register 2" },
+{ "UESC_5", 0x1001B09C, 0, 0xffffffff, 'x', "UART5 Escape Character Register" },
+{ "UTIM_5", 0x1001B0A0, 0, 0xffffffff, 'x', "UART5 Escape Timer Register" },
+{ "UBIR_5", 0x1001B0A4, 0, 0xffffffff, 'x', "UART5 BRM Incremental Register" },
+{ "UBMR_5", 0x1001B0A8, 0, 0xffffffff, 'x', "UART5 BRM Modulator Register" },
+{ "UBRC_5", 0x1001B0AC, 0, 0xffffffff, 'x', "UART5 Baud Rate Count Register" },
+{ "ONEMS_5", 0x1001B0B0, 0, 0xffffffff, 'x', "UART5 One Millisecond Register" },
+{ "UTS_5", 0x1001B0B4, 0, 0xffffffff, 'x', "UART5 Test Register 1" },
+// UART6
+{ "UXRD_6", 0x1001C000, 0, 0xffffffff, 'x', "UART6 Receiver Register" },
+{ "UTXD_6", 0x1001C040, 0, 0xffffffff, 'x', "UART6 Transmitter Register" },
+{ "UCR1_6", 0x1001C080, 0, 0xffffffff, 'x', "UART6 Control Register" },
+{ "UCR2_6", 0x1001C084, 0, 0xffffffff, 'x', "UART6 Control Register 2" },
+{ "UCR3_6", 0x1001C088, 0, 0xffffffff, 'x', "UART6 Control Register 3" },
+{ "UCR4_6", 0x1001C08C, 0, 0xffffffff, 'x', "UART6 Control Register 4" },
+{ "UFCR_6", 0x1001C090, 0, 0xffffffff, 'x', "UART6 FIFO Control Register" },
+{ "USR1_6", 0x1001C094, 0, 0xffffffff, 'x', "UART6 Status Register 1" },
+{ "USR2_6", 0x1001C098, 0, 0xffffffff, 'x', "UART6 Status Register 2" },
+{ "UESC_6", 0x1001C09C, 0, 0xffffffff, 'x', "UART6 Escape Character Register" },
+{ "UTIM_6", 0x1001C0A0, 0, 0xffffffff, 'x', "UART6 Escape Timer Register" },
+{ "UBIR_6", 0x1001C0A4, 0, 0xffffffff, 'x', "UART6 BRM Incremental Register" },
+{ "UBMR_6", 0x1001C0A8, 0, 0xffffffff, 'x', "UART6 BRM Modulator Register" },
+{ "UBRC_6", 0x1001C0AC, 0, 0xffffffff, 'x', "UART6 Baud Rate Count Register" },
+{ "ONEMS_6", 0x1001C0B0, 0, 0xffffffff, 'x', "UART6 One Millisecond Register" },
+{ "UTS_6", 0x1001C0B4, 0, 0xffffffff, 'x', "UART6 Test Register 1" },
+// I2C2
+{ "IADR", 0x1001D000, 0, 0xffffffff, 'x', "I2C Address Register" },
+{ "IFDR", 0x1001D004, 0, 0xffffffff, 'x', "I2C Frequency Divider Register" },
+{ "I2CR", 0x1001D008, 0, 0xffffffff, 'x', "I2C Control Register" },
+{ "I2SR", 0x1001D00C, 0, 0xffffffff, 'x', "I2C Status Register" },
+{ "I2DR", 0x1001D010, 0, 0xffffffff, 'x', "I2C Data I/O Register" },
+// SDHC3
+{ "STR_STP_CLK", 0x1001E000, 0, 0xffffffff, 'x', "MMC/SD2 Clock Control Register" },
+{ "STATUS", 0x1001E004, 0, 0xffffffff, 'x', "(Read Only) MMC/SD2 Status Register" },
+{ "CLK_RATE", 0x1001E008, 0, 0xffffffff, 'x', "MMC/SD2 Clock Rate Register" },
+{ "CMD_DAT_CONT", 0x1001E00C, 0, 0xffffffff, 'x', "MMC/SD2 Command and Data Control Register" },
+{ "RESPONSE_TO", 0x1001E010, 0, 0xffffffff, 'x', "MMC/SD2 Response Time Out Register" },
+{ "READ_TO", 0x1001E014, 0, 0xffffffff, 'x', "MMC/SD2 Read Time Out Register" },
+{ "BLK_LEN", 0x1001E018, 0, 0xffffffff, 'x', "MMC/SD2 Block Length Register" },
+{ "NOB", 0x1001E01C, 0, 0xffffffff, 'x', "MMC/SD2 Number of Block Register" },
+{ "REV_NO", 0x1001E020, 0, 0xffffffff, 'x', "MMC/SD2 Revision Number Register" },
+{ "INT_CNTL", 0x1001E024, 0, 0xffffffff, 'x', "MMC/SD2 Interrupt Control Register" },
+{ "CMD", 0x1001E028, 0, 0xffffffff, 'x', "MMC/SD2 Command Number Register" },
+{ "ARGH", 0x1001E02C, 0, 0xffffffff, 'x', "MMC/SD2 Higher Argument Register" },
+{ "ARGL", 0x1001E030, 0, 0xffffffff, 'x', "MMC/SD2 Lower Argument Register" },
+{ "RES_FIFO", 0x1001E034, 0, 0xffffffff, 'x', "(Read Only) MMC/SD2 Response FIFO Register" },
+{ "BUFFER_ACCESS", 0x1001E038, 0, 0xffffffff, 'x', "MMC/SD2 Buffer Access Register" },
+// GPT6
+{ "TCTL6", 0x1001F000, 0, 0xffffffff, 'x', "GPT Control Register 6" },
+{ "TPRER6", 0x1001F004, 0, 0xffffffff, 'x', "GPT Prescaler Register 6" },
+{ "TCMP6", 0x1001F008, 0, 0xffffffff, 'x', "GPT Compare Register 6" },
+{ "TCR6", 0x1001F00C, 0, 0xffffffff, 'x', "GPT Capture Register 6" },
+{ "TCN6", 0x1001F010, 0, 0xffffffff, 'x', "GPT Counter Register 6" },
+{ "TSTAT6", 0x1001F014, 0, 0xffffffff, 'x', "GPT Status Register 6" },
+// AIPI2
+{ "PSR0", 0x10020000, 0, 0xffffffff, 'x', "Peripheral Size Register0" },
+{ "PSR1", 0x10020004, 0, 0xffffffff, 'x', "Peripheral Size Register1" },
+{ "PAR", 0x10020008, 0, 0xffffffff, 'x', "Peripheral Access Register" },
+{ "AAOR", 0x1002000C, 0, 0xffffffff, 'x', "Atomic Access Only Register" },
+// LCDC
+{ "LSSAR", 0x10021000, 0, 0xffffffff, 'x', "LCDC Screen Start Address Register" },
+{ "LSR", 0x10021004, 0, 0xffffffff, 'x', "LCDC Size Register" },
+{ "LVPWR", 0x10021008, 0, 0xffffffff, 'x', "LCDC Virtual Page Width Register" },
+{ "LCPR", 0x1002100C, 0, 0xffffffff, 'x', "LCDC Cursor Position Register" },
+{ "LCWHBR", 0x10021010, 0, 0xffffffff, 'x', "LCDC Cursor Width Height and Blink" },
+{ "LCCMR", 0x10021014, 0, 0xffffffff, 'x', "LCDC Color Cursor Mapping Register" },
+{ "LPCR", 0x10021018, 0, 0xffffffff, 'x', "LCDC Panel Configuration Register" },
+{ "LHCR", 0x1002101C, 0, 0xffffffff, 'x', "LCDC Horizontal Configuration Register" },
+{ "LVCR", 0x10021020, 0, 0xffffffff, 'x', "LCDC Vertical Configuration Register" },
+{ "LPOR", 0x10021024, 0, 0xffffffff, 'x', "LCDC Panning Offset Register" },
+{ "LSCR", 0x10021028, 0, 0xffffffff, 'x', "LCDC Sharp Configuration Register" },
+{ "LPCCR", 0x1002102C, 0, 0xffffffff, 'x', "LCDC PWM Contrast Control Register" },
+{ "LDCR", 0x10021030, 0, 0xffffffff, 'x', "LCDC DMA Control Register" },
+{ "LRMCR", 0x10021034, 0, 0xffffffff, 'x', "LCDC Refresh Mode Control Register" },
+{ "LICR", 0x10021038, 0, 0xffffffff, 'x', "LCDC Interrupt Configuration Register" },
+{ "LIER", 0x1002103C, 0, 0xffffffff, 'x', "LCDC Interrupt Enable Register" },
+{ "LISR", 0x10021040, 0, 0xffffffff, 'x', "LCDC Interrupt Status Register" },
+{ "LGWSAR", 0x10021050, 0, 0xffffffff, 'x', "LCDC Graphic Window Start Address Register" },
+{ "LGWSR", 0x10021054, 0, 0xffffffff, 'x', "LCDC Graphic Window Size Register" },
+{ "LGWVPWR", 0x10021058, 0, 0xffffffff, 'x', "LCDC Graphic Window Virtual Page Width" },
+{ "LGWPOR", 0x1002105C, 0, 0xffffffff, 'x', "LCDC Graphic Window Panning Offset Register" },
+{ "LGWPR", 0x10021060, 0, 0xffffffff, 'x', "LCDC Graphic Window Position Register" },
+{ "LGWCR", 0x10021064, 0, 0xffffffff, 'x', "LCDC Graphic Window Control Register" },
+{ "LGWDCR", 0x10021068, 0, 0xffffffff, 'x', "LCDC Graphic Window DMA Control Register" },
+{ "LAUSCR", 0x10021080, 0, 0xffffffff, 'x', "LCDC Aus mode Control Register" },
+{ "LAUSCCR", 0x10021084, 0, 0xffffffff, 'x', "LCDC Aus mode Cursor Control Register" },
+// SLCD Controller
+{ "DATA_BASE_ADDR", 0x10022000, 0, 0xffffffff, 'x', "SLCD Data Base Address Register" },
+{ "DATA_BUFF_SIZE", 0x10022004, 0, 0xffffffff, 'x', "SLCD Data Buffer Size Register" },
+{ "CMD_BASE_ADDR", 0x10022008, 0, 0xffffffff, 'x', "SLCD Command Buffer Base Address Register" },
+{ "CMD_BUFF_SIZE", 0x1002200C, 0, 0xffffffff, 'x', "SLCD Command Buffer Size Register" },
+{ "CMD_STR_SIZE", 0x10022010, 0, 0xffffffff, 'x', "SLCD Command String Size Register" },
+{ "FIFO_CONFIG", 0x10022014, 0, 0xffffffff, 'x', "SLCD FIFO Configuration Register" },
+{ "LCD_CONFIG", 0x10022018, 0, 0xffffffff, 'x', "SLCD Configuration Register" },
+{ "LCD_XFER_CONFIG", 0x1002201C, 0, 0xffffffff, 'x', "SLCD Transfer Configuration Register" },
+{ "DMA_CTRL_STAT", 0x10022020, 0, 0xffffffff, 'x', "SLCD DMA Control/Status Register" },
+{ "LCD_CLK_CONFIG", 0x10022024, 0, 0xffffffff, 'x', "SLCD Clock Configuration Register" },
+{ "LCD_WRITE_DATA", 0x10022028, 0, 0xffffffff, 'x', "SLCD Write Data Register" },
+// Video Codec
+{ "CodeRun", 0x10023000, 0, 0xffffffff, 'x', "BIT run start" },
+{ "CodeDownLoad", 0x10023004, 0, 0xffffffff, 'x', "Code Download Data Register" },
+{ "HostIntReq", 0x10023008, 0, 0xffffffff, 'x', "Host Interrupt Request to BI" },
+{ "BitIntClear", 0x1002300C, 0, 0xffffffff, 'x', "BIT Interrupt Clear" },
+{ "BitIntSts", 0x10023010, 0, 0xffffffff, 'x', "BIT Interrupt Status" },
+{ "WorkBufAddr", 0x10023100, 0, 0xffffffff, 'x', "Working Buffer Address in External Memory" },
+{ "CodeBufAddr", 0x10023104, 0, 0xffffffff, 'x', "Code Table Size in External Memory" },
+{ "BitStreamCtrl", 0x10023108, 0, 0xffffffff, 'x', "Bit Stream Control" },
+{ "FrameMemCtrl", 0x1002310C, 0, 0xffffffff, 'x', "Frame Memory Control" },
+{ "SramAddr", 0x10023110, 0, 0xffffffff, 'x', "Internal SRAM Base Address" },
+{ "SramSize", 0x10023114, 0, 0xffffffff, 'x', "Internal SRAM Size" },
+{ "BitStreamRdPtr", 0x10023140, 0, 0xffffffff, 'x', "Bit Stream Buffer Read Address" },
+{ "BitStreamWrPtr", 0x10023144, 0, 0xffffffff, 'x', "Bit Stream Buffer Write Address" },
+{ "FrameNum", 0x10023148, 0, 0xffffffff, 'x', "Encoded/Decoded Frame Number" },
+{ "BusyFlag", 0x10023160, 0, 0xffffffff, 'x', "Processing Busy Flag" },
+{ "RunCommand", 0x10023164, 0, 0xffffffff, 'x', "Start/Stop Codec Run Command" },
+{ "RunIndex", 0x10023168, 0, 0xffffffff, 'x', "Run Process Index" },
+{ "RunCodStd", 0x1002316C, 0, 0xffffffff, 'x', "Run Codec Standard" },
+{ "BitBufAddr", 0x10023180, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Bitstream" },
+{ "BitBufSize", 0x10023184, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Bitstream" },
+{ "FrameIntAddrY", 0x10023188, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Temporal" },
+{ "FrameIntAddrCb", 0x1002318C, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Temporal" },
+{ "FrameIntAddrCr", 0x10023190, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Temporal" },
+{ "EncCodStd", 0x10023194, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Encode" },
+{ "EncSrcFormat", 0x10023198, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Encode" },
+{ "EncMp4Para", 0x1002319C, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Encode" },
+{ "Enc263Para", 0x100231A0, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Encode" },
+{ "Enc264Para", 0x100231A4, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Encode" },
+{ "EncSliceMode", 0x100231A8, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Encode" },
+{ "EncGopNum", 0x100231AC, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Encode" },
+{ "EncPictureQs", 0x100231B0, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Encode" },
+{ "RetStatus", 0x100231C0, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Command" },
+{ "RetSrcFormat", 0x100231C4, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Decoded" },
+{ "RetMp4Info", 0x100231C8, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Decoded" },
+{ "Ret263Info", 0x100231CC, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Decoded" },
+{ "Ret264Info", 0x100231D0, 0, 0xffffffff, 'x', "Parameter Registers in sequence initialization. Decoded" },
+{ "FrameSrcAddrY", 0x10023180, 0, 0xffffffff, 'x', "Parameter Register in Processing Running. Source" },
+{ "FrameSrcAddrCb", 0x10023184, 0, 0xffffffff, 'x', "Parameter Register in Processing Running. Source" },
+{ "FrameSrcAddrCr", 0x10023188, 0, 0xffffffff, 'x', "Parameter Register in Processing Running. Source" },
+{ "FrameDecAddrY", 0x1002318C, 0, 0xffffffff, 'x', "Parameter Register in Processing Running. Decode" },
+{ "FrameDecAddrCb", 0x10023190, 0, 0xffffffff, 'x', "Parameter Register in Processing Running. Decode" },
+{ "FrameDecAddrCr", 0x10023194, 0, 0xffffffff, 'x', "Parameter Register in Processing Running. Decode" },
+{ "RetStatus", 0x100231C0, 0, 0xffffffff, 'x', "Parameter Register in Processing Running. Command" },
+// USB On The Go
+{ "UOG_ID", 0x10024000, 0, 0xffffffff, 'x', "ID (UOG_ID)" },
+{ "UOG_HWGENERAL", 0x10024004, 0, 0xffffffff, 'x', "Hardware General (UOG_HWGENERAL)" },
+{ "UOG_HWHOST", 0x10024008, 0, 0xffffffff, 'x', "Host Hardware Parameters (UOG_HWHOST)" },
+{ "UOG_HWDEVICE", 0x1002400C, 0, 0xffffffff, 'x', "Device Hardware Parameters (UOG_HWDEVICE)" },
+{ "UOG_HWTXBUF", 0x10024010, 0, 0xffffffff, 'x', "TX Buffer Hardware Parameters (UOG_HWTXBUF)" },
+{ "UOG_HWRXBUF", 0x10024014, 0, 0xffffffff, 'x', "RX Buffer Hardware Parameters (UOG_HWRXBUF)" },
+{ "GPTIMER0LD", 0x10024080, 0, 0xffffffff, 'x', "General Purpose Timer #0 Load (GPTIMER0LD)" },
+{ "GPTIMER0CTRL", 0x10024084, 0, 0xffffffff, 'x', "General Purpose Timer #0 Controller" },
+{ "GPTIMER0LD", 0x10024088, 0, 0xffffffff, 'x', "General Purpose Timer #1 Load (GPTIMER0LD)" },
+{ "GPTIMER0CTRL", 0x1002...
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