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[Armadeus-commitlog] SF.net SVN: armadeus: [773] trunk/firmware
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From: <Fa...@us...> - 2008-03-14 12:54:48
|
Revision: 773
http://armadeus.svn.sourceforge.net/armadeus/?rev=773&view=rev
Author: FabM
Date: 2008-03-14 05:54:53 -0700 (Fri, 14 Mar 2008)
Log Message:
-----------
[firmware] Wisbone simple design example
Modified Paths:
--------------
trunk/firmware/bus_led/src/bus_led.ucf
trunk/firmware/bus_led/src/bus_led_top.vhd
trunk/firmware/bus_led/testbench/led_top_tb.vhd
Added Paths:
-----------
trunk/firmware/Wisbone_example/
trunk/firmware/Wisbone_example/Makefile
trunk/firmware/Wisbone_example/README
trunk/firmware/Wisbone_example/src/
trunk/firmware/Wisbone_example/src/Wb_button.vhd
trunk/firmware/Wisbone_example/src/Wb_led.ucf
trunk/firmware/Wisbone_example/src/Wb_led.vhd
trunk/firmware/Wisbone_example/src/Wb_top.vhd
trunk/firmware/Wisbone_example/src/intercon.vhd
trunk/firmware/Wisbone_example/src/wishbone/
trunk/firmware/Wisbone_example/src/wishbone/imx_wrapper.vhd
trunk/firmware/Wisbone_example/src/wishbone/irq_mngr.vhd
trunk/firmware/Wisbone_example/src/wishbone/syscon.vhd
trunk/firmware/Wisbone_example/testbench/
trunk/firmware/Wisbone_example/testbench/Wb_top_tb.vhd
Added: trunk/firmware/Wisbone_example/Makefile
===================================================================
--- trunk/firmware/Wisbone_example/Makefile (rev 0)
+++ trunk/firmware/Wisbone_example/Makefile 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,236 @@
+# Makefile for VHDL synthesis and simulation
+# version 1.0
+# Fabien Marteau
+
+# project name
+PROJECT=Wb_top
+# vhdl files
+FILES = src/Wb_top.vhd src/Wb_button.vhd src/intercon.vhd src/wishbone/imx_wrapper.vhd src/wishbone/irq_mngr.vhd src/Wb_led.vhd src/wishbone/syscon.vhd
+# pin configuration
+UCF_FILE = src/Wb_led.ucf
+# Synthesis constraints file
+XCF_FILE =
+# testbench
+SIMTOP = wb_top_tb
+SIMFILES = ../apf_pkg/apf_test_pkg.vhd testbench/Wb_top_tb.vhd
+# Simu break condition
+GHDL_SIM_OPT = --assert-level=error
+#GHDL_SIM_OPT = --stop-time=500ns
+
+# FPGA options
+PART = xc3s200-4-tq144
+
+############################
+# Personnals options
+############################
+
+CAT=../Xtools/catcolor
+BRIEF=../Xtools/brief.py
+
+
+############################
+# Xilinx options
+############################
+BIN = bin
+WORK = work
+
+SYNTH = xst
+NGDBUILD = ngdbuild
+MAP = map
+PAR = par
+TRACE = trce
+BITGEN = bitgen
+
+ifdef $(XCF_FILE)
+XCF = -uc $(XCF_FILE)\n
+endif
+
+##############################
+# GHDL options
+##############################
+
+SIMDIR = simu
+SYNTHFILES = bin/bus_led_ise/netgen/synthesis
+
+GHDL_CMD = ghdl
+GHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic
+#GHDL_FLAGS = --ieee=synopsys -P~/Xilinx92i/coregen/ip/xilinx/primary/com/xilinx/ip/unisim --warn-no-vital-generic
+
+VIEW_CMD = /usr/bin/gtkwave
+
+OBJS_FILES = $(patsubst %.vhd, %.o, $(notdir $(FILES)) )
+OBJS_SIMFILES = $(patsubst %.vhd, %.o, $(notdir $(SIMFILES)) )
+
+#################################
+# Synthesis with xst
+#################################
+
+messages : bit
+ $(BRIEF) $(BIN)/$(PROJECT)
+
+
+bit : $(BIN)/$(PROJECT).ncd trace
+ -$(BITGEN) -intstyle xflow -w \
+ -g DebugBitstream:No \
+ -g Binary:yes \
+ -g CRC:Enable \
+ -g ConfigRate:6 \
+ -g CclkPin:PullUp \
+ -g M0Pin:PullUp \
+ -g M1Pin:PullUp \
+ -g M2Pin:PullUp \
+ -g ProgPin:PullUp \
+ -g DonePin:PullUp \
+ -g TckPin:PullUp \
+ -g TdiPin:PullUp \
+ -g TdoPin:PullUp \
+ -g TmsPin:PullUp \
+ -g UnusedPin:PullDown \
+ -g UserID:0xFFFFFFFF \
+ -g DCMShutdown:Disable \
+ -g DCIUpdateMode:AsRequired \
+ -g StartUpClk:CClk \
+ -g DONE_cycle:4 \
+ -g GTS_cycle:5 \
+ -g GWE_cycle:6 \
+ -g LCK_cycle:NoWait \
+ -g Match_cycle:Auto \
+ -g Security:None \
+ -g DonePipe:No \
+ -g DriveDone:No \
+ $(BIN)/$(PROJECT).ncd > $(BIN)/$(PROJECT).bitlog
+ $(CAT) $(BIN)/$(PROJECT).bitlog
+ -cp $(BIN)/$(PROJECT).bit /tftpboot/
+ -cp $(BIN)/$(PROJECT).bin /tftpboot/
+
+trace: $(BIN)/$(PROJECT).ncd $(BIN)/$(PROJECT).pcf
+ -$(TRACE) -intstyle xflow -e 3 -l 3 -s 4 -xml $(BIN)/$(PROJECT) $(BIN)/$(PROJECT).ncd -o $(BIN)/$(PROJECT).twr $(BIN)/$(PROJECT).pcf
+ $(CAT) $(BIN)/$(PROJECT).tracelog
+
+$(BIN)/$(PROJECT).ncd : par
+
+par : $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).pcf
+ - sh -c 'pid=$$$$; $(PAR) -w -intstyle xflow -ol std -t 1 $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).ncd $(BIN)/$(PROJECT).pcf | (sed "/^PAR done/q";kill $$pid)' > $(BIN)/$(PROJECT).parlog
+ $(CAT) $(BIN)/$(PROJECT).parlog
+ - killall -9 par
+
+$(BIN)/$(PROJECT).pcf $(BIN)/$(PROJECT)_map.ncd : map
+
+map : $(BIN)/$(PROJECT).ngd
+ - sh -c 'pid=$$$$ ; $(MAP) -intstyle xflow -p $(PART) -cm area -pr b -k 4 -c 100 -o $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).ngd $(BIN)/$(PROJECT).pcf | (sed "/^See MAP report file/q" ; kill $$pid ) ' > $(BIN)/$(PROJECT).maplog
+ $(CAT) $(BIN)/$(PROJECT).maplog
+ - killall -9 map
+
+$(BIN)/$(PROJECT).ngd : ngdbuild
+
+ngdbuild : $(BIN)/$(PROJECT).ngr $(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).lso
+ -$(NGDBUILD) -intstyle xflow -dd _ngo -nt timestamp -p $(PART) $(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).ngd -uc $(UCF_FILE) > $(BIN)/$(PROJECT).ngdlog
+ $(CAT) $(BIN)/$(PROJECT).ngdlog
+
+$(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).ngr $(BIN)/$(PROJECT).lso : synthesis
+
+synthesis : $(BIN)/$(PROJECT).prj $(BIN)/$(PROJECT).xst
+ $(SYNTH) -ifn $(BIN)/$(PROJECT).xst -ofn $(BIN)/$(PROJECT).log \
+ | sed "s/^ERROR/[01\;31mERROR[00m/"\
+ | sed "s/^WARNING/[01\;33mWARNING[00m/"\
+ | sed "s/^INFO/[01\;32mINFO[0m/"
+
+$(BIN)/$(PROJECT).xst $(BIN)/$(PROJECT).prj :
+ @mkdir -p $(BIN)
+ @touch $(BIN)/$(PROJECT);
+ @for f in $(FILES); do \
+ echo vhdl $(WORK) \"$$f\" >> $(BIN)/$(PROJECT).prj;\
+ done
+ @echo work > $(BIN)/$(PROJECT).lso
+ @mkdir -p ./bin/xst/projnav.tmp
+ @echo " \
+ set -tmpdir "./bin/xst/projnav.tmp" \n\
+ set -xsthdpdir "./bin/xst" \n\
+ run \n\
+ -ifn $(BIN)/$(PROJECT).prj \n\
+ -ifmt mixed \n\
+ -ofn $(BIN)/$(PROJECT) \n\
+ -ofmt NGC \n\
+ -p $(PART) \n\
+ -top $(PROJECT) \n\
+ -opt_mode Speed \n\
+ -opt_level 1 \n\
+ $(XCF)\
+ -iuc NO \n\
+ -lso $(BIN)/$(PROJECT).lso \n\
+ -keep_hierarchy NO \n\
+ -rtlview Yes \n\
+ -glob_opt AllClockNets \n\
+ -read_cores YES \n\
+ -write_timing_constraints NO \n\
+ -cross_clock_analysis NO \n\
+ -hierarchy_separator / \n\
+ -bus_delimiter <> \n\
+ -case maintain \n\
+ -slice_utilization_ratio 100 \n\
+ -bram_utilization_ratio 100 \n\
+ -verilog2001 YES \n\
+ -fsm_extract YES -fsm_encoding Auto \n\
+ -safe_implementation No \n\
+ -fsm_style lut \n\
+ -ram_extract Yes \n\
+ -ram_style Auto \n\
+ -rom_extract Yes \n\
+ -mux_style Auto \n\
+ -decoder_extract YES \n\
+ -priority_extract YES \n\
+ -shreg_extract YES \n\
+ -shift_extract YES \n\
+ -xor_collapse YES \n\
+ -rom_style Auto \n\
+ -auto_bram_packing NO \n\
+ -mux_extract YES \n\
+ -resource_sharing YES \n\
+ -async_to_sync NO \n\
+ -mult_style auto \n\
+ -iobuf YES \n\
+ -max_fanout 500 \n\
+ -bufg 8 \n\
+ -register_duplication YES \n\
+ -register_balancing No \n\
+ -slice_packing YES \n\
+ -optimize_primitives NO \n\
+ -use_clock_enable Yes \n\
+ -use_sync_set Yes \n\
+ -use_sync_reset Yes \n\
+ -iob auto \n\
+ -equivalent_register_removal YES \n\
+ -slice_utilization_ratio_maxmargin 5\n\
+ " >> $(BIN)/$(PROJECT).xst
+
+clean : ghdl-clean
+ -rm -rf $(BIN)
+ -rm -rf _ngo
+ -rm xilinx_device_details.xml
+
+########################
+# Simulation with GHDL
+########################
+
+ghdl-compil :
+ mkdir -p simu
+ $(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES)
+ $(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simu --work=work $(SIMTOP)
+ @mv $(SIMTOP) simu/$(SIMTOP)
+
+#TODO: make it working !
+ghdl-simsynth :
+ $(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simu --work=work $(SYNTHFILES) $(SIMFILES)
+ $(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simu --work=work $(SIMTOP)
+ @mv $(SIMTOP) simu/$(SIMTOP)
+
+ghdl-run :
+ @$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
+
+ghdl-view:
+ gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd
+
+ghdl-clean :
+ $(GHDL_CMD) --clean --workdir=simu
+ -rm -rf simu
+
Added: trunk/firmware/Wisbone_example/README
===================================================================
--- trunk/firmware/Wisbone_example/README (rev 0)
+++ trunk/firmware/Wisbone_example/README 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,22 @@
+This project is an exemple for wishbone interface . There are three Wb slaves :
+
+* irq_mngr : this slave joins irq from others wishbone IP and
+ send it to i.mx processor.To manage these irq
+ two registers are available :
+ irq_mask ( addr : 0x0000) : enable irq writing 1
+ irq_pend/irq_ack (addr : 0x0002) : writing 1 acknowledge irq
+ and reading 1 inform that an irq pending.
+ This design use one irq for button push and release.
+
+* Wb_led : a simple led register, one led is branched on register LSB.
+ To switch on led write '0' on led register. Address register
+ is :
+ LED (addr : 0x0004)
+* Wb_button: Simple button register, when button is pressed, register LSB
+ is '0', and when it's release LSB is '1'. On each switching
+ an interuption is send to irq_mngr.
+ button (addr : 0x0008)
+
+see
+http://www.armadeus.com/wiki/index.php?title=FpgaArchitecture#La_composition_du_syst.C3.A8me_Wishbone
+(french) for more information about designing wishbone IP.
Added: trunk/firmware/Wisbone_example/src/Wb_button.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/Wb_button.vhd (rev 0)
+++ trunk/firmware/Wisbone_example/src/Wb_button.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,87 @@
+---------------------------------------------------------------------------
+-- Company : ARMades Systems
+-- Author(s) : Fabien Marteau <fab...@ar...>
+--
+-- Creation Date : 10/03/2008
+-- File : Wb_button.vhd
+--
+-- Abstract :
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity Wb_button is
+---------------------------------------------------------------------------
+ port
+ (
+ -- global signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ -- Wishbone signals
+-- wbs_writedata : in std_logic_vector( 15 downto 0);
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- irq
+ wbs_irq_s : out std_logic ;
+ -- fpga input
+ button : in std_logic
+ );
+end entity;
+
+
+---------------------------------------------------------------------------
+Architecture Wb_button_1 of Wb_button is
+ ---------------------------------------------------------------------------
+ signal button_r : std_logic ;
+ signal reg : std_logic_vector( 15 downto 0);
+begin
+
+ -- connect button
+ cbutton : process(gls_clk,gls_reset)
+ begin
+ if gls_reset = '1' then
+ reg <= (others => '0');
+ elsif rising_edge(gls_clk) then
+ reg <= "000000000000000"&button;
+ end if;
+ end process cbutton;
+
+
+ -- rise interruption
+ pbutton : process(gls_clk,gls_reset)
+ begin
+ if gls_reset = '1' then
+ wbs_irq_s <= '0';
+ button_r <= '0';
+ elsif rising_edge(gls_clk) then
+ if button_r /= button then
+ wbs_irq_s <= '1';
+ else
+ wbs_irq_s <= '0';
+ end if;
+ button_r <= button;
+ end if;
+ end process pbutton;
+
+ -- register reading process
+ pread : process(gls_clk,gls_reset)
+ begin
+ if(gls_reset = '1') then
+ wbs_ack <= '0';
+ wbs_readdata <= (others => '0');
+ elsif(falling_edge(gls_clk)) then
+ wbs_ack <= '1';
+ if(wbs_strobe = '1' and wbs_write = '0')then
+ wbs_readdata <= reg;
+ end if;
+ end if;
+ end process pread;
+
+end architecture Wb_button_1;
+
Added: trunk/firmware/Wisbone_example/src/Wb_led.ucf
===================================================================
--- trunk/firmware/Wisbone_example/src/Wb_led.ucf (rev 0)
+++ trunk/firmware/Wisbone_example/src/Wb_led.ucf 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,58 @@
+# Clock at 96MHz
+NET "clk" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 10.42 ns HIGH 50 %;
+
+# IMX controls
+NET "imx_cs_n" LOC = "P59" | IOSTANDARD = LVCMOS33;
+NET "imx_eb3_n" LOC = "P60" | IOSTANDARD = LVCMOS33;
+NET "imx_oe_n" LOC = "P63" | IOSTANDARD = LVCMOS33;
+
+# IMX interruption
+NET "imx_irq" LOC = "P68" | IOSTANDARD = LVCMOS33;
+
+# IMX address bus
+NET "imx_addr<1>" LOC = "P23" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<2>" LOC = "P24" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<3>" LOC = "P25" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<4>" LOC = "P26" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<5>" LOC = "P27" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<6>" LOC = "P28" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<7>" LOC = "P30" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<8>" LOC = "P31" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<9>" LOC = "P32" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<10>" LOC = "P33" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<11>" LOC = "P35" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<12>" LOC = "P36" | IOSTANDARD = LVCMOS33;
+
+# IMX data bus
+NET "imx_data<0>" LOC = "P1" | IOSTANDARD = LVCMOS33;
+NET "imx_data<1>" LOC = "P2" | IOSTANDARD = LVCMOS33;
+NET "imx_data<2>" LOC = "P4" | IOSTANDARD = LVCMOS33;
+NET "imx_data<3>" LOC = "P5" | IOSTANDARD = LVCMOS33;
+NET "imx_data<4>" LOC = "P6" | IOSTANDARD = LVCMOS33;
+NET "imx_data<5>" LOC = "P7" | IOSTANDARD = LVCMOS33;
+NET "imx_data<6>" LOC = "P8" | IOSTANDARD = LVCMOS33;
+NET "imx_data<7>" LOC = "P10" | IOSTANDARD = LVCMOS33;
+NET "imx_data<8>" LOC = "P11" | IOSTANDARD = LVCMOS33;
+NET "imx_data<9>" LOC = "P12" | IOSTANDARD = LVCMOS33;
+NET "imx_data<10>" LOC = "P13" | IOSTANDARD = LVCMOS33;
+NET "imx_data<11>" LOC = "P14" | IOSTANDARD = LVCMOS33;
+NET "imx_data<12>" LOC = "P15" | IOSTANDARD = LVCMOS33;
+NET "imx_data<13>" LOC = "P17" | IOSTANDARD = LVCMOS33;
+NET "imx_data<14>" LOC = "P18" | IOSTANDARD = LVCMOS33;
+NET "imx_data<15>" LOC = "P20" | IOSTANDARD = LVCMOS33;
+
+###############################################
+# fpga specific
+###############################################
+
+# led output
+NET "LED" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
+# Button input
+NET "button" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
+
+# Test (X10 on devfull) connection
+#NET "imx_data0_test" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
+#NET "imx_addr1_test" LOC = "P97" | IOSTANDARD = LVCMOS33 ;
+
Added: trunk/firmware/Wisbone_example/src/Wb_led.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/Wb_led.vhd (rev 0)
+++ trunk/firmware/Wisbone_example/src/Wb_led.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,64 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 05/03/2008
+-- File : Wb_led.vhd
+--
+-- Abstract : drive one led with Wishbone bus
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-----------------------------------------------------------------------
+ Entity Wb_led is
+-----------------------------------------------------------------------
+ port
+ (
+ -- Syscon signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ -- Wishbone signals
+ wbs_writedata : in std_logic_vector( 15 downto 0);
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- out signals
+ LED : out std_logic
+ );
+end entity;
+
+
+-----------------------------------------------------------------------
+Architecture Wb_led_1 of Wb_led is
+-----------------------------------------------------------------------
+ signal reg : std_logic_vector( 15 downto 0);
+begin
+
+-- connect led
+LED <= reg(0);
+
+-- manage register
+reg_bloc : process(gls_clk,gls_reset)
+begin
+ if gls_reset = '1' then
+ reg <= (others => '0');
+ elsif rising_edge(gls_clk) then
+ if ((wbs_strobe and wbs_write) = '1' ) then
+ reg <= wbs_writedata;
+ else
+ reg <= reg;
+ end if;
+ end if;
+
+end process reg_bloc;
+
+wbs_ack <= wbs_strobe;
+wbs_readdata <= reg;
+
+end architecture Wb_led_1;
+
Added: trunk/firmware/Wisbone_example/src/Wb_top.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/Wb_top.vhd (rev 0)
+++ trunk/firmware/Wisbone_example/src/Wb_top.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,371 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau (fab...@ar...)
+--
+-- Creation Date : 05/03/2008
+-- File : Wb_top.vhd
+--
+-- Abstract :
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity Wb_top is
+---------------------------------------------------------------------------
+port
+(
+ -- imx EIM connexion
+ imx_addr : in std_logic_vector( 12 downto 0);
+ imx_data : inout std_logic_vector( 15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ -- clock
+ clk : in std_logic ;
+ -- fpga specific
+ LED : out std_logic;
+ button : in std_logic ;
+
+ -- irq
+ imx_irq : out std_logic
+
+);
+end entity;
+
+
+---------------------------------------------------------------------------
+Architecture Wb_top_1 of Wb_top is
+---------------------------------------------------------------------------
+ component imx_wrapper
+ port (
+ -- i.MX Signals
+ imx_address : in std_logic_vector(12 downto 1);
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_oe_n : in std_logic;
+ imx_eb3_n : in std_logic;
+
+ -- Global Signals
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
+
+ -- Wishbone interface signals
+ wbm_address : out std_logic_vector(12 downto 0); -- Address bus
+ wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
+ wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
+ wbm_strobe : out std_logic; -- Data Strobe
+ wbm_write : out std_logic; -- Write access
+ wbm_sel : out std_logic_vector(1 downto 0); -- select LSB or/and MSB byte
+ wbm_ack : in std_logic ;
+ wbm_cycle : out std_logic -- bus cycle in progress
+ );
+ end component;
+
+ component syscon
+ port(
+ -- external signals
+ ext_clk : in std_logic ;
+ ext_reset : in std_logic ;
+ --internal signals
+ gls_clk : out std_logic ;
+ gls_reset : out std_logic
+ );
+ end component;
+
+ component intercon
+ port (
+ -- imx wishbone master connexion
+ gls_reset_m1 : out std_logic ;
+ gls_clk_m1 : out std_logic ;
+
+ wbm_address_m1 : in std_logic_vector( 12 downto 0);
+ wbm_readdata_m1 : out std_logic_vector( 15 downto 0);
+ wbm_writedata_m1 : in std_logic_vector( 15 downto 0);
+ wbm_strobe_m1 : in std_logic ;
+ wbm_write_m1 : in std_logic ;
+ wbm_sel_m1 : in std_logic_vector( 1 downto 0);
+ wbm_ack_m1 : out std_logic ;
+ wbm_cycle_m1 : in std_logic ;
+
+ -- led wishbone slave connexion
+ gls_reset_s1 : out std_logic ;
+ gls_clk_s1 : out std_logic ;
+ wbs_writedata_s1 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s1 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s1 : out std_logic ;
+ wbs_write_s1 : out std_logic ;
+ wbs_ack_s1 : in std_logic ;
+
+ -- button slave connexion
+ gls_reset_s2 : out std_logic ;
+ gls_clk_s2 : out std_logic ;
+-- wbs_writedata_s2 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s2 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s2 : out std_logic ;
+ wbs_write_s2 : out std_logic ;
+ wbs_ack_s2 : in std_logic ;
+
+ wbs_irq_s2 : in std_logic ;
+
+ -- irq slave connexion
+ gls_reset_s3 : out std_logic ;
+ gls_clk_s3 : out std_logic ;
+ wbs_address_s3 : out std_logic ;
+ wbs_writedata_s3 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s3 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s3 : out std_logic ;
+ wbs_write_s3 : out std_logic ;
+ wbs_ack_s3 : in std_logic ;
+ wbs_irq_s3 : out std_logic;
+
+ -- syscon connection
+ gls_reset_sys : in std_logic ;
+ gls_clk_sys : in std_logic
+ );
+ end component intercon;
+
+ component Wb_led
+ port(
+ -- Syscon signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+ -- Wishbone signals
+ wbs_writedata : in std_logic_vector( 15 downto 0);
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic;
+ -- out signals
+ LED : out std_logic
+ );
+ end component;
+
+ component Wb_button
+ port (
+ -- global signals
+ gls_reset : in std_logic ;
+ gls_clk : in std_logic ;
+-- wbs_writedata : in std_logic_vector( 15 downto 0);
+ wbs_readdata : out std_logic_vector( 15 downto 0);
+ wbs_strobe : in std_logic ;
+ wbs_write : in std_logic ;
+ wbs_ack : out std_logic ;
+
+ -- irq
+ wbs_irq_s : out std_logic ;
+
+ -- fpga input
+ button : in std_logic
+ );
+ end component;
+
+ component irq_mngr
+ generic
+ (
+ irq_count : integer := 1;
+ irq_level : std_logic := '1'
+ );
+ port (
+ -- Global Signals
+ gls_clk : in std_logic;
+ gls_reset : in std_logic;
+
+ -- Wishbone interface signals
+ wbs_s1_address : in std_logic; -- Address bus
+ wbs_s1_readdata : out std_logic_vector(15 downto 0); -- Data bus for read access
+ wbs_s1_writedata : in std_logic_vector(15 downto 0); -- Data bus for write access
+ wbs_s1_ack : out std_logic; -- Access acknowledge
+ wbs_s1_strobe : in std_logic; -- Data Strobe
+ wbs_s1_write : in std_logic; -- Write access
+ -- irq from other IP
+ wbs_s1_irq : in std_logic_vector(irq_count-1 downto 0);
+
+ -- Component external signals
+ gls_irq : out std_logic -- IRQ request
+ );
+ end component irq_mngr;
+
+ -- irq_mngr connection signal
+ signal gls_clk_s3 : std_logic ;
+ signal gls_reset_s3 : std_logic ;
+ signal wbs_address_s3 : std_logic ;
+ signal wbs_readdata_s3 : std_logic_vector(15 downto 0);
+ signal wbs_writedata_s3: std_logic_vector( 15 downto 0);
+ signal wbs_ack_s3 : std_logic ;
+ signal wbs_strobe_s3 : std_logic ;
+ signal wbs_write_s3 : std_logic ;
+ signal wbs_irq_s3 : std_logic;
+
+ -- button connection signal
+ signal gls_reset_s2 : std_logic ;
+ signal gls_clk_s2 : std_logic ;
+ signal wbs_readdata_s2 : std_logic_vector(15 downto 0);
+--signal wbs_writedata_s2: std_logic_vector( 15 downto 0);
+ signal wbs_ack_s2 : std_logic ;
+ signal wbs_strobe_s2 : std_logic ;
+ signal wbs_write_s2 : std_logic ;
+
+ signal wbs_irq_s2 : std_logic ;
+
+ -- imx_wrapper connection signals
+ signal gls_reset_m1 : std_logic ;
+ Signal gls_clk_m1 : std_logic ;
+ signal wbm_address_m1 : std_logic_vector( 12 downto 0);
+ Signal wbm_readdata_m1 : std_logic_vector( 15 downto 0);
+ Signal wbm_writedata_m1 : std_logic_vector( 15 downto 0);
+ Signal wbm_strobe_m1 : std_logic ;
+ signal wbm_write_m1 : std_logic ;
+ Signal wbm_sel_m1 : std_logic_vector( 1 downto 0);
+ signal wbm_ack_m1 : std_logic ;
+ Signal wbm_cycle_m1 : std_logic ;
+
+ -- led connection signals
+ Signal gls_reset_s1 : std_logic ;
+ Signal gls_clk_s1 : std_logic ;
+ Signal wbs_writedata_s1 : std_logic_vector( 15 downto 0);
+ Signal wbs_readdata_s1 : std_logic_vector( 15 downto 0);
+ Signal wbs_strobe_s1 : std_logic ;
+ Signal wbs_write_s1 : std_logic ;
+ Signal wbs_ack_s1 : std_logic ;
+
+ -- syscon connection signals
+ Signal gls_reset_sys : std_logic ;
+ Signal gls_clk_sys : std_logic ;
+
+
+begin
+
+ connect_imx_wrapper : imx_wrapper
+ port map (
+ imx_address => imx_addr(12 downto 1),
+ imx_data => imx_data,
+ imx_cs_n => imx_cs_n,
+ imx_oe_n => imx_oe_n,
+ imx_eb3_n => imx_eb3_n,
+
+ gls_reset => gls_reset_m1,
+ gls_clk => gls_clk_m1,
+
+ wbm_address => wbm_address_m1,
+ wbm_readdata => wbm_readdata_m1,
+ wbm_writedata => wbm_writedata_m1,
+ wbm_strobe => wbm_strobe_m1,
+ wbm_write => wbm_write_m1,
+ wbm_sel => wbm_sel_m1,
+ wbm_ack => wbm_ack_m1,
+ wbm_cycle => wbm_cycle_m1
+ );
+
+ connect_Wb_led : Wb_led
+ port map (
+ gls_reset => gls_reset_s1,
+ gls_clk => gls_clk_s1,
+
+ wbs_writedata => wbs_writedata_s1,
+ wbs_readdata => wbs_readdata_s1,
+ wbs_strobe => wbs_strobe_s1,
+ wbs_write => wbs_write_s1,
+ wbs_ack => wbs_ack_s1,
+
+ LED => LED
+ );
+
+ connect_syscon : syscon
+ port map (
+ ext_clk => clk,
+ ext_reset => '0',
+
+ gls_clk => gls_clk_sys,
+ gls_reset => gls_reset_sys
+ );
+
+ connect_intercon : intercon
+ port map (
+ -- imx_wrapper connexion
+ gls_reset_m1 => gls_reset_m1,
+ gls_clk_m1 => gls_clk_m1,
+ wbm_address_m1 => wbm_address_m1,
+ wbm_readdata_m1 => wbm_readdata_m1,
+ wbm_writedata_m1 => wbm_writedata_m1,
+ wbm_strobe_m1 => wbm_strobe_m1,
+ wbm_write_m1 => wbm_write_m1,
+ wbm_sel_m1 => wbm_sel_m1,
+ wbm_ack_m1 => wbm_ack_m1,
+ wbm_cycle_m1 => wbm_cycle_m1,
+ -- led connexion
+ gls_reset_s1 => gls_reset_s1,
+ gls_clk_s1 => gls_clk_s1,
+ wbs_writedata_s1 => wbs_writedata_s1,
+ wbs_readdata_s1 => wbs_readdata_s1,
+ wbs_strobe_s1 => wbs_strobe_s1,
+ wbs_write_s1 => wbs_write_s1,
+ wbs_ack_s1 => wbs_ack_s1,
+ -- button connexion
+ gls_reset_s2 => gls_reset_s2,
+ gls_clk_s2 => gls_clk_s2,
+-- wbs_writedata_s2 => wbs_writedata_s2,
+ wbs_readdata_s2 => wbs_readdata_s2,
+ wbs_strobe_s2 => wbs_strobe_s2,
+ wbs_write_s2 => wbs_write_s2,
+ wbs_ack_s2 => wbs_ack_s2,
+
+ wbs_irq_s2 => wbs_irq_s2,
+ -- irq connexion
+ gls_reset_s3 => gls_reset_s3,
+ gls_clk_s3 => gls_clk_s3,
+ wbs_address_s3 => wbs_address_s3,
+ wbs_writedata_s3 => wbs_writedata_s3,
+ wbs_readdata_s3 => wbs_readdata_s3,
+ wbs_strobe_s3 => wbs_strobe_s3,
+ wbs_write_s3 => wbs_write_s3,
+ wbs_ack_s3 => wbs_ack_s3,
+ wbs_irq_s3 => wbs_irq_s3,
+ -- global signals
+ gls_reset_sys => gls_reset_sys,
+ gls_clk_sys => gls_clk_sys
+ );
+
+ connect_button : Wb_button
+ port map (
+ -- global signals
+ gls_reset => gls_reset_s2,
+ gls_clk => gls_clk_s2,
+-- wbs_writedata => wbs_writedata_s2,
+ wbs_readdata => wbs_readdata_s2,
+ wbs_strobe => wbs_strobe_s2,
+ wbs_write => wbs_write_s2,
+ wbs_ack => wbs_ack_s2,
+
+ -- irq
+ wbs_irq_s => wbs_irq_s2,
+
+ -- fpga input
+ button => button
+ );
+
+ connect_irq_mngr : irq_mngr
+ port map (
+ -- Global Signals
+ gls_clk => gls_clk_s3,
+ gls_reset => gls_reset_s3,
+
+ -- Wishbone interface signals
+ wbs_s1_address => wbs_address_s3, -- Address bus
+ wbs_s1_readdata => wbs_readdata_s3, -- Data bus for read access
+ wbs_s1_writedata => wbs_writedata_s3, -- Data bus for write access
+ wbs_s1_ack => wbs_ack_s3, -- Access acknowledge
+ wbs_s1_strobe => wbs_strobe_s3, -- Data Strobe
+ wbs_s1_write => wbs_write_s3, -- Write access
+ -- irq from other IP
+ wbs_s1_irq(0) => wbs_irq_s3,
+
+ -- Component external signals
+ gls_irq => imx_irq
+ );
+
+end architecture Wb_top_1;
+
Added: trunk/firmware/Wisbone_example/src/intercon.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/intercon.vhd (rev 0)
+++ trunk/firmware/Wisbone_example/src/intercon.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,150 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 05/03/2008
+-- File : intercon.vhd
+--
+-- Abstract : connect master wishbone device with
+-- slave(s) wishbone device
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity intercon is
+---------------------------------------------------------------------------
+ port
+ (
+ -- imx wishbone master connexion
+ gls_reset_m1 : out std_logic ;
+ gls_clk_m1 : out std_logic ;
+
+ wbm_address_m1 : in std_logic_vector( 12 downto 0);
+ wbm_readdata_m1 : out std_logic_vector( 15 downto 0);
+ wbm_writedata_m1 : in std_logic_vector( 15 downto 0);
+ wbm_strobe_m1 : in std_logic ;
+ wbm_write_m1 : in std_logic ;
+ wbm_sel_m1 : in std_logic_vector( 1 downto 0);
+ wbm_ack_m1 : out std_logic ;
+ wbm_cycle_m1 : in std_logic ;
+
+ -- led wishbone slave connexion
+ gls_reset_s1 : out std_logic ;
+ gls_clk_s1 : out std_logic ;
+ wbs_writedata_s1 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s1 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s1 : out std_logic ;
+ wbs_write_s1 : out std_logic ;
+ wbs_ack_s1 : in std_logic ;
+
+ -- button slave connexion
+ gls_reset_s2 : out std_logic ;
+ gls_clk_s2 : out std_logic ;
+ wbs_readdata_s2 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s2 : out std_logic ;
+ wbs_write_s2 : out std_logic ;
+ wbs_ack_s2 : in std_logic ;
+
+ wbs_irq_s2 : in std_logic ;
+
+ -- irq slave connexion
+ gls_reset_s3 : out std_logic ;
+ gls_clk_s3 : out std_logic ;
+ wbs_address_s3 : out std_logic ;
+ wbs_writedata_s3 : out std_logic_vector( 15 downto 0);
+ wbs_readdata_s3 : in std_logic_vector( 15 downto 0);
+ wbs_strobe_s3 : out std_logic ;
+ wbs_write_s3 : out std_logic ;
+ wbs_ack_s3 : in std_logic ;
+ wbs_irq_s3 : out std_logic ;
+
+ -- syscon connection
+ gls_reset_sys : in std_logic ;
+ gls_clk_sys : in std_logic
+ );
+end entity;
+
+---------------------------------------------------------------------------
+Architecture intercon_1 of intercon is
+---------------------------------------------------------------------------
+ signal led_cs : std_logic ;
+ signal button_cs : std_logic ;
+ signal irq_cs : std_logic ;
+ signal cs :std_logic_vector( 2 downto 0);
+begin
+
+ -- clock and reset management
+ gls_reset_s1 <= gls_reset_sys;
+ gls_clk_s1 <= gls_clk_sys;
+
+ gls_reset_s2 <= gls_reset_sys;
+ gls_clk_s2 <= gls_clk_sys;
+
+ gls_reset_s3 <= gls_reset_sys;
+ gls_clk_s3 <= gls_clk_sys;
+
+ gls_reset_m1 <= gls_reset_sys;
+ gls_clk_m1 <= gls_clk_sys;
+
+ -----------------------------
+ -- master => slave connexions
+ -----------------------------
+ -- address decode
+ irq_cs <= '1' when wbm_address_m1 = "0000000000000" or wbm_address_m1 = "0000000000010"
+ else '0';
+ led_cs <= '1' when wbm_address_m1 = "0000000000100"
+ else '0';
+ button_cs <= '1' when wbm_address_m1 = "0000000001000"
+ else '0';
+
+ wbs_address_s3 <= wbm_address_m1(1);
+
+ -- control signals
+ -- for led (s1)
+ wbs_writedata_s1 <= wbm_writedata_m1 when (wbm_write_m1 and led_cs)='1'
+ else (others => '0');
+ wbs_strobe_s1 <= (wbm_strobe_m1 and led_cs);
+ wbs_write_s1 <= (wbm_write_m1 and led_cs);
+ -- for button(s2) read only
+ wbs_strobe_s2 <= (wbm_strobe_m1 and button_cs);
+ wbs_write_s2 <= '0';
+
+ -- for irq (s3)
+ wbs_writedata_s3 <= wbm_writedata_m1 when (wbm_write_m1 and irq_cs)='1'
+ else (others => '0');
+ wbs_strobe_s3 <= (wbm_strobe_m1 and irq_cs);
+ wbs_write_s3 <= (wbm_write_m1 and irq_cs);
+
+ -----------------------------
+ -- slave => master connexions
+ -----------------------------
+ cs(0) <= led_cs;
+ cs(1) <= button_cs;
+ cs(2) <= irq_cs;
+
+ with cs select
+ wbm_readdata_m1 <= wbs_readdata_s1 when "001",
+ wbs_readdata_s2 when "010",
+ wbs_readdata_s3 when "100",
+ (others => '0') when others;
+ with cs select
+ wbm_ack_m1 <= wbs_ack_s1 when "001",
+ wbs_ack_s2 when "010",
+ wbs_ack_s3 when "100",
+ '0' when others;
+
+
+ -- irq management
+ wbs_irq_s3 <= wbs_irq_s2;
+
+ -- open connexion
+-- wbm_sel_m1 => open;
+-- wbm_cycle_m1 => open;
+-- wbs_ack_s1 => open;
+
+end architecture intercon_1;
+
Added: trunk/firmware/Wisbone_example/src/wishbone/imx_wrapper.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/wishbone/imx_wrapper.vhd (rev 0)
+++ trunk/firmware/Wisbone_example/src/wishbone/imx_wrapper.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,96 @@
+-------------------------------------------------------------------------------
+--
+-- File : imx_wrapper.vhd
+-- Related files : (none)
+--
+-- Author(s) : Fabrice Mousset (fab...@la...)
+-- Project : i.MX wrapper to Wishbone bus
+--
+-- Creation Date : 2007/01/19
+--
+-- Description : This is the top file of the IP
+-------------------------------------------------------------------------------
+-- Modifications :
+-----
+-- 2008/03/05
+-- Fabien Marteau (fab...@ar...)
+-- adding comments and changing some signals names
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+
+-- ----------------------------------------------------------------------------
+ Entity imx_wrapper is
+-- ----------------------------------------------------------------------------
+ port
+ (
+ -- i.MX Signals
+ imx_address : in std_logic_vector(12 downto 1);
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_oe_n : in std_logic;
+ imx_eb3_n : in std_logic;
+
+ -- Global Signals
+ gls_reset : in std_logic;
+ gls_clk : in std_logic;
+
+ -- Wishbone interface signals
+ wbm_address : out std_logic_vector(12 downto 0); -- Address bus
+ wbm_readdata : in std_logic_vector(15 downto 0); -- Data bus for read access
+ wbm_writedata : out std_logic_vector(15 downto 0); -- Data bus for write access
+ wbm_strobe : out std_logic; -- Data Strobe
+ wbm_write : out std_logic; -- Write access
+ wbm_sel : out std_logic_vector(1 downto 0); -- select LSB or/and MSB byte
+ wbm_ack : in std_logic ; -- acknowledge
+ wbm_cycle : out std_logic -- bus cycle in progress
+ );
+ end entity;
+
+-- ----------------------------------------------------------------------------
+ Architecture RTL of imx_wrapper is
+-- ----------------------------------------------------------------------------
+
+signal write : std_logic;
+signal read : std_logic;
+signal sel : std_logic_vector(1 downto 0);
+signal strobe : std_logic;
+signal writedata : std_logic_vector(15 downto 0);
+signal address : std_logic_vector(12 downto 0);
+
+begin
+
+-- ----------------------------------------------------------------------------
+-- External signals synchronization process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ write <= '0';
+ read <= '0';
+ sel <= "00";
+ strobe <= '0';
+ writedata <= (others => '0');
+ address <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ strobe <= not (imx_cs_n) and not(imx_oe_n and imx_eb3_n);
+ write <= not (imx_cs_n or imx_eb3_n);
+ read <= not (imx_cs_n or imx_oe_n);
+ address <= imx_address & '0';
+ writedata <= imx_data;
+ end if;
+end process;
+
+wbm_address <= address when (strobe = '1') else (others => '0');
+wbm_writedata <= writedata when (write = '1') else (others => '0');
+wbm_strobe <= strobe;
+wbm_write <= write;
+wbm_sel <= strobe & strobe;
+wbm_cycle <= strobe;
+
+imx_data <= wbm_readdata when(read = '1') else (others => 'Z');
+
+end architecture RTL;
Added: trunk/firmware/Wisbone_example/src/wishbone/irq_mngr.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/wishbone/irq_mngr.vhd (rev 0)
+++ trunk/firmware/Wisbone_example/src/wishbone/irq_mngr.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,142 @@
+-------------------------------------------------------------------------------
+--
+-- File : irq_mnrg.vhd
+-- Related files : (none)
+--
+-- Author(s) : Fabrice Mousset (fab...@la...)
+-- Project : Wishbone Interruption Manager
+--
+-- Creation Date : 2007/01/05
+--
+-- Description : This is the top file of the IP
+-------------------------------------------------------------------------------
+-- Modifications :
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+ use IEEE.std_logic_1164.all;
+ use IEEE.numeric_std.all;
+
+-- ----------------------------------------------------------------------------
+ Entity irq_mngr is
+-- ----------------------------------------------------------------------------
+ generic
+ (
+ irq_count : integer := 16;
+ irq_level : std_logic := '1'
+ );
+ port
+ (
+ -- Global Signals
+ gls_clk : in std_logic;
+ gls_reset : in std_logic;
+
+ -- Wishbone interface signals
+ wbs_s1_address : in std_logic; -- Address bus
+ wbs_s1_readdata : out std_logic_vector(15 downto 0); -- Data bus for read access
+ wbs_s1_writedata : in std_logic_vector(15 downto 0); -- Data bus for write access
+ wbs_s1_ack : out std_logic; -- Access acknowledge
+ wbs_s1_strobe : in std_logic; -- Data Strobe
+ wbs_s1_write : in std_logic; -- Write access
+ -- irq from other IP
+ wbs_s1_irq : in std_logic_vector(irq_count-1 downto 0);
+
+ -- Component external signals
+ gls_irq : out std_logic -- IRQ request
+ );
+ end entity;
+
+-- ----------------------------------------------------------------------------
+ Architecture RTL of irq_mngr is
+-- ----------------------------------------------------------------------------
+
+signal irq_r : std_logic_vector(irq_count-1 downto 0);
+signal irq_pend : std_logic_vector(irq_count-1 downto 0);
+signal irq_ack : std_logic_vector(irq_count-1 downto 0);
+signal irq_mask : std_logic_vector(irq_count-1 downto 0);
+
+signal readdata : std_logic_vector(15 downto 0);
+
+signal rd_ack : std_logic;
+signal wr_ack : std_logic;
+
+begin
+
+-- ----------------------------------------------------------------------------
+-- External signals synchronization process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ irq_r <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ irq_r <= wbs_s1_irq;
+ end if;
+end process;
+
+-- ----------------------------------------------------------------------------
+-- Interruption requests latching process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ irq_pend <= (others => '0');
+ elsif(rising_edge(gls_clk)) then
+ irq_pend <= ((irq_pend or (irq_r and irq_mask)) and not (irq_ack));
+ end if;
+end process;
+
+-- ----------------------------------------------------------------------------
+-- Register reading process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ rd_ack <= '0';
+ readdata <= (others => '0');
+ elsif(falling_edge(gls_clk)) then
+ rd_ack <= '0';
+
+ if(wbs_s1_strobe = '1' and wbs_s1_write = '0') then
+ rd_ack <= '1';
+ if(wbs_s1_address = '0') then
+ readdata(irq_count-1 downto 0) <= irq_mask;
+ else
+ readdata(irq_count-1 downto 0) <= irq_pend;
+ end if;
+ end if;
+ end if;
+end process;
+
+-- ----------------------------------------------------------------------------
+-- Register update process
+-- ----------------------------------------------------------------------------
+process(gls_clk, gls_reset)
+begin
+ if(gls_reset='1') then
+ irq_ack <= (others => '0');
+ wr_ack <= '0';
+ irq_mask <= (others => '0');
+ elsif(falling_edge(gls_clk)) then
+ irq_ack <= (others => '0');
+ wr_ack <= '0';
+
+ if(wbs_s1_strobe = '1' and wbs_s1_write = '1') then
+ wr_ack <= '1';
+ if(wbs_s1_address = '0') then
+ irq_mask <= wbs_s1_writedata(irq_count-1 downto 0);
+ else
+ irq_ack <= wbs_s1_writedata(irq_count-1 downto 0);
+ end if;
+ end if;
+ end if;
+end process;
+
+gls_irq <= irq_level when(unsigned(irq_pend) /= 0 and gls_reset = '0') else
+ not irq_level;
+
+wbs_s1_ack <= rd_ack or wr_ack;
+wbs_s1_readdata <= readdata when (wbs_s1_strobe = '1' and wbs_s1_write = '0') else (others => 'Z');
+
+end architecture RTL;
Added: trunk/firmware/Wisbone_example/src/wishbone/syscon.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/wishbone/syscon.vhd (rev 0)
+++ trunk/firmware/Wisbone_example/src/wishbone/syscon.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,56 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 05/03/2008
+-- File : syscon.vhd
+--
+-- Abstract :
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity syscon is
+---------------------------------------------------------------------------
+port
+(
+ -- external signals
+ ext_clk : in std_logic ;
+ ext_reset : in std_logic ;
+ --internal signals
+ gls_clk : out std_logic ;
+ gls_reset : out std_logic
+);
+end entity;
+
+
+---------------------------------------------------------------------------
+Architecture syscon_1 of syscon is
+---------------------------------------------------------------------------
+
+signal dly: std_logic := '0';
+signal rst: std_logic := '0';
+
+begin
+----------------------------------------------------------------------------
+-- RESET signal generator.
+----------------------------------------------------------------------------
+process(ext_clk)
+begin
+ if(rising_edge(ext_clk)) then
+ dly <= ( not(ext_reset) and dly and not(rst) )
+ or ( not(ext_reset) and not(dly) and rst );
+
+ rst <= ( not(ext_reset) and not(dly) and not(rst) );
+ end if;
+end process;
+
+gls_clk <= ext_clk;
+gls_reset <= rst;
+
+end architecture syscon_1;
+
Added: trunk/firmware/Wisbone_example/testbench/Wb_top_tb.vhd
===================================================================
--- trunk/firmware/Wisbone_example/testbench/Wb_top_tb.vhd (rev 0)
+++ trunk/firmware/Wisbone_example/testbench/Wb_top_tb.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -0,0 +1,157 @@
+----------------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 14/02/2008
+-- File : led_top_tb.vhd
+--
+-- Abstract : Testbench for simple design that switch a led with the imx
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+use ieee.std_logic_arith.all;
+
+--library SIMPRIM;
+--use SIMPRIM.VCOMPONENTS.ALL;
+--use SIMPRIM.VPACKAGE.ALL;
+
+use work.apf_test_pkg.ALL;
+----------------------------------------------------------------------------------
+Entity Wb_top_tb is
+----------------------------------------------------------------------------------
+ end entity Wb_top_tb;
+
+
+----------------------------------------------------------------------------------
+Architecture RTL of Wb_top_tb is
+ ----------------------------------------------------------------------------------
+
+ CONSTANT HALF_PERIODE : time := 5 ns; -- Half clock period
+
+ signal imx_data : std_logic_vector(15 downto 0);
+ signal imx_addr : std_logic_vector (12 downto 0);
+ signal imx_cs_n : std_logic ;
+ signal imx_eb3_n : std_logic ;
+ signal imx_oe_n : std_logic ;
+ signal clk : std_logic ;
+ signal LED : std_logic ;
+ signal imx_irq : std_logic ;
+ signal button : std_logic ;
+
+ component Wb_top
+ port (
+ -- imx EIM connexion
+ imx_addr : in std_logic_vector( 12 downto 0);
+ imx_data : inout std_logic_vector( 15 downto 0);
+ imx_cs_n : in std_logic;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ -- clock
+ clk : in std_logic ;
+ -- fpga specific
+ LED : out std_logic;
+ button : in std_logic ;
+ -- irq
+ imx_irq : out std_logic
+ );
+ end component Wb_top;
+begin
+
+ connect_Wb_led : Wb_top
+ port map(imx_data => imx_data,
+ imx_addr => imx_addr,
+ imx_cs_n => imx_cs_n,
+ imx_eb3_n => imx_eb3_n,
+ imx_oe_n => imx_oe_n,
+ clk => clk,
+ LED => LED,
+ button => button,
+ imx_irq => imx_irq);
+
+ -- test read/write
+ stimulus : process
+ variable value : std_logic_vector (15 downto 0);
+ begin
+ imx_oe_n <= '1';
+ imx_eb3_n <= '1';
+ imx_cs_n <= '1';
+ imx_addr <= (others => 'Z');
+ imx_data <= (others => 'Z');
+ button <= '0';
+
+ wait for HALF_PERIODE*10;
+
+ -- reset irq_pend
+ imx_write(x"0002",x"0000",
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ -- write on irq_mask
+ imx_write(x"0004",x"ffff",
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ -- read led value
+ imx_read(x"0000",value,
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ assert value(0) = '0' report "Wrong led value" severity error;
+
+ -- push button
+ button <= '1';
+ wait for HALF_PERIODE*20;
+ assert imx_irq = '1' report "IRQ not raised" severity error;
+ -- read button value
+ imx_read(x"0008",value,
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ assert value(0) = '1' report "Failed to read button" severity error;
+
+ -- Read irq pending
+ imx_read(x"0002",value,
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ assert value(0) = '1' report "IRQ pending error" severity error;
+ -- Acknowledge irq
+ imx_write(x"0002",x"ffff",
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ imx_read(x"0002",value,
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ assert value(0) = '0' report "Acknowledge error" severity error;
+
+ -- release button
+ button <= '0';
+ wait for HALF_PERIODE*20;
+ -- Acknowledge irq
+ imx_write(x"0002",x"ffff",
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ imx_read(x"0002",value,
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ --read button value
+ imx_read(x"0008",value,
+ clk,imx_cs_n,imx_oe_n,
+ imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ assert value(0) = '0' report "Low read button error" severity error;
+
+
+
+
+ wait for HALF_PERIODE*10;
+ assert false report "End of test" severity error;
+ end process stimulus;
+
+ -- 100MHz Clock
+ Clockp : process
+ begin
+ clk <= '1';
+ wait for HALF_PERIODE;
+ clk <= '0';
+ wait for HALF_PERIODE;
+ end process Clockp;
+
+end architecture RTL;
Modified: trunk/firmware/bus_led/src/bus_led.ucf
===================================================================
--- trunk/firmware/bus_led/src/bus_led.ucf 2008-03-13 12:26:00 UTC (rev 772)
+++ trunk/firmware/bus_led/src/bus_led.ucf 2008-03-14 12:54:53 UTC (rev 773)
@@ -3,12 +3,13 @@
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10.42 ns HIGH 50 %;
+# IMX control
NET "imx_cs_n" LOC = "P59" | IOSTANDARD = LVCMOS33;
NET "imx_eb3_n" LOC = "P60" | IOSTANDARD = LVCMOS33;
NET "imx_oe_n" LOC = "P63" | IOSTANDARD = LVCMOS33;
-NET "LED" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
+# IMX address bus
NET "imx_addr<1>" LOC = "P23" | IOSTANDARD = LVCMOS33;
NET "imx_addr<2>" LOC = "P24" | IOSTANDARD = LVCMOS33;
NET "imx_addr<3>" LOC = "P25" | IOSTANDARD = LVCMOS33;
@@ -22,7 +23,7 @@
NET "imx_addr<11>" LOC = "P35" | IOSTANDARD = LVCMOS33;
NET "imx_addr<12>" LOC = "P36" | IOSTANDARD = LVCMOS33;
-# IMX connection
+# IMX data bus
NET "imx_data<0>" LOC = "P1" | IOSTANDARD = LVCMOS33;
NET "imx_data<1>" LOC = "P2" | IOSTANDARD = LVCMOS33;
NET "imx_data<2>" LOC = "P4" | IOSTANDARD = LVCMOS33;
@@ -40,6 +41,13 @@
NET "imx_data<14>" LOC = "P18" | IOSTANDARD = LVCMOS33;
NET "imx_data<15>" LOC = "P20" | IOSTANDARD = LVCMOS33;
+###############################################
+# fpga specific
+###############################################
+
+# led output
+NET "LED" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
+
# Test (X10 on devfull) connection
NET "imx_data0_test" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
NET "imx_addr1_test" LOC = "P97" | IOSTANDARD = LVCMOS33 ;
Modified: trunk/firmware/bus_led/src/bus_led_top.vhd
===================================================================
--- trunk/firmware/bus_led/src/bus_led_top.vhd 2008-03-13 12:26:00 UTC (rev 772)
+++ trunk/firmware/bus_led/src/bus_led_top.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -27,15 +27,15 @@
entity bus_led_top
is
port (
- imx_data : inout std_logic_vector(15 downto 0);
- imx_data0_test : out std_logic;
- imx_addr1_test : out std_logic ;
- imx_addr : in std_logic_vector(12 downto 1);
- imx_cs_n : in std_logic ;
- imx_eb3_n : in std_logic ;
- imx_oe_n : in std_logic ;
- clk : in std_logic ;
- LED : out std_logic);
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_data0_test : out std_logic;
+ imx_addr1_test : out std_logic ;
+ imx_addr : in std_logic_vector(12 downto 1);
+ imx_cs_n : in std_logic ;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ clk : in std_logic ;
+ LED : out std_logic);
end entity bus_led_top ;
@@ -43,14 +43,14 @@
of bus_led_top is
component bus_led
port(
- imx_data : inout std_logic_vector(15 downto 0);
- imx_addr : in std_logic_vector(12 downto 1);
- imx_cs_n : in std_logic ;
- imx_eb3_n : in std_logic ;
- imx_oe_n : in std_logic ;
- clk : in std_logic ;
- LED : out std_logic ;
- Rst_n : in std_logic);
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_addr : in std_logic_vector(12 downto 1);
+ imx_cs_n : in std_logic ;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ clk : in std_logic ;
+ LED : out std_logic ;
+ Rst_n : in std_logic);
end component;
-- Asynchrone reset active low
@@ -63,14 +63,14 @@
connect_bus_led : bus_led
port map(
- imx_data => imx_data,
- imx_addr => imx_addr,
- imx_cs_n => imx_cs_n,
- imx_eb3_n => imx_eb3_n,
- imx_oe_n => imx_oe_n,
- clk => clk,
- LED => LED,
- Rst_n => Rst_n);
+ imx_data => imx_data,
+ imx_addr => imx_addr,
+ imx_cs_n => imx_cs_n,
+ imx_eb3_n => imx_eb3_n,
+ imx_oe_n => imx_oe_n,
+ clk => clk,
+ LED => LED,
+ Rst_n => Rst_n);
end architecture ;
Modified: trunk/firmware/bus_led/testbench/led_top_tb.vhd
===================================================================
--- trunk/firmware/bus_led/testbench/led_top_tb.vhd 2008-03-13 12:26:00 UTC (rev 772)
+++ trunk/firmware/bus_led/testbench/led_top_tb.vhd 2008-03-14 12:54:53 UTC (rev 773)
@@ -13,8 +13,13 @@
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
+
+library SIMPRIM;
+use SIMPRIM.VCOMPONENTS.ALL;
+use SIMPRIM.VPACKAGE.ALL;
+
use work.apf_test_pkg.ALL;
-
+use simprim.all;
----------------------------------------------------------------------------------
Entity led_top_tb is
----------------------------------------------------------------------------------
@@ -50,8 +55,21 @@
clk : in std_logic ;
LED : out std_logic );
end component bus_led_top;
+begin
-begin
+ connect_bus_led : bus_led_top
+ port map(
+ imx_data => imx_data,
+ imx_data0_test => imx_data0_test,
+ imx_addr1_test => imx_addr1_test,
+ imx_addr => imx_addr,
+ imx_cs_n => imx_cs_n,
+ imx_eb3_n => imx_eb3_n,
+ imx_oe_n => imx_oe_n,
+ clk => clk,
+ LED => LED);
+
+
-- Test stimulus
stimulus : process
variable value : std_logic_vector (15 downto 0);
@@ -72,6 +90,7 @@
clk,imx_cs_n,imx_oe_n,
imx_eb3_n,imx_addr(12 downto 1),imx_data);
assert value = conv_std_logic_vector(i,16) report "error reading imx_data" severity error;
+ assert false report "faux" severity error;
end loop;
assert false report "End of test" severity error;
@@ -86,19 +105,4 @@
wait for HALF_PERIODE;
end process Clockp;
- connect_bus_led : bus_led_top
- port map(
- imx_data => imx_data,
- imx_data0_test => imx_data0_test,
- imx_addr1_test => imx_addr1_test,
- imx_addr => imx_addr,
- imx_cs_n => imx_cs_n,
- imx_eb3_n => imx_eb3_n,
- imx_oe_n => imx_oe_n,
- clk => clk,
- LED => LED);
-
--- Rst_n => Rst_n);
-
end architecture RTL;
-
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