[Armadeus-commitlog] SF.net SVN: armadeus: [765] trunk/firmware

[<Fa...@us...>]

Revision: 765
          http://armadeus.svn.sourceforge.net/armadeus/?rev=765&view=rev
Author:   FabM
Date:     2008-03-03 08:12:47 -0800 (Mon, 03 Mar 2008)

Log Message:
-----------
[FIRMWARE] bus_led synchronized

Modified Paths:
--------------
    trunk/firmware/Xtools/brief.py
    trunk/firmware/apf_pkg/apf_test_pkg.vhd
    trunk/firmware/bus_led/Makefile
    trunk/firmware/bus_led/src/bus_led.ucf
    trunk/firmware/bus_led/src/bus_led.vhd
    trunk/firmware/bus_led/testbench/led_top_tb.vhd

Modified: trunk/firmware/Xtools/brief.py
===================================================================
--- trunk/firmware/Xtools/brief.py	2008-03-03 13:19:41 UTC (rev 764)
+++ trunk/firmware/Xtools/brief.py	2008-03-03 16:12:47 UTC (rev 765)
@@ -43,7 +43,7 @@
 file.close()
 print '---------------------------------------------------'
 print ' trace messages :'
-file = open(sys.argv[1] + ".tracelog",'r')
+file = open(sys.argv[1] + ".twr",'r')
 report(file)
 file.close()
 print '---------------------------------------------------'

Modified: trunk/firmware/apf_pkg/apf_test_pkg.vhd
===================================================================
--- trunk/firmware/apf_pkg/apf_test_pkg.vhd	2008-03-03 13:19:41 UTC (rev 764)
+++ trunk/firmware/apf_pkg/apf_test_pkg.vhd	2008-03-03 16:12:47 UTC (rev 765)
@@ -10,7 +10,7 @@
 use ieee.std_logic_1164.all;
 
 package apf_test_pkg is
-	   -- read and write procedures
+	-- read and write procedures
 	procedure imx_write(
 	address     : in std_logic_vector (15 downto 0);
 	value       : in std_logic_vector (15 downto 0);
@@ -23,14 +23,14 @@
 );
 
 procedure imx_read(
-	address     : in std_logic_vector (15 downto 0);
-	value       : out std_logic_vector (15 downto 0);
-	signal   gls_clk     : in std_logic ;
-	signal   imx_cs_n    : out std_logic ;
-	signal   imx_oe_n    : out std_logic ;
-	signal   imx_eb3_n   : out std_logic ;
-	signal   imx_address : out std_logic_vector (12 downto 1);
-	signal   imx_data    : in std_logic_vector (15 downto 0)
+address     : in std_logic_vector (15 downto 0);
+value       : out std_logic_vector (15 downto 0);
+signal   gls_clk     : in std_logic ;
+signal   imx_cs_n    : out std_logic ;
+signal   imx_oe_n    : out std_logic ;
+signal   imx_eb3_n   : out std_logic ;
+signal   imx_address : out std_logic_vector (12 downto 1);
+signal   imx_data    : in std_logic_vector (15 downto 0)
    );
 
 
@@ -38,7 +38,7 @@
 
 package body apf_test_pkg is
 
-	   -- Write value from imx
+	-- Write value from imx
 	procedure imx_write(
 	address     : in std_logic_vector (15 downto 0);
 	value       : in std_logic_vector (15 downto 0);
@@ -50,7 +50,7 @@
 	signal   imx_data    : out std_logic_vector (15 downto 0)
 ) is
 begin
-					   -- Write value
+	-- Write value
 	wait until falling_edge(gls_clk);
 	wait for 4 ns;
 	imx_address <= address(12 downto 1);
@@ -68,19 +68,19 @@
 	imx_data  <= (others => 'Z');
 end procedure imx_write;
 
-			   -- Read a value from imx
+-- Read a value from imx
 procedure imx_read(
-address     : in std_logic_vector (15 downto 0);
-value       : out std_logic_vector (15 downto 0);
-signal   gls_clk     : in std_logic ;
-signal   imx_cs_n    : out std_logic ;
-signal   imx_oe_n    : out std_logic ;
-signal   imx_eb3_n   : out std_logic ;
-signal   imx_address : out std_logic_vector (12 downto 1);
-signal   imx_data    : in std_logic_vector (15 downto 0)
+					address     : in std_logic_vector (15 downto 0);
+					value       : out std_logic_vector (15 downto 0);
+					signal   gls_clk     : in std_logic ;
+					signal   imx_cs_n    : out std_logic ;
+					signal   imx_oe_n    : out std_logic ;
+					signal   imx_eb3_n   : out std_logic ;
+					signal   imx_address : out std_logic_vector (12 downto 1);
+					signal   imx_data    : in std_logic_vector (15 downto 0)
 					   ) is
 					   begin
-							   -- Read value
+						   -- Read value
 						   wait until falling_edge(gls_clk);
 						   wait for 4 ns;
 						   imx_address <= address(12 downto 1);

Modified: trunk/firmware/bus_led/Makefile
===================================================================
--- trunk/firmware/bus_led/Makefile	2008-03-03 13:19:41 UTC (rev 764)
+++ trunk/firmware/bus_led/Makefile	2008-03-03 16:12:47 UTC (rev 765)
@@ -103,7 +103,7 @@
 	cp $(BIN)/$(PROJECT).bit /tftpboot/
 
 trace: $(BIN)/$(PROJECT).ncd $(BIN)/$(PROJECT).pcf
-	-$(TRACE) -intstyle xflow -e 3 -l 3 -s 5 -xml $(BIN)/$(PROJECT) $(BIN)/$(PROJECT).ncd -o $(BIN)/$(PROJECT).twr $(BIN)/$(PROJECT).pcf > $(BIN)/$(PROJECT).tracelog 
+	-$(TRACE) -intstyle xflow -e 3 -l 3 -s 5 -xml $(BIN)/$(PROJECT) $(BIN)/$(PROJECT).ncd -o $(BIN)/$(PROJECT).twr $(BIN)/$(PROJECT).pcf 
 	$(CAT) $(BIN)/$(PROJECT).tracelog
 
 $(BIN)/$(PROJECT).ncd : par 

Modified: trunk/firmware/bus_led/src/bus_led.ucf
===================================================================
--- trunk/firmware/bus_led/src/bus_led.ucf	2008-03-03 13:19:41 UTC (rev 764)
+++ trunk/firmware/bus_led/src/bus_led.ucf	2008-03-03 16:12:47 UTC (rev 765)
@@ -1,7 +1,7 @@
 # Clock at 96MHz
 NET "clk"    LOC = "P55"  | IOSTANDARD = LVCMOS33 ;  
 NET "clk" TNM_NET = "clk";
-TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
+TIMESPEC "TS_clk" = PERIOD "clk" 10.42 ns HIGH 50 %;
 
 NET "imx_cs_n"      LOC = "P59"  | IOSTANDARD = LVCMOS33; 
 NET "imx_eb3_n"  		LOC = "P60"  | IOSTANDARD = LVCMOS33; 

Modified: trunk/firmware/bus_led/src/bus_led.vhd
===================================================================
--- trunk/firmware/bus_led/src/bus_led.vhd	2008-03-03 13:19:41 UTC (rev 764)
+++ trunk/firmware/bus_led/src/bus_led.vhd	2008-03-03 16:12:47 UTC (rev 765)
@@ -36,51 +36,69 @@
 ---------------------------------------------------------------------------
 Architecture RTL of bus_led is
 	---------------------------------------------------------------------------
-	signal Reg  : std_logic_vector(15 downto 0) := (others => '0');
+	signal Reg        : std_logic_vector(15 downto 0) := (others => '0');
+	signal address    : std_logic_vector(11 downto 0);
+	signal readdata   : std_logic_vector(15 downto 0);
+	signal writedata  : std_logic_vector(15 downto 0);
+	signal read       : std_logic;
+	signal write      : std_logic;
 
 begin
 
 	-- Led connection
 	LED <= Reg(0);
 
-	write : process (clk,Rst_n)
+	imx_data <= readdata when (read = '1') else (others => 'Z');  
+
+	-----------------------------------------------------
+	-- Synchro external signal
+	-----------------------------------------------------
+	sync_proc : process(clk, rst_n)
+	 begin
+	   if Rst_n = '0' then
+	     address <= (others => '0');
+	     read    <= '0';
+	     write   <= '0';
+	   elsif rising_edge(clk) then
+	     write     <= not (imx_cs_n or imx_eb3_n);
+	     read      <= not (imx_cs_n or imx_oe_n);
+	     address   <= imx_addr;
+	     writedata <= imx_data;
+	   end if;
+	 end process;
+
+	writeprocess : process (clk,Rst_n)
 	begin
 		if Rst_n = '0' then
 			Reg    <= (others => '0');
 		elsif rising_edge(clk) then
-			if (imx_cs_n = '0' and	imx_oe_n = '1' and imx_eb3_n = '0' ) then
-				case imx_addr is
+			if (write = '1') then
+				case address is
 					when "000000000000" => 
 						-- Save imx_data value in Reg
-						Reg <= imx_data;
-					when others => 
-						Reg <= Reg;
+						Reg <= writedata;
+					when others => Null; 
 				end case;
-
 			end if;
 		end if;
-	end process write;
+	end process writeprocess;
 
-	read : process (clk, Rst_n)
+	readprocess : process (clk, Rst_n)
 	begin
 		if Rst_n = '0' then
-			imx_data <= (others => 'Z');
-		elsif falling_edge(clk) then
-			if(imx_cs_n = '0' and imx_oe_n = '0' and imx_eb3_n = '1' ) then
-				case imx_addr is
+			readdata <= (others => '0');
+		elsif rising_edge(clk) then
+			readdata <= (others => '0');
+			if(read = '1') then
+				case address is
 					when "000000000000" => 
 					-- Write Reg value on imx_data bus
-						imx_data <= Reg;
-					when others => 
-					-- High impedance if others address
-						imx_data <= (others => 'Z');
+						readdata <= Reg;
+					when others => Null; 
 				end case;
-			else
-					-- High impedance if others address
-				imx_data <= (others => 'Z');
 			end if;
 		end if;
-	end process read;
+	end process readprocess;
 
 end architecture RTL;
 

Modified: trunk/firmware/bus_led/testbench/led_top_tb.vhd
===================================================================
--- trunk/firmware/bus_led/testbench/led_top_tb.vhd	2008-03-03 13:19:41 UTC (rev 764)
+++ trunk/firmware/bus_led/testbench/led_top_tb.vhd	2008-03-03 16:12:47 UTC (rev 765)
@@ -65,8 +65,12 @@
 		wait for HALF_PERIODE*20;
 
 		for i in 0 to 600 loop
-			imx_write(x"0000",conv_std_logic_vector(i,16),clk,imx_cs_n,imx_oe_n,imx_eb3_n,imx_addr(12 downto 1),imx_data);
-			imx_read(x"0000",value,clk,imx_cs_n,imx_oe_n,imx_eb3_n,imx_addr(12 downto 1),imx_data);
+			imx_write(x"0000",conv_std_logic_vector(i,16),
+						clk,imx_cs_n,imx_oe_n,
+						imx_eb3_n,imx_addr(12 downto 1),imx_data);
+			imx_read(x"0000",value,
+						clk,imx_cs_n,imx_oe_n,
+						imx_eb3_n,imx_addr(12 downto 1),imx_data);
 			assert value = conv_std_logic_vector(i,16) report "error reading imx_data" severity error;
 		end loop;
 


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